Commit Graph

180 Commits

Author SHA1 Message Date
Awais Abbas 54d4f30592 OpenFPGA Documentation updated for yosys only support 2022-01-14 16:14:48 +05:00
nadeemyaseen-rs 1ea56b2d18 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-18 00:00:55 +05:00
Aram Kostanyan a355977420 Adding Yosys+Verific support. 2021-10-29 18:34:27 +05:00
tangxifan 57159fc121 [Doc] Update documentation for the new syntax in configuration protocol and fabric key file format 2021-10-10 17:46:45 -07:00
tangxifan 40b589dc6d [Doc] Update documentation about the clock definition for programming clocks in simulation settings 2021-10-06 13:50:33 -07:00
tangxifan 03bcf6dee5 [Doc] Update documenation for the new option ``--keep_dont_care_bits`` 2021-10-05 19:23:42 -07:00
tangxifan ff339312f6 [Doc] Update documentation about the limitations of multi-region configuration protocols 2021-10-05 11:55:10 -07:00
tangxifan 9a7e0f761a [Doc] Add fabric bitstream file format for QL memory bank 2021-10-04 12:29:49 -07:00
tangxifan a01fa7c282 [Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank 2021-10-04 12:09:42 -07:00
tangxifan b0a97a7052 [Doc] Update doc about WLR usage for QL memory bank 2021-09-27 10:24:04 -07:00
tangxifan f9bceff33a [Doc] Update documentation for the flatten BL/WL protocols 2021-09-25 20:44:45 -07:00
tangxifan 10774dc15c [Doc] Updated documentation about new syntax in fabric key 2021-09-21 17:01:52 -07:00
tangxifan d9d959709c [Doc] Add missing figures 2021-09-20 20:31:53 -07:00
tangxifan 3146d2484f [Doc] Update documentation on the WLR definition for circuit model 2021-09-20 17:21:33 -07:00
tangxifan 73d21c9730 [Doc] Update doc about how to use the QuickLogic memory bank 2021-09-10 15:30:37 -07:00
tangxifan 43afaca17c [Doc] Add more details about the new syntax 2021-07-01 23:51:54 -06:00
tangxifan 0851075bc9 [Doc] Update documentation about the new feature in pin constraint file 2021-07-01 23:47:36 -06:00
tangxifan ac9046b7d2 [Doc] Remove ``define_simulation.v`` since it is no longer needed. 2021-06-29 15:38:35 -06:00
tangxifan 30027b8c15 [Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init' 2021-06-25 15:27:15 -06:00
tangxifan 11d0283771 [Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream' 2021-06-25 15:11:12 -06:00
tangxifan 507f5ee54c [Doc] Update documentation about time unit support in writing simulation file 2021-06-25 10:34:43 -06:00
tangxifan 8e2ba718d0 [Doc] update documentation on the new option '--testbench_type' 2021-06-25 10:16:48 -06:00
tangxifan 779437cd37 [Doc] Update documentation to remove out-of-date options related to signal_init 2021-06-24 17:07:15 -06:00
tangxifan 9585e1d3b5 [Doc] Update documentation about 'default_net_type' option in testbench generators 2021-06-14 14:00:34 -06:00
tangxifan b719419931 [Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command 2021-06-09 16:59:02 -06:00
tangxifan 54a53bc988 [Doc] Update documentation on the minor changes on bitstream file for memory bank protocol 2021-06-07 17:58:00 -06:00
tangxifan 0fee741008 [Doc] Update documentation on the minor changes on fabric bitstream file format 2021-06-07 14:22:35 -06:00
tangxifan c30be6e95e [Doc] Update documentation about the fast configuration for write bitstream command 2021-06-04 20:00:28 -06:00
tangxifan 059e74b4ef [Doc] Add --fast configuration option to documentation for 'write_full_testbench' 2021-06-04 15:17:00 -06:00
tangxifan b83d8826fb [Doc] Update documentation on the testbench organization/waveforms 2021-06-03 16:54:13 -06:00
tangxifan 9bcaa820ae [Doc] Update documentation for the new command 'write_full_testbench' 2021-06-03 16:18:07 -06:00
tangxifan 9b40e74e25 [Doc] Add example circuit models for multipliers and update technical highlight with links to the examples 2021-05-24 15:24:50 -06:00
tangxifan 21a18069a1 [Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples 2021-05-24 14:50:55 -06:00
tangxifan b6b98a75b8 [Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model; 2021-05-24 13:03:40 -06:00
tangxifan 24f83f0058 [Doc] Update documentation about the new command 'report_bitstream_distribution' 2021-05-07 11:54:33 -06:00
tangxifan 1bae59dc6a [Doc] Update documentation for the write_io_mapping command 2021-04-27 14:54:57 -06:00
tangxifan 62dc5a3856 [Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes 2021-04-24 16:02:24 -06:00
tangxifan 2e1cc5499d [Doc] Add disclaimer for limitations when using repack pin constraints 2021-04-21 14:14:54 -06:00
tangxifan 9b3dcc65bd [Doc] Add new bitstream setting syntex 'interconnect' to documentation 2021-04-19 16:37:21 -06:00
tangxifan e5b47b7d3d [Doc] Update documentation on the changes on fabric bitstream file formats 2021-04-10 15:45:39 -06:00
tangxifan 19b2641839
Merge branch 'master' into doc_patch 2021-03-15 11:45:32 -06:00
tangxifan fb7d76545e [Doc] Patch the schematic of LUT circuit models to be consistent with netlists 2021-03-15 11:40:09 -06:00
tangxifan ff0faeb285 [Doc] Update documentation about the extended bitstream setting 2021-03-10 21:41:59 -07:00
tangxifan c638e5bde5 [Doc] Update documentation for default net type option 2021-02-28 12:00:55 -07:00
tangxifan 01b9bf2a02 [Doc] Update num_region XML for config protocol 2021-02-18 21:58:30 -07:00
tangxifan 1c4dc9f74b [Doc] Update documentation about the super LUT feature 2021-02-10 11:49:59 -07:00
tangxifan 9c5368f912 [Doc] Correct bugs in compiling latexpdf 2021-02-07 16:17:54 -07:00
AurelienAlacchi 00fc3d7622
Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
tangxifan 9b5c64f35f [Doc] Update documentation about disable_packing syntax 2021-02-04 16:41:24 -07:00
tangxifan d83158654c [Doc] Add a draft documentation about the bitstream setting 2021-02-01 22:33:17 -07:00
tangxifan 0e16638dc2 [Doc] Update documentation about the changes on activity files 2021-01-29 11:49:07 -07:00
tangxifan 78ad9cd000 [Doc] Add version command/option to documentation 2021-01-27 16:06:45 -07:00
tangxifan d53d3963d4 [Doc] Broken link fix in config protocol documentation 2021-01-26 14:05:11 -07:00
tangxifan 9fefe1502f [Doc] Typo fix on write_fabric_key option 2021-01-25 15:18:16 -07:00
tangxifan dd0680246a [Doc] Typo fix on fabric key command 2021-01-25 14:12:40 -07:00
ganeshgore 1ba7e0663f
Merge pull request #176 from lnis-uofu/dev
Documentation Formatting
2021-01-24 21:11:49 -07:00
tangxifan e18c533657 [Doc] Add new openfpga shell command to documentation 2021-01-24 14:48:56 -07:00
tangxifan 815468ac65 [Doc] Add shortcut to call pin constraint option to documentation 2021-01-20 09:20:51 -07:00
tangxifan 977ff52cb1 [Doc] Format openfpga command documentation by using option views 2021-01-19 20:26:38 -07:00
tangxifan e9dc708d66 [Doc] Group file format documentation into a unified section 2021-01-19 19:44:44 -07:00
tangxifan ac8c63553a [Doc] Add file format index file 2021-01-19 18:07:53 -07:00
tangxifan fbb5c0cf8f [Doc] Add pin constraints to documentation 2021-01-19 18:04:45 -07:00
tangxifan c7f02601ab [Doc] Add repack design constraints to documentation 2021-01-17 12:59:46 -07:00
tangxifan c4d3e7c50c [Doc] Update documentation for the new XML syntax in simulation settings 2021-01-15 12:30:26 -07:00
tangxifan 0c808bec41 [Doc] Add clarification for defining multi-bit global tile ports 2021-01-09 20:00:16 -07:00
tangxifan 2324edc522 [Doc] Update documentation for upgraded tile annotation 2021-01-09 18:55:16 -07:00
tangxifan 226f6b8d6d [Doc] Update documentation about FF circuit models to show capability in modeling SCFFs 2021-01-04 18:30:04 -07:00
tangxifan 406edeec89 [Doc] Typo fix 2020-12-04 15:07:02 -07:00
tangxifan 4fe190fa7e [Doc] Bug fix in LUT circuit model documentation 2020-12-04 14:44:27 -07:00
tangxifan 8350b0f911 [Doc] Update documentation about default value definition in tile annotation 2020-12-02 17:08:34 -07:00
tangxifan cc0114459a [Doc] Enrich examples for LUT circuit models 2020-11-26 13:03:12 -07:00
tangxifan 62e804215b [Doc] Add svg figures for LUT examples 2020-11-26 12:35:39 -07:00
tangxifan b857135f4e [Doc] Add clarification about which cells are applicable for signal initialization 2020-11-23 15:19:15 -07:00
tangxifan 2b9a97729e [Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models 2020-11-23 15:09:47 -07:00
tangxifan fd0e6814ea [Doc] Update documentation about the pre-processing flags 2020-11-22 20:33:15 -07:00
tangxifan f6126d1ed6 [Doc] Add illustrative example to diff between global ports definitions 2020-11-12 09:24:39 -07:00
tangxifan bc43c876b0 [Doc] Update documentation for the rules in global port definition for tile ports 2020-11-11 14:10:11 -07:00
tangxifan 2c269c532a [Doc] Update doc for the global port definition using physical tile port 2020-11-10 20:48:28 -07:00
tangxifan 056b7c0c79 [Doc] Update documentation about CCFF circuit model examples 2020-11-06 12:22:22 -07:00
tangxifan 849ecc7fc0 [Doc] Add notes for using the is_data_io syntax 2020-11-05 09:30:19 -07:00
tangxifan 9bce2f3818 [Doc] Update documentation for new XML syntax "is_data_io" 2020-11-05 09:28:46 -07:00
tangxifan be7f7592ae [Doc] Update documentation about don't care bit in frame address 2020-10-30 22:13:28 -06:00
tangxifan 7e940980e1 [Doc] Update documentation about configuration regions for frame-based protocol 2020-10-30 21:52:01 -06:00
tangxifan c2c384e24b [Doc] update documentation about memory bank definition 2020-10-29 17:04:25 -06:00
tangxifan 3aeea724de [Documentation] Update for new options in fpga-verilog 2020-10-12 12:36:24 -06:00
tangxifan ccaa697e5a [Documentation] Add links to technical features to examples 2020-10-10 22:40:37 -06:00
tangxifan 56ab63d939 [Documentation] Fix format in table 2020-10-06 12:02:15 -06:00
tangxifan 113708c68f [Documentation] Reorganization the overview part by adding technical highlights 2020-10-06 11:56:10 -06:00
tangxifan 67300af987 [Documentation] Update motivation with new set of figures 2020-09-29 16:52:16 -06:00
tangxifan 639d57016b [Documentation] Update documentation about the multi-region configuration 2020-09-29 15:55:42 -06:00
tangxifan 462886fb5f [Documentation] Update documentation for the multiple region support on configuration chain 2020-09-29 14:02:03 -06:00
tangxifan 94a1324f05 [Documentation] Remove deprecated XML syntax 2020-09-26 14:31:57 -06:00
tangxifan f57fd273af [Documentation] Update documentation for smart fast configuration 2020-09-23 21:28:06 -06:00
tangxifan 3d234d840b [Documentation] Update documentation for the edge triggered attribute 2020-09-23 20:31:11 -06:00
tangxifan 7a2502ddf9 [documentation] add more guidelines about the vpr-openfpga architecture annotation 2020-09-02 22:47:14 -06:00
tangxifan ac8e937a50 [Documentation] Update for default circuit model rules 2020-08-23 14:08:38 -06:00
tangxifan fb5a5a2448 [documentation] remove the limitation on through channels 2020-08-19 20:12:49 -06:00
tangxifan 47f15729ad update doc about the limitation on using tileable routing 2020-08-19 18:37:28 -06:00
tangxifan d6d17675e2 update docoumentation about the constraints when using tileable rr_graph generator 2020-08-19 18:01:32 -06:00
tangxifan 161d660837 update documentation for the initial offset when mapping physical pins 2020-08-19 15:00:46 -06:00