d7837b8eeb
[doc] add documentation about mock fpga wrapper
2023-05-25 15:01:10 -07:00
76a553e7bc
[doc] supplementary description
2023-04-21 15:23:51 +08:00
c220438c42
[doc] adding new syntax that supports separated clocks for multi-head configuration chains
2023-04-21 15:21:34 +08:00
081620055b
[doc] fix broken links in the Clock Network file format
2023-04-21 13:58:13 +08:00
509f5eb6dc
[doc] add documentation about clock network description file
2023-04-20 17:06:53 +08:00
9756bfe0ca
[doc] document newly added commands for programmable clock arch support
2023-04-20 15:27:28 +08:00
55be8f491e
fix mux syntax in circuit_model_examples
...
the documentation is inconsistent about using underscores or dashes when describing a mux. It used one-level, but multi_level. Only underscores are valid in openfpga
2023-02-10 10:22:37 -07:00
9b109edaa1
[doc] added a new command
2023-01-11 17:14:06 -08:00
d48d7d6343
[doc] format fix
2023-01-01 17:28:55 -08:00
882682c30a
[doc] update for using batch_mode
2023-01-01 17:23:36 -08:00
e46397c91c
[doc] update doucmentation about new command source
2023-01-01 12:06:49 -08:00
5dfb3e6cb0
[doc] added an example about how to call vpr
2022-12-30 18:43:01 -08:00
492b8a153a
[doc] add documentation about vpr commands
2022-12-30 18:16:00 -08:00
e660880419
[doc] fixed bugs on small figure sizes shown
2022-12-06 17:20:46 -08:00
70b0d2e505
[doc] update pin table file format for pin direction keywords
2022-10-17 15:32:00 -07:00
aef94171c2
[doc] update options for pcf2place command
2022-10-17 13:55:18 -07:00
58487c7766
[doc] add more notes about the commmand ``pb_pin_fixup``
2022-09-29 11:01:07 -07:00
48f776d49b
[doc] update documentation about the new option
2022-09-12 16:58:32 -07:00
0609210b39
[doc] update doc with the new xml syntax
2022-09-08 17:00:16 -07:00
50813d90a2
[doc] update documentation based on the actual implementation on rr_gsb writer
2022-08-29 20:45:31 -07:00
12a30196e0
[engine] updating gsb writer; Unfinished!!!
2022-08-29 16:58:48 -07:00
adbc69f081
[doc] add new options for GSB writer
2022-08-29 14:16:51 -07:00
77abb86dab
[doc] update documentation about the activity file options
2022-08-01 21:37:22 -07:00
84dbcd61dd
[doc] fixed a few typo and format errors
2022-07-28 19:09:53 -07:00
c16bcd7f63
[doc] add file formates required by pcf2place
2022-07-28 16:35:13 -07:00
860591ff3f
[doc] add pcf file format to documentation
2022-07-28 16:15:44 -07:00
6e5fde56ce
[doc] add pcf2place to command list
2022-07-28 16:06:57 -07:00
2b4beb632c
[doc] fix a bug in including io information file format
2022-07-26 15:50:35 -07:00
bf2b1da801
[doc] add the new command file format to documentation
2022-07-26 14:06:07 -07:00
907308ee0f
[Doc] Update bitstream distribution file format
2022-03-29 20:09:24 +08:00
781250f0bb
Fix a small typo to trigger the CI flow.
2022-03-22 16:36:45 -07:00
6ff69d26b9
[Doc] An example to the documentation about the new feature in tile_annotation
2022-03-20 13:12:13 +08:00
123bb70cb3
[Doc] More explanantion on the use of config_enable attribute for circuit ports
2022-02-23 15:53:58 -08:00
b78e58d9bf
[Doc] Update doc about big endian syntax in bus group file format
2022-02-18 23:07:18 -08:00
8116141210
[Doc] Update documentation on the bus group feature
2022-02-18 15:46:25 -08:00
37d8617a5c
[Doc] Update due to new options
2022-02-17 19:45:37 -08:00
4a78bcf5d3
[Doc] update file format about bus group
2022-02-17 15:15:05 -08:00
796428d848
[Doc] Add documentation about bus group file format
2022-02-17 14:22:21 -08:00
2b5fded2a9
[Doc] Update documentation on the new option
2022-02-01 13:25:58 -08:00
b7b0a2a5d8
[Doc] Update doc about the new option
2022-02-01 12:19:26 -08:00
63f44adf15
[FPGA-Verilog] Now have a new option ``--use_relative_path``
2022-01-31 12:48:05 -08:00
a9a56686e2
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
2022-01-26 11:10:29 -08:00
25143d07f1
[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
2022-01-25 13:37:54 -08:00
a4659020f2
Merge branch 'master' into time_stamp
2022-01-25 12:11:35 -08:00
62b57b05d2
[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
2022-01-25 12:09:08 -08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
bd158311c5
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
2022-01-18 14:07:41 +05:00
588ee14920
Merge branch 'master' into issue-483
2022-01-18 13:38:12 +05:00
fb2e4377c8
Added missing changes from previous commit.
2022-01-17 19:42:40 +05:00
2b008177e7
Updated documentation.
2022-01-17 14:58:20 +05:00
tangxifan
scott-temple
taoli4rs
Aram Kostanyan