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[doc] update documentation about the activity file options

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tangxifan 2022-08-01 21:37:22 -07:00
parent 0f7c600528
commit 77abb86dab
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docs/source/manual/openfpga_flow/run_fpga_task.rst
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@ -206,6 +206,8 @@ Synthesis Parameter Sections
In case of running ``blif_vpr_flow`` this option provides the activity files
to be used to generate testbench for ``bench_label`` benchmark
.. note:: This file is required only when the ``power_analysis`` option in the general section is enabled. Otherwise, it is optional
.. option:: bench<bench_label>_verilog=<source_verilog_file_path>
In case of running ``blif_vpr_flow`` with verification this option provides

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yosys-plugins

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Subproject commit 3b3dcc5cc216f7a39d26a6d894c53b8aa3e10d71
Subproject commit 52cdcc42db527087fb342b4dabdb1a79878266cb