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[doc] update documentation about the new option

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tangxifan 2022-09-12 16:58:32 -07:00
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docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
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@ -24,6 +24,14 @@ Repack's functionality are in the following aspects:
See details in :ref:`file_formats_repack_design_constraints`.
.. warning:: Design constraints are designed to help repacker to identify which clock net to be mapped to which pin, so that multi-clock benchmarks can be correctly implemented, in the case that VPR may not have sufficient vision on clock net mapping. **Try not to use design constraints to remap any other types of nets!!!**
.. option:: --ignore_global_nets_on_pins
Specify the mapping results of global nets should be ignored on which pins of a ``pb_type``. For example, ``--ignore_global_nets_on_pins clb.I[0:11]``. Once specified, the mapping results on the pins for all the global nets, such as clock, reset *etc.*, are ignored. Routing traces will be appeneded to other pins where the same global nets are mapped to.
.. note:: This option is designed for global nets which are applied to both data path and global networks. For example, a reset signal is mapped to both a LUT input and the reset pin of a FF. Suggest not to use the option in other purposes!
.. warning:: Users must specify the size/width of the pin. Currently, OpenFPGA cannot infer the pin size from the architecture!!!
.. option:: --verbose