[Doc] Add pin constraints to documentation

docs/source/manual/file_formats/pin_constraints_file.rst

@@ -0,0 +1,25 @@
+.. _file_format_pin_constraints_file:
+
+Pin Constraints File
+--------------------
+
+The *Pin Constraints File* (PCF) aims to create pin binding between an implementation and an FPGA fabric
+
+An example of design constraints is shown as follows.
+
+.. code-block:: xml
+
+  <pin_constraints>
+    <set_io pin="clk[0]" net="clk0"/>
+    <set_io pin="clk[1]" net="clk1"/>
+    <set_io pin="clk[2]" net="OPEN"/>
+    <set_io pin="clk[3]" net="OPEN"/>
+  </pin_constraints>
+
+.. option:: pin="<string>"
+
+  The pin name of the FPGA fabric to be constrained, which should be a valid pin defined in OpenFPGA architecture description. Explicit index is required, e.g., ``clk[1:1]``. Otherwise, default index ``0`` will be considered, e.g., ``clk`` will be translated as ``clk[0:0]``.
+
+.. option:: net="<string>"
+
+  The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.

docs/source/manual/index.rst

@@ -16,3 +16,5 @@
 
    fpga_bitstream/index
 
+   file_formats/index
+

docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst

@@ -33,6 +33,8 @@ write_verilog_testbench
 
   - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
 
+  - ``--pin_constraints_file`` specify the *Pin Constraints File* (PCF) if you want to custom stimulus in  testbenches. Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
+
   - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
 
     .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.