tangxifan
|
977283dd34
|
[core] typo
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2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
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[test] add a new test to validate reset generated by internal driver through programmable clock network
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2024-07-10 14:11:06 -07:00 |
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tangxifan
|
b6ff69faac
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[test] reworking the testcase to validate clock network with internal drivers
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2024-07-10 11:36:22 -07:00 |
|
tangxifan
|
63f2a07c86
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[test] typo
|
2024-07-09 22:54:33 -07:00 |
|
tangxifan
|
89e6a0483f
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[test] add a new benchmark to validate rst and clk on LUTs
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2024-07-09 18:45:33 -07:00 |
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tangxifan
|
38bb5aa906
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[test] add a new benchmark to validate clock on LUT
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2024-07-09 18:42:39 -07:00 |
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tangxifan
|
4d9aacdf8f
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[test] add and deploy new benchmark
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2024-06-02 14:27:02 -07:00 |
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tangxifan
|
ad2d101554
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[test] deploy new benchmarks
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2024-06-02 14:23:08 -07:00 |
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tangxifan
|
d60d0540da
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[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
|
tangxifan
|
bc51be4863
|
[benchmark] syntax
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2023-01-18 18:34:24 -08:00 |
|
tangxifan
|
b6ae829518
|
[benchmark] add a new benchmark to validate dff
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2023-01-18 17:59:52 -08:00 |
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tangxifan
|
2c9593c1d4
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[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
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2023-01-15 13:09:40 -08:00 |
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tangxifan
|
6400605603
|
[benchmark] add clock divider
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2023-01-13 16:39:06 -08:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
9bc9b61d35
|
[test] fixed a few bugs
|
2022-09-29 15:11:30 -07:00 |
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tangxifan
|
df1ae7ba2a
|
[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker
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2022-09-29 14:23:17 -07:00 |
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tangxifan
|
a3d070ac6f
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[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
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2022-09-12 10:43:21 -07:00 |
|
tangxifan
|
314f5395b4
|
[benchmark] fixed a bug which causes yosys failed
|
2022-09-09 17:04:59 -07:00 |
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tangxifan
|
7a38c7dd18
|
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
|
2022-09-09 16:42:55 -07:00 |
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tangxifan
|
9c7868cfab
|
[hdl] add a counter design which is triggered by negative edges
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2022-05-09 16:41:21 +08:00 |
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tangxifan
|
430580f138
|
[HDL] Fix a typo
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2022-02-15 16:09:14 -08:00 |
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tangxifan
|
a7786efde1
|
[HDL] Now dual-clock counter has only 1 reset pin
|
2022-02-15 16:07:50 -08:00 |
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tangxifan
|
7121513396
|
[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
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2022-02-15 15:21:08 -08:00 |
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tangxifan
|
48355d1fc3
|
[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers
|
2022-01-02 20:16:59 -08:00 |
Aram Kostanyan
|
b332a5a1b4
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
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tangxifan
|
5a6874e9f1
|
[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
|
2021-07-02 17:28:17 -06:00 |
|
tangxifan
|
0b6a9b06f5
|
[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
|
2021-07-02 10:39:07 -06:00 |
ANDREW HARRIS POND
|
1d281765ea
|
fixed tab spacing
|
2021-07-01 16:42:04 -06:00 |
|
ANDREW HARRIS POND
|
808821bb8c
|
fixed errors
|
2021-07-01 16:40:03 -06:00 |
|
ANDREW HARRIS POND
|
8513b8a4ff
|
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
|
2021-07-01 15:29:39 -06:00 |
|
ANDREW HARRIS POND
|
2567fbee05
|
ready to merge
|
2021-07-01 15:28:59 -06:00 |
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tangxifan
|
04ceeefb0a
|
Merge branch 'master' into verilog_testbench
|
2021-07-01 14:43:26 -06:00 |
|
ANDREW HARRIS POND
|
db9231c225
|
tests failing with initial blocks
|
2021-07-01 13:52:28 -06:00 |
Andrew Pond
|
fab2b069f0
|
added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
|
tangxifan
|
a898537474
|
[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
|
2021-06-30 15:29:13 -06:00 |
|
tangxifan
|
4d4577bb83
|
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
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2021-06-30 15:13:47 -06:00 |
|
tangxifan
|
477cba1c7e
|
Merge branch 'master' into verilog_testbench
|
2021-06-23 09:18:18 -06:00 |
|
tangxifan
|
0a0d10b36d
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[HDL] Bug fix in Verilog syntax
|
2021-06-22 16:18:46 -06:00 |
|
tangxifan
|
07dcf3ad27
|
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
|
2021-06-21 16:48:35 -06:00 |
|
Andrew Pond
|
3cfc42cdf9
|
added testbench CI
|
2021-06-15 14:16:31 -06:00 |
|
Andrew Pond
|
12b44e0eca
|
added configuration benchmark files
|
2021-05-13 10:04:23 -06:00 |
|
tangxifan
|
16fff90607
|
[Benchmark] Add microbenchmark 1-bit blinking
|
2021-05-06 15:17:27 -06:00 |
|
tangxifan
|
a571b063b6
|
[Benchmark] Add 1k DPRAM benchmark which can fit new arch
|
2021-04-28 11:26:31 -06:00 |
|
tangxifan
|
7d059f7407
|
[Benchmark] Bug fix in dual port ram 16k benchmark
|
2021-04-27 23:33:20 -06:00 |
|
tangxifan
|
3c1c33bf1e
|
[Benchmark] Add a microbenchmark just fit 16k dual port ram
|
2021-04-27 22:51:43 -06:00 |
|
tangxifan
|
7e2368158e
|
[Benchmark] move benchmarks to microbenchmark category
|
2021-04-27 22:12:30 -06:00 |
|
tangxifan
|
5a85ec9fa0
|
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
|
2021-04-27 22:09:10 -06:00 |
|
tangxifan
|
1d498bb296
|
[Benchmark] Add a scalable micro benchmark fifo
|
2021-04-27 15:26:52 -06:00 |
|
tangxifan
|
200b6d39a6
|
[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
|
2021-04-23 20:36:28 -06:00 |
|
tangxifan
|
671394ec2c
|
[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
|
2021-04-23 20:33:43 -06:00 |