Commit Graph

682 Commits

Author SHA1 Message Date
Tim Newsome 4f9e2d7171
Fix semihosting for multicore targets (#478)
* WIP making semihosting work with -rtos hwthread.

Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e

* More WIP.

Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb

* Fix halting due to a trigger.

Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad

* Fix multicore semihosting without halt groups.

Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4

* WIP

Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40

* Fix single core semihosting.

This was the last bug!

Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28

* Fix whitespace.

Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
2020-05-19 10:34:36 -07:00
Tim Newsome 1524487a13
Speed up SBA block reads roughly 2x. (#477)
* Speed up SBA block reads roughly 2x.

Change-Id: I4e4f5530d4abae7470fd00308361e727904367d2

* Fix whitespace.

Change-Id: I28a1269c489d051560a2455973f9a8574f35f487
2020-05-18 14:43:41 -07:00
Antonio Borneo 4f459660a9 coding style: avoid unnecessary line continuations
Line continuation, adding a backslash as last char of the line, is
requested in multi-line macro definition, but is not necessary in
the rest of C code.

Remove it where present.

Identified by checkpatch script from Linux kernel v5.1 using the
command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types LINE_CONTINUATIONS -f {} \;

Change-Id: Id0c69e93456731717a7b290b16580e9f8ae741bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5619
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:29 +01:00
Antonio Borneo 9b29cb58ac coding style: remove useless break after a goto or return
In a switch/case statement, a break placed after a goto or return
is never executed.
The script checkpatch available in Linux kernel v5.1 issues a
warning for such unused break statements.
In the process of reviewing the new checkpatch for its inclusion
in OpenOCD, let's get rid of these warnings.

The script checkpatch is unable to fixup automatically this case.
Thanks to having "break" command using a single code line, this
patch has been generated using the script below:

	find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \
	 --types UNNECESSARY_BREAK -f {} \; \
	| sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \
	| awk 'function P() {print "sed -i '\''"b"'\'' "a};
	       {
	         if ($1!=a) {
	           if (a) {P()};
	           a=$1;
	           b=$2"{d}";
	         } else {
	           b=b";"$2"{d}"
	         }
	       };
	       END {P()}'

Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5617
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:05 +01:00
Tim Newsome 55dd7e83ca
Add awareness of halt group cause. (#472)
Change-Id: I7f7b967ccaa3d1ff05a7e7d0c2a7ba4fa7d68ac0
2020-05-06 08:42:38 -07:00
Florian Fainelli 5c6e32612d Remove BUILD_TARGET64
BUILD_TARGET64 creates a larger test matrix and mostly gates the
building of the aarch64/armv8 target, make that unconditional, which
would help fixing any issues with 64-bit address types anyway.

Rebased by Antonio Borneo after commit 1fbe8450a9 ("mips: Add
MIPS64 support")

Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5240
Tested-by: jenkins
2020-04-21 12:55:41 +01:00
Tim Newsome 3967f48843
Fix some clang static checker complaints. (#464)
The OpenOCD project looks at this, so once in a while I go through and
make sure our code is OK.

Change-Id: I50032c847f30e93604d83d6366cfad85918d6e66
2020-03-27 11:20:48 -07:00
Tim Newsome 5b2426a4b2
Deal with vlenb being unreadable. (#458)
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.

Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
2020-03-26 09:08:56 -07:00
Tomas Vanek a2e822834d helper/binarybuffer: fix clang static analyzer warnings
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)

Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-03-07 15:30:05 +00:00
Antonio Borneo e7306d361b coding style: fix space around pointer's asterisk
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.

This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command
	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types POINTER_LOCATION --fix-inplace -f {} \;
then manually reviewed.

OpenOCD coding style does not mention the space around pointer's
asterisk, so no check is enforced. This patch only makes the style
uniform across the files.

The patch only changes amount and position of whitespace, thus
the following commands show empty diff
	git diff -w
	git log -w -p
	git log -w --stat

Change-Id: Iefb4998e69bebdfe0d1ae65cadfc8d2c4f166d13
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5197
Tested-by: jenkins
2020-02-24 10:30:36 +00:00
Tim Newsome 1449af5bdb
Give control over dcsr.ebreak[msu] bits. (#451)
This allows a user to debug code that uses software breakpoints itself.

Change-Id: If40cb626354e11703017cdf8c5919a31e83ebc3f
2020-02-20 13:58:15 -08:00
Tim Newsome 95462a8a35
Add support for vector register access (#448)
* WIP

Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd

* Reading v* registers appears to work.

Can't really test it though, because gdb doesn't print them right.

Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5

* Total hack to communicate registers to gdb.

Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765

* Implement writing vector registers.

Fixed reading vector registers.

Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214

* Show gdb the actual size of the vector registers.

This length may be different per hart.

Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493

* Remove outdated todo comment.

Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128

* Removed TODO comment.

Filed #449 to track this.

Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47

* Nicely handle some errors reading/writing V regs.

Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
2020-02-14 14:54:05 -08:00
Tim Newsome 2f456abd55
Complain about debug version before authentication. (#441)
Change-Id: I769af8323545c2c18e4253a1543e9202f0bdfabc
2020-01-27 16:07:08 -08:00
Tim Newsome 69e6891434
Handle DMI busy in sba write. (#437)
* Handle DMI busy in sba write.

If we encounter DMI busy on the NOP after a read, we'll never get the
value out because DMI busy is sticky. The read must be retried, but we
don't know whether it was ever issued. Since the read has side effects
(incrementing of the address) this retry must be handled at a higher
layer. So now dmi_op_timeout can be told to retry or not, and if retry
is disabled it'll return an error when busy.

Also actually properly do the retry in dmi_op_timeout(). Previously the
code would not reissue the command and end up returning a garbage value.

Change-Id: I3b52ebd51ebbbedd6e425676ac861b57fbe711b1

* Fix whitespace.

Change-Id: Icb76d964e681b22346368d224d1930c9342343f3

* Handle a few more DMI busy cases.

Change-Id: I8503a44e4bf935c0ebfff0d598fe4c322fda702a

* Explain when to use dmi_op_timeout(retry).

Change-Id: I1a5c6d76ac41a84472a8f79faecb2f48105191ff

* dmi_reset does not affect the current transaction.

That means the retry scheme we had been using works fine. This does
contain some minor tweaks, and now we pass my tests which hammer the DMI
busy case harder.

Change-Id: I13eee384dbba82bc5a5b1d387c75c547afe557b5

* Remove unnecessary changes to make the PR readable

Change-Id: I87079876e6965563cf590e3936b3595aeab8715d

* Move idle to end of line...

... because we go through run-test/idle after the scan.

Change-Id: I21a8cff22471f0b895d8cd8d25373dced9bf1ca9

* Remove unused code.

Change-Id: I07a7cdd2d64ca40a4fe181111a34cf55ff1928d1
2020-01-13 15:10:43 -08:00
Jan Matyas fcea4f79ba Don't issue extra FENCE+FENCE.i for the current hart. (#439)
The original OpenOCD code issued FENCE & FENCE.i twice for the current
hart (which is harmless, but takes time).

Avoiding this extra FENCE is a slight performance improvement. Per my rough
measurements, this improves performance of certain debugger actions
(single-stepping) by approx. 20% in single-hart systems.
2020-01-10 12:29:10 -08:00
Jan Matyas e03dd199e0 Fixed write_memory_progbuf() on RV64. (#426)
Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
2019-11-27 15:24:25 -08:00
Tim Newsome de00906ebd
Fix memory access on some targets. (#428)
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.

This fixes https://github.com/riscv/riscv-tests/issues/217.

Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
2019-11-22 11:37:46 -08:00
Jan Matyas 739d16d503 Fix: Take into account progbuf writability. (#424)
When allocating scratch memory within RISC-V target
(scratch_reserve()), take into account whether progbuf
is writable or not, as determined by examine_progbuf().
2019-11-20 12:00:00 -08:00
Greg Savin b7bd3f8d47 BSCAN batch fix (#422)
* fix for batch scans not honoring presence of BSCAN tunnel

* fix formatting to placate checkpatch

* replace DIM with ARRAY_SIZE

* Refactor code that adds a bscan tunneled scan.

* Move bscan tunnel context to the batch structure, and in array
form, one per scan

* adjust code that was inconsistent with project code formatting standards
2019-11-12 09:00:35 -08:00
Tim Newsome f93ede5401
Add support for 64-bit memory reads/writes (#419)
* 64-bit progbuf memory reads work.

Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399

* 64-bit writes work.

Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23

* Let targets indicate number of supported data bits.

This is used by the default memory read/write functions when creating an
aligned block.

I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.

Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b

* Make mingw32 happy.

Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
2019-11-04 11:04:30 -08:00
Tim Newsome 3b4fcf471f The compliance test is poorly supported.
In reaction to #412.

Change-Id: I183bd8b4995c04e44cbc4f1c475eae391030fae6
2019-10-03 16:36:24 -07:00
darius-bluespec 20fc862b15 Perform SBA writes with batch transactions for improved performance. (#405)
* Add riscv_batch_available_scans().

This function will query the number of available scans in a batch.

* Perform SBA writes with batch transactions for improved performance.

Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
2019-09-24 17:49:25 -07:00
Tim Newsome 274be9587f
Fix flashing HiFive Unleashed (#402)
* Align algorithm stack to XLEN.

This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.

Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d

* Compile 32-bit RISC-V algorithms for RV32E.

Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa

* Remove debug code.

Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b

* Dump start of gdb packets escaping non-printable.

Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915

* Propagate flash programming errors.

Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7

* Improve debug messaging.

Change-Id: I47ac3518f3b241986c677824864102936100adf6

* Add debug output to flash image.

This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.

Change-Id: Id44c6498c288872cc2cec79044116ac38198c572

* Make timeout depend on how much data is written.

Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e

* Fix issi erase commands.

This is required to flash HiFive Unleashed.

Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10

* Fix running algorithm on multicore `-rtos riscv`.

The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.

Change-Id: I140431898285cf471b372139cef2378ab4879377

* Make fespi flash algorithm debugging optional.

Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.

Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-09 12:01:17 -07:00
Tim Newsome 5173ddf75e
Use only one hart to run algorithm. (#396)
* Clear cmderr by writing all ones.

This should have been part of #389.

Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0

* Don't update reg cache in register_write_direct().

This function explicitly bypasses any caches.

Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9

* Use only one hart to run algorithm.

Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.

Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
2019-08-26 11:24:29 -07:00
dave-estes-syzexion cd7eea6d76 Adds support for RISCV Access Memory Abstract Commands (#394)
* Adds support for RISCV Access Memory Abstract Commands

The Access Memory Abstract Command is one of the three optional
methods for reading and writing memory on a complient RISCV
debug module. The previous two options were already implemented
in OpenOCD.

Implementation Notes:
- aamvirtual is hard-coded to false until the design for accessing
  virtual addresses is finalized.
- aamsizes corresponding to 8b, 16b, 32b, and 64b are supported.
  128b support is postponed until it is required, as it will mean
  changes to the read/write_abstract_arg() interface to pass 128b
  values.
- aampostincrement is not used and hard-coded to false.

* Changes from review.

* Additional lint fixes and a typo from last commit.

* Fixing a clang error.

* Fixes a last-minute change that broke writes with width > 8b.

* Removing memcpy after adding read_from_buf().
2019-08-19 14:03:20 -07:00
Tim Newsome 7eaf60f1b5
Properly detect errors in SBA reads. (#392)
Also don't set/clear sbreadondata when only reading one word.

Change-Id: Ia81834014895f1f4b552312ad0b60b3d3967a2c7
2019-07-26 11:08:35 -07:00
Nils Wistoff 239a515a9c Access memory through the scope of current privilege level (#386)
* add opcode for csrrsi and csrrci

* enable MMU while reading/writing memory using progbuf

* fix style issues

* keep old behavior for progbufsize<4, perform r/w/csr only when necessary

* do not pass progbufsize, only write mstatus if changed

* add config option to enable virtualization feature

* throw error if virt enabled but unavaliable, outsource modify_privilege

* support virtualization for read_memory_progbuf_one
2019-07-18 13:15:28 -07:00
Tim Newsome 09016bcb6e
Optimize reading a single byte/short/word. (#390)
gdb has developed a nasty habit of very often reading 30-some
half-words. This change speeds that up significantly.

Change-Id: Iab1b7575bec5c57051c6e630ae292dddf8fe6350
2019-07-15 10:34:40 -07:00
Tim Newsome 9b34f8ca3c
Write all ones to clear cmderr. (#389)
Change-Id: Ia76e749ed9f5a5f3509f253eeb69d1208bcfc929
2019-07-15 10:33:52 -07:00
Tim Newsome 91faf1a573
Reduce abstract command execution by one scan. (#383)
Speeds up Arty flashing another 7%.

```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 96.997032s (22.434 KiB/s)
verified 2192012 bytes in 6.642059s (322.285 KiB/s)
11.86user 12.75system 1:44.13elapsed 23%CPU (0avgtext+0avgdata 18684maxresident)k
```

Change-Id: If609ce3de1726332f420d131e9fa6e04a5d974a1
2019-06-21 09:59:28 -07:00
Tim Newsome bb03f79bde
Improve block read and checksum speed (#381)
* Cache program buffer writes.

Speeds up flash program by 3%, flash verify by 2%.

Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a

* Remove nop from batch reads.

program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).

Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935

* Use "algorithm" to compute CRC on RISC-V targets.

Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.

riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.

Small target.[ch] change to be able to run algorithms at 64-bit
addresses.

Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```

Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190

* Clean up formatting.

Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 10:56:37 -07:00
Tim Newsome c05ad1a92a
Set mstatus.FS to access FPU CSRs. (#380)
This improves behavior when executing function calls from mainline gdb.

Change-Id: Ia37507a16cd76fc03d26457e84fd68402969c534
2019-06-14 15:55:56 -07:00
Paul George fd9c54b1fe Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode

Given the variable supported message length , a prefix  decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len =  max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected.

* style patch

* non-conflict with original

* style patch

* style patch

* requested changes

* style-patch
2019-06-10 13:33:50 -07:00
Tim Newsome 998fed1fe7
Don't write sbcs while sbbusy is set. (#375)
* Fix small SBA bug.

We were not compliant with the spec, but I'm not sure if this was
causing problems for anybody.

Change-Id: Ia31ee400fd75ad907349c4dd995b1e03bd2116c7

* Don't write sbcs while sbbusy is set.

Probably not hurting anything, but the spec says we shouldn't.
Also propagate more errors, and fully decode sbcs in debug output.

Change-Id: I1a36646772fe794c8780702565103a309bbcc5e9
2019-05-21 14:40:47 -07:00
Philipp Wagner 44f595b2b8 RISC-V: Make compliance tests more verbose (#366)
Currently the RISC-V compliance test suite doesn't output the test is
currently runs before it succeeds. It also uses the same message for
many tests. This makes it very hard to find out which test fails.

This commit makes things slightly easier by printing the test that's
being executed before it actually runs, and by adding the source code
line where the test is located, making it easier to look up the test in
the source code.

New output looks like this:

Info : Executing test 149 (riscv-013.c:3800): Regular calls must return ERROR_OK
Info :   PASSED
2019-05-20 13:36:41 -07:00
Philipp Wagner 45b5178b1a RISC-V compliance test: target must be examined (#367)
The test assumes that the target has been examined. If that fails (for
whatever reason) the test will segfault:

Program received signal SIGSEGV, Segmentation fault.
register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
109             struct reg *reg = cache->reg_list;
(gdb) bt
0  register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
1  0x0000000000520735 in riscv_invalidate_register_cache (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2160
2  0x000000000052224f in riscv_halt_all_harts (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2022
3  0x0000000000574e82 in riscv013_test_compliance (target=0x779b50) at ../src/target/riscv/riscv-013.c:3600
2019-05-20 13:35:58 -07:00
Tim Newsome 5cb2f200f8
Simultaneous halt (#372)
* WIP

Change-Id: I4f50dced77e9ded4a58ab152824a841a73bc0dc1

* riscv_halt() only halt harts that are running.

Progress towards simultaneous halt.

Change-Id: I749b6d9ba5e77aa7aca4342c7af841312b78be0e

* -rtos riscv passes.

But dual gdb is failing again.

Change-Id: I1747ba42ce3f3062f6e8c28a75ac40e17f80e980

* Dual gdb works again.

-rtos riscv still works.

Change-Id: Idddddda79e5918b26e181384def1a305ecceced2

* -rtos hwthread almost completely works.

Change-Id: I845feb0bd93484e28ca8620f4760c234d4ce5310

* Maybe better?

Change-Id: I669c67e83acf1b749bfb534d3b3c0915c129d686

* All three methods work.

Change-Id: If77074fa43f6420d1ec9b594fe366415f5a41f2c

* Fix hitting hardware triggers with `-rtos riscv`.

Change-Id: I8d4600e1c66fa0e3b9d986b96a5973d09f40735c

* Fix halting dual core E31.

Change-Id: Ic2d885e027312b68e2f3c6854957fbfee09f814b

* Not addressing this TODO right now.

Change-Id: Ic7c0d32424068ae1de04d37d15a411c1957207c4

* Remove duplicate line.

Change-Id: I14fe8d422f23c97afdaa20a02c0e3ab568219467
2019-05-09 11:32:04 -07:00
Greg Savin 5190dd4cef
Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#370)
Including adjustments in response to review comments.
2019-04-23 16:25:22 -07:00
Tim Newsome d78ff5ab4e Propagate some errors in execute_abstract_command().
Change-Id: Ia3ec457dd5d65378a6c922802713e36d6828bcea
2019-04-09 10:55:25 -07:00
Tim Newsome c089e6ae9a
Support simultaneous resume using hasel (#364)
* Remove unnecessary 0.11 code.

Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().

Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.

Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc

* WIP little refactor working towards hasel support.

Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf

* More refactoring.

Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b

* More refactoring.

Change-Id: Icea1308499492da51354f89e1529353e8385f3a1

* Starting to work towards actual hasel changes.

Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e

* Implement simultaneous resume using hasel.

Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f

* Add support back for targets that don't have hasel.

Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a

* Make hasel work with >32 harts.

Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
2019-04-03 12:13:09 -07:00
Tim Newsome bc72695f67 Lots of RISC-V improvements.
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`

Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27 08:53:09 +00:00
Tim Newsome 9fac2de633
Set up halt groups for SMP groups. (#353)
If the hardware supports it, when one hart in an SMP group halts all the
other harts in that same SMP group will automatically, quickly, halt as
well.

Change-Id: Ida81f1309c180674e8c9d8060e3d2a4bbb910a6f
2019-03-05 13:05:53 -08:00
Tim Newsome 80ef54dba2
Rtos riscv (#350)
* Implement riscv_get_thread_reg().

This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).

CustomRegisterTest went from 1329s to 106s.

Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32

* Also implement riscv_set_reg().

Now all the `-rtos riscv` tests pass again, at regular speed.

Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1

* Better error messages.

Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5

* Add target_get_gdb_reg_list_noread().

Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.

Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7

* Revert a change I made that has no effect.

I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.

Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
2019-02-07 13:24:44 -08:00
Tim Newsome 49dd7ded87 Merge branch 'riscv' into hwthread 2019-01-25 14:17:32 -08:00
Tim Newsome afedcb337a WIP on hardware breakpoints.
This is messy, but contains at least some bugfixes.

39/43 tests pass now.

Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-24 15:27:53 -08:00
Tim Newsome 906635c4bd Move version check until after dmactive=1.
This should allow OpenOCD to work with targets where version is not
readable when dmactive=0, which is allowed by the spec.
2019-01-22 12:48:47 -08:00
Tim Newsome 02ece46105 Clean up register caching a little.
Change-Id: Id039aedac44d9c206ac4bd30eb3ef754e190c3fe
2019-01-10 12:32:03 -08:00
Darius Rad 00b591a09a Add 'riscv set_ir' command to set IR value for JTAG registers.
This allows using different TAP addresses, for example, if using
BSCANE2 primitives on a Xilinx FPGA.
2019-01-09 17:20:39 -05:00
Tim Newsome e6b6aa615b Add comment for reset_delays_wait.
Also refactor so there's just one of them in riscv, instead of one for
0.11 and one for 0.13.

Change-Id: I0dbbf112b4c57f76bed971a22dadf844fa27cd4e
2019-01-08 14:01:25 -08:00
Tim Newsome 6faa9ded26 Clean up debug printf.
I only need to see 64 bits of PC if the high bits are non-zero.

Change-Id: I29397791da1e3f1705e573b2eaafc3eac202e178
2019-01-07 12:16:51 -08:00
Tim Newsome ccc093ab82 Fix typo.
Change-Id: Ibdd26c5c524b10a3518fe708e9b7fc917b0cb1b6
2019-01-02 12:42:31 -08:00
Tim Newsome d6a6699f15 Fix block read corner cases.
Change-Id: I841f264ca881078075beaa58023dd0e0a81f3ff3
2018-12-13 12:05:55 -08:00
Tim Newsome 41e5272adc Add `riscv reset_delays` for testing.
This allows me to test corner cases in block read/write errors.

Change-Id: I3ccfe707851dbc578277ea0d5e278eab81a3c7ef
2018-12-04 12:38:51 -08:00
Tim Newsome d650ef6089 Deal with DMI busy in block reads/writes.
Rename dtmcontrol_idle to dtmcs_idle, because the register is now called
dtmcs.
Simplify read_memory_progbuf_inner(), getting rid of several unnecessary
variables.

Change-Id: Ibac655a45c63cf2210ab282568b54f8097526c10
2018-12-03 16:04:58 -08:00
Tim Newsome 42be17aed6
Add idle count to debug output. (#337)
Few other minor cleanups/debug improvements.

Change-Id: I370a86ddc17a2d888afa178448125661e12caf72
2018-11-29 12:52:06 -08:00
Tim Newsome f042dcb0a3
examine() should leave halted harts halted (#327)
Previously all harts would be resumed at the end of examine().
Fixes #326.

Change-Id: Id82b361e98f151911f8679538ee4b3c754efd6a5
2018-11-12 13:01:55 -08:00
Tim Newsome d18c2f23d3
Doxygen style, too. (#325)
* Doxygen style, too.

Change-Id: I85e60e8577c4177ac7094ae41ee84357b292a89c

* More Doxygen.

Change-Id: Ic7477dce5459146f299e080cac1a3f133af7abdb
2018-11-07 13:53:52 -08:00
Tim Newsome 005cfca219
Install patchutils for the build. (#321)
* Install patchutils for the build.

This contains filterdiff, which we need to check that our changes
conform to OpenOCD style.

Change-Id: Id522f4e62fee3efad4e0e00933abfeada9635624

* Fix paths for filterdiff line.

Change-Id: Ic50e13c7fe64e65b2d2af0260fb19c07a9f10e20

* Conform to OpenOCD style.

Change-Id: I51660d30404c0a625b58c9bed2d948695575e72e
2018-11-05 11:50:09 -08:00
Carsten Gosvig dc4fe85880 Old fixes from June (#311)
* Changed logging level

* Added logging statement

* Removed halt event when attaching to target

* Extended some packet handling

* Extended handling of rtos_hart_id and clearing of register cache

* Extended execute_fence to handle all harts

* Removing logging statement again

* Updated according to review comments

* Forgot to re-add the return statement

* Was removing too much for the if statement to work

* This needs to >= 3 now to handle both a fence and a fence.i
2018-10-30 11:29:00 -07:00
Carsten Gosvig 983a07be64
Merge pull request #308 from riscv/eclipse_memory_read
Fixing Eclipse block memory read
2018-10-19 23:07:22 +02:00
cgsfv 9703c00b25 Moved comment and added initial buffer clearing 2018-10-19 17:47:58 +02:00
Tim Newsome 60c37e1679
dmi_scan() allocate bytes depending on abits value (#307)
* dmi_scan() allocate bytes depending on abits value

Fixes #303.

Change-Id: Iac45959cf342180c60cd0b5462f864ad81beddd2

* Incorporate review feedback.

Change-Id: I1cc7d20fed6f2d891bec0e858fca53ece450720c
2018-10-18 13:26:03 -07:00
cgsfv 0a31d919e3 Corrected wrong C syntax 2018-09-17 13:53:35 -07:00
cgsfv 10a2823191 Read memory words individually if burst read fails 2018-09-17 13:53:35 -07:00
Ryan Macdonald 631f6cd55b More style fixes
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:30:17 -07:00
Ryan Macdonald 3516fd5019 Style fixes
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:29:09 -07:00
Ryan Macdonald 583c90e87c Add pass message for SBA and compliance tests
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:26:32 -07:00
Megan Wachs 4b29af433d Merge remote-tracking branch 'origin/riscv' into sba_tests 2018-08-31 09:02:55 -07:00
Megan Wachs 24513fe51f riscv-compliance: fix comment typo 2018-08-30 15:37:15 -07:00
Megan Wachs 7448f8780a riscv-compliance: fix whitespace 2018-08-30 11:30:14 -07:00
Megan Wachs 934440b80e riscv-compliance: incorporate review feedback 2018-08-30 11:26:05 -07:00
Tim Newsome 164415cfbe
Merge branch 'riscv' into sba_tests 2018-08-29 15:55:30 -07:00
Megan Wachs 34ee883aef Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase 2018-08-29 15:47:54 -07:00
Tim Newsome b4b2ec7d2d
Add command to expose custom registers (#293)
* Added `riscv expose_custom` command.

Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.

Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f

* Conform to OpenOCD style.

Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf

* Free all the memory allocated by register init.

Change-Id: I04e35ab54613f99708cee85e41fef989079adefc

* Properly document `riscv expose_custom`.

Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
2018-08-29 14:22:50 -07:00
Tim Newsome 684d7d6764
Remove unused variable. (#284)
Change-Id: Iedebce86b5d914ff612a4747ffdc6f776edca783
2018-08-20 12:42:30 -07:00
Tim Newsome a51ab8ddf6 Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-07-24 13:07:26 +01:00
Tim Newsome ead2a595b8 Use work area instead of riscv-specific config
Per review requested at http://openocd.zylin.com/#/c/4578/3

Change-Id: I1a8117665d38844dc1479f33b4f9b7c8f9f101c8
2018-07-16 14:43:15 -07:00
Tim Newsome 2a6332f620 Update debug defines to match spec
The main difference is we need to deal with hartsello/hartselhi. (Note
that there's a compile-time limit to 16 harts, but that can be changed.)
My largest target has 4 harts, so I can't tell how well this really
works. But it doesn't break anything.

Fixes #240.

Change-Id: Ie1a2a789b5e00f55174994568749da1cf3a33b92
2018-06-06 13:43:35 -07:00
Tim Newsome ab7ab8a867
Merge pull request #261 from riscv/trigger_enum
Delay trigger enumeration until it's required.
2018-05-25 11:52:10 -07:00
Megan Wachs bdc4355493 Merge remote-tracking branch 'origin/trigger_enum' into riscv-compliance 2018-05-22 16:27:52 -07:00
Megan Wachs a0e811580a Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-22 16:27:29 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required.
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22 13:07:25 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Megan Wachs 9a5a5c2dc9 Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compliance 2018-05-16 22:29:45 -07:00
Megan Wachs 802c3b4003
riscv: remove unexpected check during reset
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
2018-05-16 22:25:38 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
2018-05-03 16:02:59 -07:00
Tim Newsome 292180fb44
Merge pull request #246 from darius-bluespec/sysbus-bugfix
Bug fixes for system bus access
2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Ryan Macdonald 0ed96e80d3 Fix more style issues
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-04-24 14:15:30 -07:00
Ryan Macdonald 9089854b84 Code cleanup from feedback. 2018-04-24 14:01:21 -07:00
Tim Newsome 9a69c1c096 Fix mingw32 build.
Change-Id: If7a57749ba8c49385a4020ce8d2d8dbb94242122
2018-04-20 16:28:24 -07:00
Tim Newsome 4593659edf Fix error messages for reset dmi timeouts.
Change-Id: I00869ba20db6f27415af8e53e7b3e67741bf894d
2018-04-20 15:10:56 -07:00
Megan Wachs eeac4f7fd4 riscv-compliance: remove whitespace 2018-04-19 10:52:19 -07:00
Megan Wachs debf2b040a riscv-compliance: correct the HALTSUM0/HALTSUM1 checks 2018-04-19 10:36:52 -07:00
Megan Wachs ac953c71c0 riscv-compliance: add dummy comments to appease the linter 2018-04-18 16:15:07 -07:00
Megan Wachs 06fc61f464 riscv-compliance: whitespace 2018-04-18 16:10:41 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 005630d24d Use reset timeout to read dmstatus out of reset
Change-Id: I74cc6a1e006269270c5197994d21523d01206141
2018-04-18 14:31:00 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Megan Wachs 8fa81c1f97 riscv-compliance... code that compiles > code that makes linter happy 2018-04-17 16:11:03 -07:00
Megan Wachs 8ce4f787ca riscv-compliance: whitespace cleanup 2018-04-17 16:05:15 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs 401dcf7a06 riscv-compliance: make sure reset assertion and deassertion actually worked. 2018-04-17 15:47:15 -07:00
Megan Wachs f516825079 riscv-compliance: make sure not to clear DMACTIVE 2018-04-17 14:30:37 -07:00
Megan Wachs aef4888249 riscv-compliance: Fix writing hartsello 2018-04-17 11:55:50 -07:00
Ryan Macdonald e025cb320c Fix style issues. Code cleanup. 2018-04-17 10:47:44 -07:00
Megan Wachs 30e1dbdc6b riscv-compliance: fix compile errors and whitespace 2018-04-17 10:43:36 -07:00
Ryan Macdonald 4f4d5f46f1 Fix build issues 2018-04-17 10:35:32 -07:00
Megan Wachs ef684c2e68 riscv-compliance: Incorporate feedback to make tests make fewer assumptions about hte implementation and properly use OpenOCD functions 2018-04-17 10:28:13 -07:00
Megan Wachs 716c12bcaf riscv: don't supporess errors 2018-04-17 07:57:32 -07:00
Megan Wachs 4c6c4cb078 riscv: Add a TODO note we need to handle hartselhi 2018-04-17 07:53:34 -07:00
Megan Wachs fa99b8e3b1 riscv-compliance: Fix OpenOCD lint checks 2018-04-17 07:49:06 -07:00
Ryan Macdonald 0b027a2854 Code cleanup. Bump debug_defines.h version 2018-04-16 17:20:31 -07:00
Ryan Macdonald 065671b311 Code style cleanup 2018-04-13 11:20:12 -07:00
Megan Wachs ff365173a0 riscv-compliance: fix too-narrow constant 2018-04-12 17:31:23 -07:00
Megan Wachs 2deff1b2c9 riscv: hartsel-> hartsello (not supporting hartselhi yet) 2018-04-12 16:10:45 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Megan Wachs 7eca2dfe5d Squashed commit of the following:
commit fb7009fc38
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55eb
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4a
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
2018-04-12 15:02:04 -07:00
Ryan Macdonald 1ba3986eb7 More test/SBA RTL debug 2018-04-12 12:26:54 -07:00
Ryan Macdonald a9b8820916 Checkpoint: debugging tests 2018-04-11 18:10:48 -07:00
Ryan Macdonald 50cd4203a5 Fix more style issues with previous commit 2018-04-11 14:41:00 -07:00
Ryan Macdonald 4191505b76 Fix style issues with previous commit 2018-04-11 14:38:51 -07:00
Ryan Macdonald cc98a14839 Added address alignment test, code fixups from review 2018-04-11 14:26:16 -07:00
Tim Newsome 1fda89c3ce Only write hartsel if we're changing it.
DebugBreakpoint went from 2.94s to 2.74s.

Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
2018-04-09 15:13:24 -07:00
Ryan Macdonald 836bd7cb69 Fix sign compare compiler error 2018-04-09 11:55:46 -07:00
Ryan Macdonald c2c52c89b1 Fix some build issues 2018-04-09 11:38:41 -07:00
Ryan Macdonald 99f2f5a272 Change #ifdef SIM_ON to be a run-time arg 2018-04-09 11:26:31 -07:00
Ryan Macdonald de329f4004 Fixed style issues in previous commit. 2018-04-09 10:54:21 -07:00
Ryan Macdonald a9b2277574 Add #ifdef to only enable sbbusyerror test in simulation. 2018-04-09 10:51:53 -07:00
Tim Newsome 238b1e9f06 Cache registers while halted.
This saves us from re-reading s0 before doing just about anything
program buffer related.

Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.

Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
2018-04-06 15:52:40 -07:00
Ryan Macdonald 7c6f6d79bc Fixed more style issues 2018-04-05 17:59:43 -07:00
Tim Newsome 5c0a9a9ee4 Just read abstractcs once when executing a command
DebugBreakpoint went from 3.41s to 3.05s!

Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
2018-04-05 17:59:07 -07:00
Ryan Macdonald d471fff3db Fixed build issues 2018-04-05 17:57:53 -07:00
Ryan Macdonald ada78cae11 Checkpoint: fix even more code style issues 2018-04-05 16:49:00 -07:00
Ryan Macdonald 8c8bed878c Checkpoint: fix some more code style issues 2018-04-05 16:42:28 -07:00
Ryan Macdonald 761aaeba98 Checkpoint: fix some code style issues 2018-04-05 16:39:33 -07:00
Ryan Macdonald 3bdb8b29a8 Checkpoint: finish debug of tests, working on hitting sbbusyerror case 2018-04-05 16:31:09 -07:00
Ryan Macdonald c5a8e1cf4c Initial commit of tests for SBA feature 2018-04-04 13:50:17 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome 755c6a4caa Add wall clock timeout to dmi_op()
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.

Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
2018-03-30 15:24:16 -07:00
Tim Newsome 4ee7d5373d Fix auth error message.
Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
2018-03-30 13:21:00 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset.
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
Tim Newsome c534a37fc3 Make reset work again for multicore
Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
2018-03-23 12:53:24 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
Tim Newsome e5591c2584 Halt the target again if it was reset while halted
Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
2018-03-20 12:34:17 -07:00
Tim Newsome 52eabbd2a5 Add `riscv set_prefer_sba`
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
Tim Newsome d5b450c508 Fix build, broken by b7c5c5d228.
Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
2018-03-19 12:56:05 -07:00
Tim Newsome 40e0c5b976 Format error messages.
Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
2018-03-19 12:46:10 -07:00
Tim Newsome b7c5c5d228
Merge pull request #225 from riscv/old_bus2
Support v0 System Bus Access
2018-03-19 12:11:28 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset.
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
Tim Newsome fd2759a63d Clear havereset in examine() and deassert_reset().
Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
2018-03-16 15:03:31 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00
Tim Newsome 3ddbbd525d
Merge pull request #222 from riscv/dmi_commands
Add riscv dmi_read/dmi_write commands.
2018-03-15 11:32:33 -07:00
Tim Newsome 68a6812a41 Use TARGET_PRIxADDR instead of PRIx64.
Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
2018-03-09 18:02:18 -08:00
Tim Newsome 075610d495 Support v0 system bus access
This code was submitted at
https://github.com/riscv/riscv-openocd/pull/214. This change
incorporates that code, makes it build, and fixes the style to fit the
OpenOCD style guide.

I have not tested the new code because I don't have a target. It does
not cause any regressions.

Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46d
2018-03-09 18:02:18 -08:00
Tim Newsome fd9de02fac
Merge pull request #221 from riscv/reg_running
Error instead of asserting on reg access failure
2018-03-07 12:22:33 -08:00
Tim Newsome ddb894edf6 Add riscv dmi_read/dmi_write commands.
Mostly addresses #207.

Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.

Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
Tim Newsome 509e0e4715 Error instead of asserting on reg access failure
Instead of asserting, return error when an abstract register access
fails on running target.

Fixes #201

Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
2018-03-02 20:24:58 -08:00
Tim Newsome 84c0fdd5d1 Don't always error if a debug program fails
This is often expected, and the calling code should decide whether to
emit an error or not.

Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
2018-03-02 20:02:32 -08:00
Tim Newsome 1d00d03dc0 Remove unable to read register error message
It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.

Fixes #176

Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
2018-03-02 19:41:31 -08:00
Tim Newsome 0c8235d11f
Merge pull request #216 from kaspar030/fix_some_fallthroughs
target/riscv: add some switch fallthrough comments
2018-02-28 12:31:22 -08:00
Tim Newsome d388f1cbb2
Merge pull request #218 from riscv/auth
Add `riscv authdata_read` and `riscv authdata_write` commands to support arbitrary authentication through TCL scripts
2018-02-28 09:20:31 -08:00
Tim Newsome 39716b15ab Fix authentication for multi-core targets.
When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.

Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
2018-02-27 14:22:06 -08:00
Tim Newsome 10108b623d Add `authdata_read` and `authdata_write` commands.
They can be used to authenticate to a Debug Module.

There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.

Example usage (very simple challenge-response protocol):
```
init

set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]

reset halt
```

Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
Tim Newsome 9033d99491
Merge pull request #217 from riscv/disable_target64
build with --disable-target64
2018-02-26 12:06:47 -08:00
Tim Newsome 3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
Kaspar Schleiser d570f89303 target/riscv: add some switch fallthrough comments 2018-02-20 14:31:31 +01:00
Tim Newsome 6b02ab4196 Fix build with --disable-target64
Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
2018-02-19 15:07:10 -08:00
Tim Newsome 352e6b82ed
Merge pull request #208 from riscv/run_from_trigger
Handle resuming from a trigger...
2018-02-19 13:42:50 -08:00
Megan Wachs 1b37f60969 riscv-compliance: Check that DPC is sign extended properly. 2018-02-13 15:02:31 -08:00
Megan Wachs 8f7195af76 riscv-compliance: Turn off ABSTRACTAUTO until the appropriate time 2018-02-13 13:47:14 -08:00
Megan Wachs 313885cb3b riscv-compliance: whitespace fixes 2018-02-13 13:08:15 -08:00
Megan Wachs 2e525e391f riscv-compliance: get it compiling against riscv branch again 2018-02-13 13:01:56 -08:00
Megan Wachs 88370b3989 riscv-compliance: fix some macros which were renamed 2018-02-13 11:44:53 -08:00
Megan Wachs f3bce93dc8 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-13 10:57:32 -08:00
Gleb Gagarin 5c543ee3a1 complete reset before writing to hartsel field 2018-02-07 16:06:02 -08:00
Tim Newsome ace6b7e49a Handle resuming from a trigger...
... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.

Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
2018-02-07 13:30:23 -08:00
Megan Wachs 5cf705d360 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-06 10:26:22 -08:00
Tim Newsome a80ab87efd Add unreachable return for mingw build.
Change-Id: I8c0c4d7be8f6f28638cc2b5ae8114f5c8f95f94b
2018-01-31 16:55:43 -08:00
Tim Newsome 7114ef485c Fix cut and paste bug.
Change-Id: I1c554cbe3d7cb7845bc62f14ae6b8dff107eb192
2018-01-31 16:45:33 -08:00
Tim Newsome bb2c25c5ce Make OpenOCD work when there is no program buffer.
Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.

Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
2018-01-31 15:33:45 -08:00
Tim Newsome 6f0d70f5c8 Mention register name instead of number in error
Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
2018-01-30 12:30:39 -08:00
Tim Newsome ee93a9b2f1 Add error handling code to system bus read/write
It's not tested because spike never reports any busy errors since every
access happens instantaneously.

Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
2018-01-30 08:53:46 -08:00
Tim Newsome 0f0c5b1ff5 Merge branch 'riscv' into sysbusbits
Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
2018-01-29 11:39:14 -08:00
Tim Newsome 6a98fb7076 Detect hartsellen, limiting which harts we probe
Tested with doctored spike with hartsellens of 0, 1, 3, and 10.

Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
2018-01-26 16:39:58 -08:00
Tim Newsome 5184c32125 Clear errors that we see.
Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...

Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
2018-01-26 15:43:05 -08:00
Tim Newsome b67379700b Add support for v1 system bus access.
This is functional, but doesn't handle errors.

Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
2018-01-26 15:43:05 -08:00
Tim Newsome 2d263bae84 Make all memory logging lines consistent.
Also reduce a few 64-bit variables to 32 bits, which is all they need.

Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
2018-01-24 13:53:11 -08:00
Tim Newsome 42e601afc1
Merge pull request #191 from riscv/scanbuild
Fix some niggles found by clang's static analysis.
2018-01-24 07:59:47 -08:00
Tim Newsome 553a63808c Fix some niggles found by clang's static analysis.
Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
2018-01-23 15:16:23 -08:00
Tim Newsome 3839cbf0ad Add some error checking to examine().
Fixes #183.

Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
2018-01-19 13:58:02 -08:00
Tim Newsome 7f368468c8 Remove dead code.
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-15 12:07:20 -08:00
Tim Newsome 0d60a29c21
Merge pull request #178 from riscv/cleanup
Rename dummy variable to be correct.
2018-01-10 15:16:40 -08:00
Tim Newsome 29c7a76708 Muck with mstatus to always be able to read FPRs
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-09 12:06:11 -08:00
Tim Newsome fd506fa839 Propagate register read errors.
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
Tim Newsome 37434ffd77 Rename dummy variable to be correct.
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-05 13:05:33 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info.
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04 13:36:53 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls.
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27 13:45:50 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort().
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26 15:04:02 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide.
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26 11:38:11 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure.
Change-Id: Ia54f778152974164697b712c360918e17a127d95
2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions.
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct.
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine()
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11.
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names.
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
Tim Newsome 7c989698a1 WIP better CSR names, and include only existing
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D.
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
Tim Newsome e648856a41 `make all` debug tests now pass.
Also properly support (I think) D extension on RV32.

Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
Tim Newsome c421fefdcb Checkpoint that seems to work.
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-19 10:41:48 -08:00
Tim Newsome 6aff46adcc Fix cut and paste bug.
Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.

Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14 13:51:13 -08:00
Tim Newsome 0a65a6527d Fix build.
Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11 12:58:20 -08:00
Tim Newsome 52cdf286ca Add missing return.
Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-16 15:58:08 -08:00
Megan Wachs 9f56a9643d riscv-compliance: remove some compile warnings 2017-11-02 09:34:43 -07:00
Megan Wachs e435011713 Merge commit '8304e1b' into HEAD 2017-11-01 13:44:51 -07:00
Tim Newsome e28abf7c9e Merge branch 'riscv' into small_progbuf
Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01 13:38:17 -07:00
Tim Newsome db754536e8 Support 64-bit FPRs on RV32.
Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.

I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.

Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.

This change improves Issue #110 but there's more work to be done.

Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
Megan Wachs 1672f9a60d Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-10-25 15:41:41 -07:00
Tim Newsome 1acb128290 Remove unused variables.
Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-25 13:37:56 -07:00
Tim Newsome 23bd6d08c9 Remove more unused functionality.
Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24 15:11:33 -07:00
Tim Newsome dbecbfee99 Add a fence after memory writes.
Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24 12:15:25 -07:00
Tim Newsome 59a0340261 Remove more unused code.
Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24 11:38:39 -07:00
Tim Newsome 8432b7cf3d Remove more unused code.
Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-24 11:34:48 -07:00
Tim Newsome 5425c871c9 Properly fix memory read when encountering busy.
Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-23 14:13:46 -07:00
Tim Newsome a3a137062d Pay attention to impebreak.
This required updating debug_defines.h, which caused a few other small
cleanups as well.

Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
2017-10-18 14:21:23 -07:00
Tim Newsome 5d3f5c35d2 Still restore registers if an access failed.
Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
2017-10-18 12:32:41 -07:00
Tim Newsome 7edd9b1786 Fix FPR access.
Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
2017-10-18 11:47:15 -07:00
Tim Newsome a0623b2fa8 Don't crash when encountering RV64.
Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
2017-10-17 11:58:51 -07:00
Tim Newsome 65be0776d8 Memory read/write works if the core can keep up.
Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
2017-10-17 11:52:07 -07:00
Tim Newsome fbe2980eb7 MemTest64 passes.
Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
2017-10-17 11:15:51 -07:00
Tim Newsome d94b38279a Memtest{16,32} pass.
Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-16 21:08:59 -07:00
Tim Newsome 7ec7bc32fe At least some memory writes work.
Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
2017-10-13 12:50:02 -07:00
Tim Newsome e7bb815e87 Register read/write might be working.
Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
2017-10-12 14:38:52 -07:00
Tim Newsome 94e8250713 WIP; doesn't work.
Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-12 11:45:52 -07:00
Tim Newsome 77802af655 Remove duplicate progbuf size variable.
Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
2017-10-10 16:27:51 -07:00
Tim Newsome abe7eba25a Merge pull request #118 from riscv/priv
Fix priv access
2017-10-04 12:52:21 -07:00
Tim Newsome e64bb8c44a Fix priv access on 0.13. 2017-09-30 14:15:37 -07:00
Tim Newsome 744894e965 Better debug messages. 2017-09-26 15:40:41 -07:00
Tim Newsome f0195868d3 Fall back on ndmreset if hartreset is unsupported. 2017-09-21 14:53:12 -07:00
Tim Newsome fe36097ff8 Fix reset for multicore. 2017-09-21 12:42:40 -07:00
Tim Newsome 848fe0ffcf Cleaning up single-hart reset. 2017-09-19 17:41:52 -07:00
Tim Newsome 4e701669b7 Merge pull request #113 from riscv/macos_build
Add clang build
2017-09-19 14:11:10 -07:00
Tim Newsome 0abd94b50c Make constants unsigned for clang. 2017-09-18 14:23:59 -07:00
Tim Newsome 604dfa0dcc Try to fix some clang warnings. 2017-09-18 14:03:33 -07:00
Tim Newsome 157a67a98a Be more clear in multi-core systems without -rtos
Don't print out there's a hart with XLEN of 0.
2017-09-18 11:29:14 -07:00
Tim Newsome ce20be3d78 Add support for F extension. 2017-09-14 16:23:47 -07:00
Tim Newsome f9b2549e20 Tell user how to increase timeout. 2017-09-11 12:11:24 -07:00
Tim Newsome a6ec1a0e68 Add timeout to another infinite loop. 2017-09-11 11:35:47 -07:00
Tim Newsome 6721988ce3 Ensure read_memory() only reads each address once.
Previously it might read an address multiple times if an abstract
command took longer to execute than expected.

The new implementations reads from the target how far it has gotten
along reading memory, and resumes from there if cmderr=busy.

This ended up being a bigger change than I envisioned, but in the end it
deleted more lines than it added, so I'm happy. :-)
2017-08-29 17:25:04 -07:00
Tim Newsome 2efc415db4 Finally nailed memory read on slow targets
The downloaded program now post-increments, and there's no longer an
attempt to read the current address from the target. This made it easier
to fix the problem where at the start of the loop the current address
was already read (in regular entry) or has not yet been read (when the
first round through the loop encountered busy more than once, or busy
was encountered at least once later on).
2017-08-28 11:17:55 -07:00
Tim Newsome 5f53655e65 Fix off-by-one error. 2017-08-26 18:25:10 -07:00
Tim Newsome eef9442aa7 Remove redundant code. 2017-08-26 17:50:05 -07:00
Tim Newsome 5bdee8bc66 Fix off-by-3 error on 64-bit targets.
This caused everything to fall apart when debugging slow 64-bit targets.
2017-08-26 17:49:13 -07:00
Tim Newsome 92ef328161 Don't reset DMI when an abstract command is busy. 2017-08-25 18:14:08 -07:00
Tim Newsome a9bcc48064 Remove unnecessary newlines. 2017-08-25 18:14:08 -07:00
Palmer Dabbelt 322669ca98 Merge pull request #95 from riscv/memread
Fix block memory reads on slow targets.
2017-08-25 16:57:07 -07:00
Tim Newsome 4d0e88d887 Merge pull request #100 from riscv/riscv_timeout_commands
riscv: Add commands for setting timeouts
2017-08-25 09:49:15 -07:00
Megan Wachs 6e16ef2bd4 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-08-15 17:22:48 -07:00
Megan Wachs 6200d9a180 Merge branch 'riscv_timeout_commands' into riscv-compliance 2017-08-15 17:22:08 -07:00
Megan Wachs 879c274cb9 riscv: Add commands for setting timeouts 2017-08-15 15:59:40 -07:00
Megan Wachs 3ec1772c96 riscv: Add commands for setting timeouts 2017-08-15 15:55:09 -07:00
Tim Newsome 0ff4103a26 Reset address if target was busy during bust write
Improve Issue #98.

DebugCompareSections is still failing for me (with an instrumented
sometimes-slow spike), but MemTestBlock now passes reliably.
2017-08-15 15:47:35 -07:00
Tim Newsome 5c39079a62 Remove some unnecessary casts. 2017-08-15 14:29:24 -07:00
Tim Newsome 0d74c8689d Fix block memory reads on slow targets.
The interesting new code concerns ignore_prev_addr and
this_is_last_read.

Additionally, I tweaked some debug output, and optimized
riscv_batch_run() when the batch is empty.
2017-08-14 15:02:19 -07:00
Megan Wachs 25eedb94a5 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-08-14 12:08:58 -07:00
Tim Newsome 2706df0ec3 Fix a corner case in block memory read. 2017-08-13 14:14:23 -07:00
Gleb Gagarin 3109da7dfd Force actual read from prog buffer for the last transaction in read_memory() 2017-08-12 14:51:12 -07:00
Gleb Gagarin e676d3dae6 Fixed off-by-one error in previous commit 2017-08-11 17:46:35 -07:00
Gleb Gagarin 39b01259fa fixed memory leak introduced by previous commit 2017-08-10 16:37:50 -07:00
Gleb Gagarin b5692585de Fix reads beyond requested memory range 2017-08-10 14:27:11 -07:00
Tim Newsome efcfcf555f Fix assertion failure when reading from address 0. 2017-08-09 12:42:17 -07:00
Tim Newsome b032eb1bcc Use a wall clock timeout to complete reset. 2017-07-16 11:48:12 -07:00
Tim Newsome f0f1df1061 Fix infinite loop in reset. 2017-07-14 12:50:11 -07:00
Megan Wachs c8015e8dc1 riscv compliance: More post-test cleanup 2017-07-13 08:00:22 -07:00
Tim Newsome d60dbd60e8 Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
Megan Wachs 20d46b8bf0 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-12 18:46:26 -07:00
Megan Wachs 66fa38add7 riscv-compliance: Halt harts again at the end of the test. 2017-07-12 18:44:41 -07:00
Tim Newsome 2deb02695e Forgot to commit this follow up to PR #79 2017-07-12 17:51:38 -07:00
Tim Newsome 09bf86e31a Keep around cmderr for callers to inspect.
Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
Tim Newsome 856f70fe44 Try abstract register writes as well. 2017-07-12 14:13:31 -07:00
Tim Newsome f37e93bbc0 Try using abstract commands to read registers
This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.

Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).

riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
Tim Newsome 4072fa493b Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
Tim Newsome 31e5b53a46 Merge pull request #74 from riscv/build32
Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
mwachs5 6842fd2c10 riscv: Add more TODO compliance comments 2017-07-05 17:59:30 -07:00
mwachs5 bdc38561c0 riscv: Clean up reset/dmactive/step compliance test 2017-07-05 17:54:55 -07:00
mwachs5 2b94888100 riscv: Add single-step, reset, and dmactive to the compliance test. 2017-07-05 15:11:40 -07:00
mwachs5 87abbe4a51 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-05 11:02:30 -07:00
Palmer Dabbelt 3cff4213a4 Merge pull request #69 from riscv/multi-gdb
Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
Tim Newsome 450307b66f Fix 32-bit build errors.
I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71.
2017-07-03 12:17:07 -07:00
Tim Newsome f18fd83ac7 Fix trigger set/clear bug. 2017-07-03 11:52:35 -07:00
Dmitry Ryzhov 99a3673507 Fix comment about saving the temporary register in examine procedure. 2017-07-01 15:09:23 +03:00
Dmitry Ryzhov 7d451e00f5 Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction. 2017-06-30 19:15:58 +03:00
Megan Wachs 7bc23c7776 riscv: Add some comments on what else compliance test needs 2017-06-28 19:36:22 -07:00
Megan Wachs 434fb3708a riscv: Correct DPC masking in compliance test. 2017-06-28 19:36:22 -07:00
Megan Wachs e32a8c911d riscv: Fix AUTOEXEC test for 32-bit cores 2017-06-28 19:36:22 -07:00
mwachs5 4101740928 riscv: add compliance tests for DPC and DCSR 2017-06-28 19:36:22 -07:00
mwachs5 e17ca3a31d riscv: More compliance tests for core registers. 2017-06-28 19:36:22 -07:00
mwachs5 222850df55 debug: add a 'wfi' to compliance test. 2017-06-28 19:36:22 -07:00
mwachs5 9e76ec1779 riscv: Compliance test for HALTREQ/RESUMEREQ R/W 2017-06-28 19:36:22 -07:00
mwachs5 ccc605158a riscv: Added several compliance test items 2017-06-28 19:32:38 -07:00
mwachs5 95ee7975ea riscv: Add skeleton of RISC-V v013 compliance 2017-06-28 19:32:38 -07:00
Palmer Dabbelt d77c4a953c Don't set breakpoints on disabled harts 2017-06-21 12:25:20 -07:00
Palmer Dabbelt 4bdb042224 Allow memory writes to proceed on all harts 2017-06-21 12:25:19 -07:00
Palmer Dabbelt a277416a39 Refactor examine, to avoid some assertions
Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart.  Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
Palmer Dabbelt 788908fcf0 Factor out checking if harts should be used
Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled".  This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
Palmer Dabbelt 9f4cac5a38 Set current_hartid from coreid
This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
Tim Newsome 9cd98058a0 Set hardware triggers on all harts.
Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
Tim Newsome ccdd26e3ef Comment curious code. 2017-06-20 11:32:42 -07:00
Tim Newsome 927f9d8873 Update list of "threads" when harts are discovered.
This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
Tim Newsome 4d264b3579 Put early DEBUG notice of XLEN back. 2017-06-19 08:46:02 -07:00
Tim Newsome 6082f35a55 Update debug_defines. Clarify debug output.
Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
Tim Newsome fd81f7fcac Fix comment. 2017-06-16 14:02:25 -07:00
Tim Newsome 851849a295 Tell the user about detected harts. 2017-06-16 14:02:25 -07:00
Tim Newsome ac2da40f74 Fix indentation to match OpenOCD style.
This change is just in the whitespace. There are no code changes.

See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
Tim Newsome 363a0a2bf2 Merge pull request #64 from riscv/release-fixes
Two fixes from the release branch
2017-06-15 12:43:46 -07:00
Tim Newsome 50a223ef9a Fix print statements to work with 64-bit addresses 2017-06-15 12:24:37 -07:00
Palmer Dabbelt 099a3020d2 Clear abstract errors from register_read_direct 2017-06-15 12:16:24 -07:00
Tim Newsome 64af052911 Fix the build.
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
Tim Newsome 6be600318c Fix dmi_read() indentation; remove \n in LOG_ERROR 2017-06-08 12:31:08 -07:00
Megan Wachs c3b344d1c0 riscv: Move the initialization of the field inside the structure for consistency 2017-06-07 21:06:33 -07:00
Megan Wachs 459b39ec67 riscv: v13 -- dmi_write must still check for the OP result 2017-06-07 21:06:33 -07:00
Palmer Dabbelt c431c0eb25 Check for abstractcs.busy, not just CMDERR_BUSY
This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
Palmer Dabbelt a8cf04b839 Go back to 32-word read/write buffers
The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
Palmer Dabbelt e31761df64 Don't re-read registers after they're written
This was just a sanity check.
2017-05-15 16:57:08 -07:00
Palmer Dabbelt 9d308db2bc Print out the actual CSR that's read 2017-05-15 16:56:50 -07:00
Palmer Dabbelt 8252b9d36c Build fixes 2017-05-15 13:39:58 -07:00
Megan Wachs af6e04d5c0 riscv: Remove some compile warnings 2017-05-15 13:36:05 -07:00
Palmer Dabbelt 563f6acc3c Allow all harts to be reset 2017-05-09 13:33:20 -07:00
Megan Wachs 95a2eb157a riscv-013: more consistent parens 2017-05-01 09:42:11 -07:00
Megan Wachs 458bb20699 riscv-013: Correct sign extension of address on read_memory for lower bits as well 2017-05-01 09:39:59 -07:00
Megan Wachs 8462750357 riscv-013: Correct sign extension of address on read_memory 2017-05-01 09:37:48 -07:00
Megan Wachs ad1cf13ef4 Correct debugging print in read_memory 2017-05-01 08:35:10 -07:00
Palmer Dabbelt 16de5044d4 Fix an assertion when reading from 0 2017-05-01 08:33:01 -07:00
Palmer Dabbelt 1ec607c726 Clean up unused read_memory code 2017-04-27 12:56:01 -07:00
Palmer Dabbelt 8dea2908b7 Add 64-bit and multihart support
This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest draft version of the RISC-V debug spec, as of
   April 26th.  This version fixes a number of spec bugs and should be
   close to the final debug spec.
2017-04-26 09:10:49 -07:00
Megan Wachs 3dc066382b Properly consider 'reset halt' and do halt or resume as needed 2017-04-10 12:03:15 -07:00
Megan Wachs b04c6cb3ed riscv: Implement the assert/deassert reset functions for v13 2017-04-10 12:03:15 -07:00
Megan Wachs 14e26040b8 riscv: move value read to after autoexec is cleared. 2017-04-04 16:33:17 -07:00
Megan Wachs 9c1f6ea28b riscv: Correct the autoexec in read_mem 2017-04-04 16:22:55 -07:00
Megan Wachs eb90a5e05e riscv: Use write-1-to-clear for CMDERR, not write 0 to clear. 2017-03-30 14:27:28 -07:00
Palmer Dabbelt 03fa9d22c4 Don't set abstractauto at the start 2017-03-23 14:50:40 -07:00
Megan Wachs c61b3efe9a riscv: Retry failed memory reads 2017-03-22 17:51:46 -07:00
Megan Wachs 98420e377a riscv: add missing variable declaration. 2017-03-21 23:47:21 -07:00
Palmer Dabbelt 09da0c812f Clear autoexec correctly 2017-03-21 17:20:11 -07:00
Palmer Dabbelt 6033850415 Wrong autoexec 2017-03-21 17:20:11 -07:00