Commit Graph

682 Commits

Author SHA1 Message Date
Rob Bradford eed9e5b229
Merge cfd4dc2b0a into fa7e2351c8 2025-02-26 14:46:38 +01:00
Farid Khaydari c14d9b6d1d target/riscv: make mem_access_result_t enum type safe
Make mem_access_result_t enum type safe and fix related problems

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Change-Id: Ie5a8c71f3a8ad803f1660114c399c5a4dd0f7414
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2025-02-21 13:45:49 +03:00
Farid Khaydari 7335759845 target/riscv: set appropriate memory access result codes
Set appropriate memory access result codes

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Change-Id: Ib73b5a041e5f15aef150b80fdd45f107de19d3a6
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2025-02-21 13:44:47 +03:00
Farid Khaydari dce6182d4b target/riscv: merged read/write functions to one access function
Commit merges read/write functions to access function.
It allows to decrease amount of code duplication.

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2025-02-17 19:09:33 +03:00
Evgeniy Naydanov fac1412ace
Merge pull request #1218 from fk-sc/fk-sc/ref-mem-acc-res
target/riscv: refactored memory access result codes
2025-02-17 15:13:45 +03:00
Evgeniy Naydanov dd72250c63
Merge pull request #1208 from en-sc/en-sc/pass-tap
target/riscv: pass `jtag_tap` instead of `target`
2025-02-17 15:09:22 +03:00
Evgeniy Naydanov 8309288831 target/riscv: pass `jtag_tap` instead of `target`
For some functions, passing `target` is excessive. The corresponding
`tap` provides all the necessary data.

Change-Id: Ie5836024a15222bda7c2b727f5dbaac38f459b3c
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-02-07 12:30:50 +03:00
Farid Khaydari 0bd8aaa46c target/riscv: refactored memory access result codes
Slightly refactored memory access result codes:
* Changed enum formatting
* Changed status handlers to decrease boilerplate

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2025-02-03 15:17:20 +03:00
Evgeniy Naydanov 5de7310881
Merge pull request #1190 from lz-bro/enable-hardware-translation
target/riscv: move the dcsr modification out of program buffer
2025-01-29 18:47:41 +03:00
Evgeniy Naydanov e870c5f2de
Merge pull request #1206 from JanMatCodasip/jm-codasip/remove-asm-h
Remove target/riscv/asm.h
2025-01-27 15:56:12 +03:00
Evgeniy Naydanov 57b58b7832
Merge pull request #1202 from JanMatCodasip/fix-datatypes-around-batch
Fix data types around batch.{c,h}
2025-01-27 15:55:21 +03:00
Evgeniy Naydanov 1d623819e9
Merge pull request #1193 from en-sc/en-sc/not-busy
target/riscv: clear `abstract_cmd_maybe_busy` after commands
2025-01-27 15:54:38 +03:00
liangzhen 05d377af75 target/riscv: move the dcsr modification out of program buffer
when riscv virt2phys_mode is hw, reduce the use of
unnecessary program buffers.
2025-01-25 00:45:19 +08:00
Evgeniy Naydanov 182092a364 Merge up to 26f2df80c3 from upstream
Conflicts:
* `src/target/target.c` due to commit
  4004db5d3a ("Make polling_interval
  unsigned.")

Change-Id: I0a691dbebe300f3a53fb31bd1097a9aff5551a52
2025-01-22 17:47:14 +03:00
Jan Matyas a450a7d496 Fix data types around batch.{c,h}
Check that the value of dtmcs.abits is in the expected range.

Make corrections of data types in batch.{c,h} and in related code.
Some of the issues were found by activating "-Wconversion" in GCC,
others by inspecting the code manually.

This is an initial step towards being able to use "-Wconversion" on
RISC-V target code, which will give us bit more confidence when
refactoring or merging new patches.

Changes made:

- Check `dtmcs.abits` during examination.

- DMI address is no larger than 32-bits per the debug spec.
  Changed address parameters of multiple functions from uint64_t
  to uint32_t.

- The value passed to jtag_add_runtest() is now `unsigned int`,
  not `int`. No need for `assert(idle <= INT_MAX)` anymore.

- `get_delay()` in batch.c can return an unsigned value.

- Added few assertions around `field->num_bits` in batch.c.

Change-Id: Ibfccd62d552063df6ab9b5a2d4ea4ed23617d3db
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-01-21 16:09:29 +01:00
Jan Matyas c1dfb0d50e Remove target/riscv/asm.h
The file asm.h is only used by riscv-011.c.

Remove the whole asm.h file and inline the two functions into
riscv-011.c which is the only place of use.

Change-Id: Ifa4b2b87ab9f3f50c78a75361003ce478bfd9d5f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-01-20 09:16:30 +01:00
Evgeniy Naydanov b9d9d1a6a2 target/riscv: new `ebreak` controls
* Deprecate `riscv set_ebreak*` commands.
* Introduce RISC-V-sepecific `configure` parameter `-ebreak` instead.
* Separate controls for VS and VU modes.

Change-Id: I0ff88318dcb52af6923eb9f20f9d0c056ad09cf0
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-01-15 19:49:05 +03:00
Antonio Borneo 26f2df80c3 helper: list: rename macro clashing with sys/queue.h
The macro named LIST_HEAD() clashed with a macro of same name in
the GNU libc file sys/queue.h.
This causes a warning in MacOS build due to some other system file
including sys/queue.h.

Rename LIST_HEAD() as OOCD_LIST_HEAD().

Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: Ic653edec77425a58251d64f56c9f5f6c645ba0cd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Andrew Shelley <ashelley@btinternet.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8683
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andy <andrewjohnshelley@gmail.com>
2025-01-12 11:09:31 +00:00
Evgeniy Naydanov 83dc8a6446 target/riscv: clear `abstract_cmd_maybe_busy` after commands
If a sufficient delay was used before reading `abstractcs` during the
batch execution, `dm->abstract_cmd_maybe_busy` was not cleared and the
following call to `wait_for_idle_if_needed()` (e.g. on `resume`), would
result in a call to `wait_for_idle()` performing a redundant read of
`abstractcs`.
While this is not a bug, it impedes the performance.

Change-Id: I9d234ef6d53af96c60892d71247c10e631dfcc3b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-12-25 17:31:51 +03:00
Evgeniy Naydanov cf9963ad81
Merge pull request #1181 from en-sc/en-sc/reg-invalidate
target/riscv: clean-up register invalidation
2024-12-11 16:40:20 +03:00
Evgeniy Naydanov de20c2ad5f target/riscv: clean-up register invalidation
* Registers were not invalidated if the hart became unavailable.
* Improved logging in the case register invalidation involves loss of
  information.

Change-Id: Icfb5e190dd6dcb1a97e4d314d802466cab7a01e4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-12-10 15:25:22 +03:00
Farid Khaydari d5c2604418 target/riscv: replaced repeating ternary operator with variable
Replaced repeating ternary operator with variable

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-12-10 13:40:08 +03:00
Farid Khaydari 4dcd80164a target/riscv: use buf_get_uXX instead of manual bit shift
Replaced manual bit shift with buf_get_u64/buf_get_u32

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-12-04 22:56:05 +03:00
Anatoly Parshintsev c430c24330
Merge pull request #1167 from fk-sc/fk-sc/rwargs
target/riscv: pass memory access info in struct, move write_memory pointer
2024-12-04 21:04:56 +03:00
Rob Bradford cfd4dc2b0a target/riscv: Add support for external triggers
Add support for associating a halt group with an external trigger via a
newly exposed configuration option "riscv set_external_trigger".

Change-Id: If10c67d2e14d8bc7cd6d59011b3215fda4ff4b02
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
2024-12-02 17:16:08 +00:00
Farid Khaydari eb4e717a3b target/riscv: pass memory access info in struct, move write_memory pointer
This changes will allow to unite read_memory/write_memory fucntions
to one access function

(1) Replaced read/write functions arguments with one structure
(2) Unified read_memory/write_memory function pointers
    to be stored in same structure

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-11-29 18:12:53 +03:00
Anatoly Parshintsev 0f0302b029
Merge pull request #1174 from fk-sc/fk-sc/checker-fix
target/riscv: fix memory access result type checker function return in case of assertion
2024-11-29 01:23:37 +03:00
Farid Khaydari c8ae081979 target/riscv: fix memory access result type checker function return in case of assertion
Fix memory access result type checker return in case of assertion

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-11-26 12:56:36 +03:00
Farid Khaydari 8b7013028c target/riscv: decrease modify_privilege function nesting level
Restructured modify_privilege function to decrease nesting level

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-11-21 00:04:15 +03:00
Evgeniy Naydanov f51900b4a2
Merge pull request #1165 from aap-sc/aap-sc/resume_debug_errors
target/riscv: detailed error messages for cases when resume operation fails
2024-11-18 13:17:25 +03:00
Evgeniy Naydanov 463d1b0866
Merge pull request #1157 from zqb-all/support-disable-auto-fence
target/riscv: support disable auto fence
2024-11-18 13:16:54 +03:00
Evgeniy Naydanov c53f9319c8
Merge pull request #1163 from en-sc/en-sc/from_upstream
Merge up to fd62626dff from  upstream
2024-11-18 13:16:18 +03:00
Parshintsev Anatoly faffae0493 target/riscv: detailed error messages for cases when resume operation fails
This change aims to provide more context in case if resume operation
fails. Before the change messages were quite confusing.
2024-11-14 12:23:47 +03:00
Evgeniy Naydanov cabb6000df Merge up to fd62626dff from upstream
Conflicts are related to `unsigned`->`unisgned int` cleanup:
* `src/jtag/drivers/ftdi.c` -- between
  6749c70a3a and
  a64dc23bf1.
* `src/rtos/hwthread.c` -- between
  ef3e61bebc and
  436e6f1770.
* `src/target/target.c` and `.h` -- between
  53ec10b61d and
  e72733d590.
* `src/target/riscv/*` -- due to
  957eb741a0 and
  fec3b22421.
  Resolved by:
    * Changing the return type of `riscv_batch_get_dmi_read_op()` to
      `uint32_t`.
    * Using RISC-V OpenOCD's version in other cases.

Change-Id: Ia6e2129c6fddb1dec26adcd936506af2539412ef
2024-11-12 17:25:33 +03:00
Evgeniy Naydanov 784687d781 target/riscv: avoid updating `target` if `ackhavereset` fails
`target`'s `state` and `debug_reason` should not be updated in
`deassert_reset` if sending reset acknowledgment fails.

Change-Id: I86136fe829e7a7c6b69f718f0cf32322e40341b0
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-11-08 16:36:25 +03:00
Mark Zhuang 340e38a9ed target/riscv: support disable auto fence
Support disable automatic fence, it's useful for
debug some cache related issue.
2024-11-06 17:15:57 +08:00
Mark Zhuang 134e56338d target: riscv: convert 'unsigned' to 'unsigned int'
Change-Id: I10b9abf9e42389eb91b210b8c2f01219ca9068cd
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8366
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-11-02 21:02:42 +00:00
Evgeniy Naydanov f9a1292716
Merge pull request #1154 from en-sc/en-sc/dcsr-ebreak-halt-on-reset
target/riscv: avoid unnecessary `dcsr.ebreak*` update on reset
2024-10-30 17:52:56 +03:00
Mark Zhuang b7708c84e6 [NFC] target/riscv: simplify code with MAX macros
slightly improves readability
2024-10-28 22:57:07 +08:00
Evgeniy Naydanov 3fe20e7aa4 target/riscv: avoid unnecessary `dcsr.ebreak*` update on reset
There is no need to change if `dcsr.ebreak*` fields after a reset if a
user requested a configuration that will result `dcsr.ebreak*` field
values equal to reset values.

Change-Id: I2844d30aef8f735c7b37394ee422e9b3f04a2e3b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-10-25 17:27:19 +03:00
Evgeniy Naydanov 7b4ad6f173
Merge pull request #1152 from fk-sc/translation-drivers
target/riscv: added translation drivers
2024-10-24 15:06:27 +03:00
Farid Khaydari 6a27d9fbc0 target/riscv: added translation drivers
Existing flags: 'enable_virtual' and 'enable_virt2phys' were
replaced with explicit translation drivers. Motivation:

(1) Having 'enable_virtual' and 'enable_virt2phys' flags set simultaneously
may cause double address translation which is unacceptable

(2) Flags were global for all targets which is wrong too

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-10-23 12:36:29 +03:00
Antonio Borneo fec3b22421 target: riscv: remove non-trivial 'unsigned' cast
Change the prototype of riscv_batch_get_dmi_read_op().
Now that 'target->smp' is unsigned, drop the cast.

Change-Id: I2a54268ed1e4bf0ea884b62cceb73f5c7451da78
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8484
Tested-by: jenkins
2024-10-20 09:23:09 +00:00
Antonio Borneo 957eb741a0 target: riscv: convert 'unsigned' to 'unsigned int'
Conversion done with
	checkpatch --fix-inplace -types UNSPECIFIED_INT

Ignore the cast as they could be better addressed.
Fix only minor additional checkpatch issue (spacing and line
length).

Change-Id: I11f10eddadc21e051c96eb3d4d4c0554a2cddd15
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8483
Tested-by: jenkins
2024-10-20 09:22:52 +00:00
Evgeniy Naydanov bc68bd71a3
Merge pull request #1146 from en-sc/en-sc/select-dmi-bypass
target/riscv: check other TAPs in `select_dmi()`
2024-10-18 12:37:31 +03:00
Evgeniy Naydanov f3ed0ab608 target/riscv: check other TAPs in `select_dmi()`
If some other TAP is not in BYPASS, an IR scan is needed to select
BYPASS on that TAP.

Change-Id: Iae425a415109b1a853db3718762661877eea56e8
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-10-16 13:42:48 +03:00
Antonio Borneo 89fb9211ec target: riscv: convert 'unsigned' to 'unsigned int'
Conversion done with
	checkpatch --fix-inplace -types UNSPECIFIED_INT

Change-Id: I62fad88dd33716c24154d44c5a23ae2c0f7c4a4c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-10-12 17:01:36 +02:00
Evgeniy Naydanov a4020f1a02
Merge pull request #1142 from en-sc/en-sc/from_upstream
Merge up to 1173473f66 from upstream
2024-10-08 14:17:57 +03:00
Evgeniy Naydanov ec00140a10 Merge up to 1173473f66 from upstream
1ae6b07b45 replaced `buf_cmp()` with
`buf_eq()`, so a96a0a4e39 needs to be
adjusted.

Change-Id: I97f6a3518db9421dab2ae4dd2312f443e928b114
2024-10-03 21:48:18 +03:00
Tommy Murphy 16fa57da41 Fix riscv013_invalidate_cached_progbuf() off by one error
See https://github.com/riscv-collab/riscv-openocd/issues/1139
riscv013_invalidate_cached_progbuf() was failing to zeroize the final
buffer array element. Use memset() instead of a manual loop to zeroize
it in order to address this and simplify the code.
2024-10-03 09:37:28 +01:00