interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

riscv: remove unexpected check during reset 

I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
This commit is contained in:
Megan Wachs 2018-05-16 22:25:38 -07:00 committed by GitHub
parent 06e6c2297f
commit 802c3b4003
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/target/riscv/riscv-013.c
View File

@ -1644,15 +1644,12 @@ static int deassert_reset(struct target *target)
char *operation;
uint32_t expected_field;
uint32_t unexpected_field;
if (target->reset_halt) {
operation = "halt";
expected_field = DMI_DMSTATUS_ALLHALTED;
unexpected_field = DMI_DMSTATUS_ANYRUNNING;
} else {
operation = "run";
expected_field = DMI_DMSTATUS_ALLRUNNING;
unexpected_field = DMI_DMSTATUS_ANYHALTED;
}
LOG_DEBUG("Waiting for hart %d to %s out of reset.", index, operation);
while (1) {
@ -1665,11 +1662,6 @@ static int deassert_reset(struct target *target)
index, riscv_reset_timeout_sec);
if (result != ERROR_OK)
return result;
if (get_field(dmstatus, unexpected_field)) {
LOG_ERROR("Unexpected hart %d status during reset. dmstatus=0x%x",
index, dmstatus);
return ERROR_FAIL;
}
if (get_field(dmstatus, expected_field))
break;
if (time(NULL) - start > riscv_reset_timeout_sec) {