Clifford Wolf
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73bf453929
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Improvements in pmgen for recursive patterns
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 18:35:56 +02:00 |
Eddie Hung
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aad97168b0
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Fixes for reverting SigSpec helper functions
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2019-08-14 10:22:33 -07:00 |
Eddie Hung
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2f04beeeb5
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Perform C -> PCIN optimisation after pattern matcher
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2019-08-13 17:11:35 -07:00 |
Eddie Hung
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1b0e68db94
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Revert changes to RTLIL::SigSpec methods
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2019-08-13 17:09:28 -07:00 |
Eddie Hung
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0597a3ea23
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Rename to XilinxDspPass
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2019-08-13 10:23:07 -07:00 |
Eddie Hung
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12c692f6ed
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc1310 , reversing
changes made to f54bf1631f .
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2019-08-12 12:06:45 -07:00 |
David Shah
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f9020ce2b3
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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
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2019-08-10 17:14:48 +01:00 |
Eddie Hung
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ab1d63a565
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Check nusers of DSP output, not whole flop
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2019-08-09 17:35:13 -07:00 |
Eddie Hung
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3dd3ab98c2
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Improve ice40_dsp for non-fully-32-bit adders
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2019-08-09 17:23:12 -07:00 |
Eddie Hung
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dfc878deb4
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Another filter -> if
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2019-08-09 16:23:32 -07:00 |
Eddie Hung
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e83f231927
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Cleanup
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2019-08-09 15:47:40 -07:00 |
Eddie Hung
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0b5b56c1ec
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Pack partial-product adder DSP48E1 packing
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2019-08-09 15:19:33 -07:00 |
Eddie Hung
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a002eba14a
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Fix check
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2019-08-09 14:27:08 -07:00 |
Eddie Hung
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82cbfada1b
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Revert "Fix typo"
This reverts commit e3c39cc450 .
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2019-08-09 14:14:28 -07:00 |
Eddie Hung
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747690a6df
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Remove muxY and ffY for now
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2019-08-08 16:33:37 -07:00 |
Eddie Hung
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2c0be7aa5d
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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
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2019-08-08 12:56:05 -07:00 |
Eddie Hung
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07e50b9c25
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Only pack registers if {A,B,P}REG = 0, do not pack $dffe
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2019-08-08 10:51:19 -07:00 |
Eddie Hung
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911129e3ef
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Disable $dffe
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2019-08-08 10:44:49 -07:00 |
Eddie Hung
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675c1d4218
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Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
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2019-08-07 16:29:38 -07:00 |
Eddie Hung
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fb568ddb4e
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Fix compile error
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2019-08-07 14:31:55 -07:00 |
Eddie Hung
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d90b8b081a
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Do not SigSpec::extract() beyond bounds
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2019-08-07 13:58:26 -07:00 |
Eddie Hung
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cdf9c80134
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Do not pack registers if (* keep *)
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2019-08-07 12:57:10 -07:00 |
Eddie Hung
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c39b1a6fcf
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Add comment about supporting $dffe in ice40_dsp
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2019-08-01 15:13:18 -07:00 |
Eddie Hung
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ed7540a46f
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Pack P register properly
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2019-08-01 15:10:43 -07:00 |
Eddie Hung
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e19d33b003
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Cope with sign extension in mul2dsp
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2019-08-01 12:44:56 -07:00 |
Eddie Hung
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c54a39069d
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CO is sign extension only if signed multiplier
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2019-08-01 10:00:49 -07:00 |
Eddie Hung
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e3c39cc450
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Fix typo
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2019-08-01 10:00:01 -07:00 |
Eddie Hung
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e4a638c292
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Restore old CO behaviour
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2019-07-31 15:45:15 -07:00 |
Eddie Hung
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4c25d1a76f
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Pop the CO bit from O
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2019-07-26 10:27:30 -07:00 |
Eddie Hung
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c1a05f4557
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Allow adders/accumulators with 33 bits using CO output
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2019-07-26 10:15:36 -07:00 |
Eddie Hung
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79fd6edc5a
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Eliminate warnings by sizing O correctly
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2019-07-23 15:13:30 -07:00 |
Eddie Hung
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a37574ccbf
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Fix muxAB logic
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2019-07-23 14:52:14 -07:00 |
Eddie Hung
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0dd2a125f6
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Remove debug print
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2019-07-23 14:21:45 -07:00 |
Eddie Hung
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dc0c853abe
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Simplify and fix for MACs
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2019-07-23 14:20:34 -07:00 |
Eddie Hung
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4f11ff8ebd
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Fix typo
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2019-07-23 13:58:56 -07:00 |
Eddie Hung
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33c984a044
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Fix spacing
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2019-07-22 16:37:13 -07:00 |
Eddie Hung
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068617f094
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Pack hi and lo registers separately
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2019-07-22 16:12:57 -07:00 |
Eddie Hung
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4d71ab384d
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Rename according to vendor doc TN1295
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2019-07-22 15:08:26 -07:00 |
Eddie Hung
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304cefbbe2
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Pack Y register
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2019-07-22 15:05:16 -07:00 |
Eddie Hung
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5a14b6e1f6
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Pack adders not just accumulators
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2019-07-22 13:01:49 -07:00 |
Eddie Hung
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e0720a8018
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Restore old ffY behaviour
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2019-07-19 22:47:08 -07:00 |
Eddie Hung
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f9d08a5e5e
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Cleanup
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2019-07-19 20:25:28 -07:00 |
Eddie Hung
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9ad11ea2cc
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Fine tune ice40_dsp.pmg, add support for packing subsets of registers
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2019-07-19 10:57:32 -07:00 |
Eddie Hung
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8f0e796be1
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Add support for ice40 signed multipliers
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2019-07-19 10:38:13 -07:00 |
Eddie Hung
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09411dd996
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ice40_dsp to accept $__MUL16X16 too
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2019-07-18 15:38:28 -07:00 |
Eddie Hung
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802470746c
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Check if RHS is empty first
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2019-07-18 15:22:00 -07:00 |
Eddie Hung
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90ac147eb2
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Do not autoremove ffP aor muxP
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2019-07-18 15:02:41 -07:00 |
Eddie Hung
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08fe63c61e
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Improve pattern matcher to match subsets of $dffe? cells
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2019-07-18 14:08:18 -07:00 |
Eddie Hung
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79d63479ea
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Improve A/B reg packing
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2019-07-18 13:30:35 -07:00 |
Eddie Hung
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e075f0dda0
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Do not autoremove A/B registers since they might have other consumers
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2019-07-18 13:22:22 -07:00 |
Eddie Hung
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0727b2c902
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Fix xilinx_dsp index cast
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2019-07-18 13:18:04 -07:00 |
Eddie Hung
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c76607b9bc
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Wrong wildcard symbol
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2019-07-18 08:14:58 -07:00 |
Eddie Hung
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91629ee4b3
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Pattern matcher to check pool of bits, not exactly
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2019-07-17 12:45:25 -07:00 |
Eddie Hung
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3f677fb0db
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Signed extension
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2019-07-16 15:54:07 -07:00 |
Eddie Hung
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9616dbd125
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Add support {A,B,P}REG packing
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2019-07-16 14:06:32 -07:00 |
Eddie Hung
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5f00d335d4
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Oops forgot these files
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2019-07-15 15:03:15 -07:00 |
Eddie Hung
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dd59375a66
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Add xilinx_dsp for register packing
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2019-07-15 14:46:31 -07:00 |
Clifford Wolf
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cb285e4b87
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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-28 17:17:56 +02:00 |
Clifford Wolf
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b37c31e2cb
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Bugfix in peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 15:34:19 +02:00 |
Clifford Wolf
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2b29aa5c86
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Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:35:45 +02:00 |
Clifford Wolf
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e8c5afcb84
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:25:30 +02:00 |
Clifford Wolf
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b515fd2d25
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Add peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 11:25:15 +02:00 |
Clifford Wolf
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4306bebe58
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pmgen progress
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 10:51:51 +02:00 |
Clifford Wolf
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bb4f3642de
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Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 08:04:22 +02:00 |
Clifford Wolf
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58238da133
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Progress in shiftmul peepopt pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 07:59:39 +02:00 |
Clifford Wolf
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ea547bcaa3
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Add "peepopt" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:38:56 +02:00 |
Clifford Wolf
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9f792c599d
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Add pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:02:05 +02:00 |
Clifford Wolf
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32881a989c
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Support multiple pmg files (right now just concatenated together)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 12:09:02 +02:00 |
Eddie Hung
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408161ea3a
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Misspelling
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2019-04-25 16:46:13 -07:00 |
Eddie Hung
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0deaccbaae
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Fix a few typos
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2019-04-08 16:46:33 -07:00 |
Eddie Hung
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d03780c3f4
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Fix spelling in pmgen/README.md
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2019-03-05 17:55:29 -08:00 |
Larry Doolittle
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57f8bb471f
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Try again for passes/pmgen/ice40_dsp_pm.h rule
Tested on both in-tree and out-of-tree builds
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2019-03-01 20:20:53 -08:00 |
Larry Doolittle
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e2fc18f27b
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Reduce amount of trailing whitespace in code base
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2019-02-28 14:58:11 -08:00 |
Clifford Wolf
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68a6937173
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Fix pmgen for in-tree builds
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 14:56:05 -08:00 |
Clifford Wolf
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64d91219b4
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Fix pmgen for out-of-tree build
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 14:00:58 -08:00 |
Clifford Wolf
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893194689d
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Fix typo in passes/pmgen/README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 18:50:02 +01:00 |
Clifford Wolf
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2fe1c830eb
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Bugfix in ice40_dsp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 13:28:46 +01:00 |
Clifford Wolf
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218e9051bb
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Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 16:42:27 +01:00 |
Clifford Wolf
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dca65d83a0
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Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 11:18:19 +01:00 |
Clifford Wolf
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5a853ed46c
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Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-17 15:35:48 +01:00 |
Clifford Wolf
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8ddec5d882
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Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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5216735210
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Progress in pmgen, add pmgen README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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55ac030382
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Fix pmgen "reject" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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d45379936b
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Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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1f8e76f993
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Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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b9545aa0e1
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Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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ad69c668ce
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Add mockup .pmg (pattern matcher generator) file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |