b6af90fe20
verilog: fix sizing of constant args for tasks/functions
...
- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
2021-02-21 15:44:43 -05:00
220cb1f7bb
verilog: error on macro invocations with missing argument lists
...
This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
2021-02-19 09:18:41 -05:00
27d7741540
Merge pull request #2574 from dh73/master
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Accept disable case for SVA liveness properties.
2021-02-15 17:49:11 +01:00
8de2e863af
verilog: support recursive functions using ternary expressions
...
This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
2021-02-12 14:43:42 -05:00
13c2fd7137
Ganulate Verific support
2021-02-12 10:08:43 +01:00
326f1c9db4
Merge pull request #2573 from zachjs/repeat-call
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verilog: refactored constant function evaluation
2021-02-11 19:56:41 +00:00
73d611990d
Merge pull request #2578 from zachjs/genblk-port
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verlog: allow shadowing module ports within generate blocks
2021-02-11 10:26:49 -05:00
7533534429
Add missing is_signed to type_atom
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-11 15:05:38 +01:00
1d5f3fe506
verlog: allow shadowing module ports within generate blocks
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This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
4b2f977331
genrtlil: fix signed port connection codegen failures
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This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00
c96eb2fbd7
Accept disable case for SVA liveness properties.
2021-02-04 15:35:35 -06:00
98c4feb72f
Add check of begin/end labels for genblock
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-04 17:16:30 +01:00
b93b6f4285
verilog: refactored constant function evaluation
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Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.
2021-02-04 10:18:27 -05:00
baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
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verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
5eff0b73ae
Provide an integer implementation of decimal_digits().
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Signed-off-by: Henner Zeller <h.zeller@acm.org>
2021-02-01 11:23:44 -08:00
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
d99c032c27
Require latest Verific build
2021-01-30 09:23:46 +01:00
a4c04d1b90
ast: fix dump_vlog display of casex/casez
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The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
2021-01-29 16:28:15 +01:00
27257a419f
verilog: strip leading and trailing spaces in macro args
2021-01-28 11:26:35 -05:00
ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces
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verilog: allow spaces in macro arguments
2021-01-25 10:36:07 +00:00
09311b6581
dpi: Support for chandle type
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Signed-off-by: David Shah <dave@ds0.me>
2021-01-23 22:24:31 +00:00
7d014902ec
Fix digit-formatting calculation for small numbers.
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Calling log10() on zero causes a non-sensical value to be calculated. On some
compile options, I've observed yosys crashing with an illegal
instruction (SIGILL).
To make it safe, fix the calculation to do a range check; wrap it a
decimal_digits() function, and use it where the previous ceil(log10(n)) call
was used. As a side, it also improves readability.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2021-01-21 12:20:53 -08:00
1096b969ef
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
acad7a6e40
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-01-20 20:48:10 +01:00
006c18fc11
sv: fix support wire and var data type modifiers
2021-01-20 09:16:21 -07:00
4fadcc8f25
verilog: allow spaces in macro arguments
2021-01-20 08:49:58 -07:00
61501e3266
Fix input/output attributes when resolving typedef of wire
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
09071afe15
Parse package user type in module port list
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
3a8eecebba
Fix indents.
2021-01-04 00:17:16 -08:00
bb3439562e
Add -nosynthesis flag for read_verilog command.
2021-01-04 00:11:01 -08:00
bc2de4567c
Merge pull request #2518 from zachjs/recursion
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verilog: improved support for recursive functions
2021-01-01 09:32:26 +00:00
2085d9a55d
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
75abd90829
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
750831e3e0
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
1419c8761c
Fix constants bound to redeclared function args
...
The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
2020-12-26 08:48:01 -07:00
deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign
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genrtlil: fix mux2rtlil generated wire signedness
2020-12-23 23:15:56 +00:00
8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width
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Fix constants bound to single bit arguments (fixes #2383 )
2020-12-23 23:15:30 +00:00
999eec5617
genrtlil: fix mux2rtlil generated wire signedness
2020-12-22 17:49:16 -07:00
8206546c45
Fix constants bound to single bit arguments ( fixes #2383 )
2020-12-22 17:01:03 -07:00
3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint
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Allow constant function calls in constant function arguments
2020-12-22 01:31:25 +00:00
0d8e5d965f
Sign extend port connections where necessary
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- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
186d6df4c3
Allow constant function calls in constant function arguments
2020-12-07 13:53:27 -07:00
90724ea9e7
Merge pull request #2456 from Zottel/master
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Return correct modname when found in cache.
2020-12-02 22:20:02 +00:00
1c4a18f66f
Bump required Verific version
2020-12-02 15:18:04 +01:00
c1f6ce8b33
Fix SYNTHESIS always being defined in Verilog frontend
2020-12-01 01:37:19 +00:00
2e23dfd96b
Return correct modname when found in cache.
2020-11-26 13:31:22 +01:00
015b476e56
rtlil: remove dotted identifiers.
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No one knows where they came from and they never did anything useful.
2020-11-25 16:47:20 +00:00
c228cb74d6
Update verific version
2020-10-30 08:32:59 +01:00
acc9d0575b
Fix argument handling in connect_rpc
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Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
2020-10-19 13:40:57 +02:00
c8f052bbe0
extend verific library API for formal apps and generators
2020-10-12 14:56:15 +02:00
1b7ed719a5
Update required Verific version
2020-10-05 13:27:27 +02:00
46f0932c4c
Ignore empty parameters in Verilog module instantiations
...
Fixes #2394
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
2020-10-01 18:27:16 +02:00
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low
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Added $high(), $low(), $left(), $right()
2020-10-01 18:17:36 +02:00
a44c5df259
use sha1 for parameter list in case if they contain spaces
2020-09-30 09:16:59 +02:00
44705102b5
Better error for unsupported SVA sequence
2020-09-18 17:08:00 +02:00
f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size
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Rewrite multirange arrays sizes [n] as [n-1:0]
2020-09-17 18:27:05 +02:00
9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access
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Fix unsupported subarray access detection
2020-09-17 18:21:53 +02:00
7ed0e23e19
We can now handle array slices (e.g. $size(x[1]) etc. )
2020-09-17 00:55:17 +03:00
6de7ba02e3
Fixed comments, removed debug message
2020-09-16 10:57:06 +03:00
b548722bee
Added $high(), $low(), $left(), $right()
2020-09-15 20:49:52 +03:00
3f27a4ea68
Use latest verific
2020-09-02 10:22:25 +02:00
a10893072b
Merge pull request #2352 from zachjs/const-func-localparam
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Allow localparams in constant functions
2020-09-01 17:31:48 +02:00
c1a6097376
Merge pull request #2366 from zachjs/library-format
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Simple support for %l format specifier
2020-09-01 17:30:36 +02:00
3e1840d036
Merge pull request #2353 from zachjs/top-scope
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Module name scope support
2020-09-01 17:30:09 +02:00
452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type
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Fix constant args used with function ports split across declarations
2020-09-01 17:28:35 +02:00
04d5692a85
Reorder to prevent crash
2020-08-31 12:22:26 +02:00
3af499c60f
ast recognize lower case x and z and verific gives upper case
2020-08-30 13:33:03 +02:00
2f93579bd1
Do not check for 1 and 0 only
2020-08-30 13:15:06 +02:00
b1e3bc059c
Fix import of VHDL enums
2020-08-30 12:25:23 +02:00
c7ceed3fd3
Simple support for %l format specifier
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Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.
2020-08-29 13:33:31 -04:00
ecc5c23b4d
Fix constant args used with function ports split across declarations
2020-08-29 13:31:02 -04:00
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
...
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
fe8226a22d
Add formal apps and template generators
2020-08-26 10:39:57 +02:00
6127f22788
Module name scope support
2020-08-20 20:15:08 -04:00
74abc3bbfd
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2
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Support 2D bit arrays in structures. Optimise array indexing.
2020-08-19 17:58:37 +02:00
22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
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Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
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Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
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Fix generate scoping issues
2020-08-18 17:37:11 +02:00
7f767bf2b7
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
5ee9349647
Merge pull request #2281 from zachjs/const-real
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Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
2ee0b8ebea
Propagate const_fold through generate blocks and branches
2020-08-09 17:21:08 -04:00
96ec9acf84
Allow %0s $display format specifier
2020-08-09 17:19:49 -04:00
ba08c25133
Fix subarray access condition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 16:16:04 +02:00
83ddc62034
Rewrite multirange arrays sizes [n] as [n-1:0]
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 14:48:27 +02:00
c3e95eb1ab
Fix generate scoping issues
...
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214 , resolves #1456
2020-07-31 20:32:47 -06:00
cc02d58194
Clear last error message
2020-07-29 15:28:33 +02:00
45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors
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Clearer for loop error messages
2020-07-28 14:07:26 +02:00
58da181af9
Clearer for loop error messages
2020-07-25 10:37:16 -06:00
f69daf4830
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
59c4ad8ed3
Avoid generating wires for function args which are constant
2020-07-24 21:18:24 -06:00
f285f7b769
Allow reals as constant function parameters
2020-07-19 20:27:09 -06:00
51ee0b683f
Treat all bison warnings as errors in verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:57:31 +02:00
7a79843cc3
Use %precedence in verilog_parser.y
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:54:28 +02:00
24540291c7
Fix bison warnings for missing %empty
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:50:59 +02:00
1f4e452609
Run bison with -Wall for verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:49:36 +02:00
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
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Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
02c071888b
Add missing semicolons
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-15 10:15:13 +02:00
f9ed09423e
Add AST_EDGE support to AstNode::detect_latch(), fixes #2241
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-10 18:41:13 +02:00
d77b3305d8
Fix S/R conflicts
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This commit fixes S/R conflicts introduced by commit 6f9be93
2020-07-10 15:03:53 +02:00
0ffaddee5e
Fix R/R conflicts
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This commit fixes R/R conflicts introduced by commit 7e83a51
2020-07-10 15:03:01 +02:00
de649b9194
Revert "Revert PRs #2203 and #2244."
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This reverts commit 9c120b89ac
2020-07-10 09:59:48 +02:00
dc35ef05f9
verilog_parser: turn S/R and R/R conflicts into hard errors.
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Fixes #2253 .
2020-07-09 19:36:59 +00:00
9c120b89ac
Revert PRs #2203 and #2244 .
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This reverts commit 7e83a51fc9b422f2e4d07cb56f34b06f9be939bd76a34dc5f3
2020-07-09 19:36:32 +00:00
7e83a51fc9
Support logic typed parameters
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-07-06 09:18:48 +02:00
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial
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verific: rewrite initial assume/asserts prior to elaboration
2020-07-02 17:50:22 +02:00
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
9d658a1970
Merge pull request #2136 from zachjs/master
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Allow constant function calls in for loops and generate if and case
2020-06-30 17:38:49 +02:00
561890c4e8
Update verific API version check
2020-06-30 12:13:13 +02:00
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
b822beb1b2
Fix crash in verific frontend
2020-06-26 20:11:01 +02:00
6f9be939bd
Parse macro call attached semicolon as empty expression
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-26 15:38:20 +02:00
7cb56f34b0
Fix integer signing grammar
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This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:
parameter integer signed i = 0;
parameter integer unsigned i = 0;
Example of incorrect parameters:
parameter signed integer i = 0;
parameter unsigned integer i = 0;
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:35:56 +02:00
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators
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Add logic-assignments operators
2020-06-26 07:30:27 +00:00
d6bdc09422
Merge pull request #2189 from antmicro/optional-labels
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Add support for optional labels
2020-06-26 07:29:24 +00:00
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
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Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
539087f417
Support missing sub-assign and and-assign operators
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 13:29:06 +02:00
4aec50a863
optimization, all items should have same attributes
2020-06-25 09:18:53 +02:00
a4b4c22c96
Support missing xor-assign operator
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 14:32:12 +02:00
a8750b496e
Support optional labels at the end of package definition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
3b81a1b809
Support optional labels at the end of module definition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
22408f24c7
Add plus-assignment operator
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:54:30 +02:00
416a66aee8
Add or-assignment operator
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:53:50 +02:00
f993d18755
verific - import attributes for net buses as well
2020-06-24 11:01:06 +02:00
429d37ff41
static cast: simplify
2020-06-19 19:09:43 -07:00
185bbbe681
static cast: support changing size and signedness
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Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)
Fix #535
2020-06-19 17:39:20 -07:00
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
504f220619
MSVC does not understand __builtin_unreachable
2020-06-17 15:10:08 +02:00
35008e6d40
MSVC cannot omit operand in conditional
2020-06-17 15:10:08 +02:00
b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs
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Do not optimize away FFs in "prep" and Verific front-end
2020-06-10 12:44:23 +02:00
d6bec3ba1c
verific - detect missing memory to prevent crash.
2020-06-10 11:27:44 +02:00
5c426d2bff
Merge pull request #2112 from YosysHQ/claire/fix2040
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Add latch detection for use_case_method in part-select write
2020-06-09 18:27:59 +02:00
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
f80b09fc58
Support 2D packed bit arrays in struct/union.
2020-06-09 13:52:09 +01:00
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
7ad0c49905
Add latch detection for use_case_method in part-select write, fixes #2040
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:25:59 +02:00
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
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Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
71072d1945
Support asymmetric memories for verific frontend
2020-06-01 10:30:03 +02:00
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange
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ilang_lexer: fix check for out of range literal
2020-05-29 09:04:27 +00:00
13b2963ded
ilang_lexer: fix check for out of range literal.
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Commit ca70a104
2020-05-29 06:58:44 +00:00
2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
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verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
6aa0f72ae9
Silence spurious warning in Verilog lexer when compiling with GCC
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The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
1ebf7155a7
aiger: cleanup
2020-05-25 08:43:33 -07:00
c5a9abba11
verilog: move attr from simple_behav_stmt to its children to attach
2020-05-25 07:36:53 -07:00
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
88bddb37c9
verilog: handle empty generate statement by removing gen_stmt_or_null...
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... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
d21a07c7b5
verilog: fix #2037 by permitting (and freeing) attributes on null stmt
2020-05-25 07:36:53 -07:00
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
38e858af8d
Update frontends/verilog/verilog_parser.y
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Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
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This reverts commit 173aa27ca5
2020-05-17 11:31:11 +02:00
39fa1e160d
verific: rewrite initial assume/asserts prior to elaboration
2020-05-15 14:05:28 -07:00
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
4017cc6380
aiger: -xaiger to return $_FF_ flops
2020-05-14 10:33:56 -07:00
6f4f795953
aiger/xaiger: use odd for negedge clk, even for posedge
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Since abc9 doesn't like negative mergeability values
2020-05-14 10:33:56 -07:00
483a190c1b
aiger: -xaiger to parse initial state back into (* init *) on Q wire
2020-05-14 10:33:56 -07:00
53fc3ed645
aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
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according to mergeability class, and init state as cell attr
2020-05-14 10:33:56 -07:00
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix
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Add support for non-power-of-two mem chunks in verific importer
2020-05-14 18:45:13 +02:00
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
173aa27ca5
Add support for non-power-of-two mem chunks in verific importer
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-14 14:38:13 +02:00
237962debd
verilog: default to input in sv mode if task/func has no dir ...
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otherwise error
2020-05-13 13:33:37 -07:00
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
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Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
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C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-06 07:22:17 +00:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
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frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbde241942
Merge pull request #2001 from whitequark/wasi
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Add WASI platform support
2020-05-01 21:28:20 +00:00
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
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Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
adb483ddfd
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
Zachary Snow
Claire Xen
Miodrag Milanovic
whitequark
Kamil Rakoczy
Diego H
Henner Zeller
Marcelina Kościelnicka
David Shah
Lukasz Dalek
Tom Verbeure
georgerennie
Julius Roob
Claire Xenia Wolf
Udi Finkelstein
Kazuki Sakamoto
Anonymous Maarten
Peter Crozier
Eddie Hung
Rupert Swarbrick
Claire Wolf
Xiretza
Alberto Gonzalez
Vamsi K Vytla