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501 Commits

Author SHA1 Message Date
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 014606affe Fix issue with part of PI being 1'bx 2019-06-20 17:38:16 -07:00
Eddie Hung c20adc5263 Add test 2019-06-20 16:07:22 -07:00
Eddie Hung d0bbf9e4d4 Extend sign extension tests 2019-06-20 12:43:59 -07:00
Eddie Hung b77322034c Remove leftover comment 2019-06-20 10:15:04 -07:00
Eddie Hung b98276fa61 Add test 2019-06-20 10:13:52 -07:00
Clifford Wolf a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 13:44:21 +02:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf 6a6dd5e057 Add proper test for SV-style arrays 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:06:07 +02:00
Clifford Wolf 2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Clifford Wolf 5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit 
Improve handling of initial/default values
 2019-06-19 13:53:07 +02:00
Tobias Wölfel 8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf c330379870 Make tests/aiger less chatty 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:20:35 +02:00
Clifford Wolf fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:12:08 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Eddie Hung 9f275c1437 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
 2019-06-12 16:33:05 -07:00
Eddie Hung 2e7b3eee40 Add a couple more tests 2019-06-12 15:43:43 -07:00
Eddie Hung 2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
 2019-06-12 09:05:02 -07:00
Eddie Hung 86efe9a616 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
 2019-06-12 09:01:15 -07:00
Eddie Hung 45c2a5f876 Add shregmap -tech xilinx test 2019-06-12 08:34:06 -07:00
Eddie Hung a138381ac3 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-10 16:21:43 -07:00
Eddie Hung c314ca3c51 Add test 2019-06-10 16:16:26 -07:00
Eddie Hung 352c532bb2 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-10 11:02:54 -07:00
Eddie Hung 1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
Eddie Hung 1e201a9b01 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-07 16:15:19 -07:00
Eddie Hung 58f4b106f3 Merge branch 'master' into eddie/muxpack 2019-06-07 15:47:28 -07:00
Eddie Hung b959bf79c0 Add nonexcl case test, comment out two others 2019-06-07 15:35:15 -07:00
Eddie Hung 1da12c5071 Add @cliffordwolf freduce testcase 2019-06-07 12:12:11 -07:00
Eddie Hung e263bc249b Add nonexclusive test from @cliffordwolf 2019-06-07 11:54:29 -07:00
Eddie Hung 65924fd12f Test *.aag too, by using *.aig as reference 2019-06-07 11:28:05 -07:00
Eddie Hung abc40924ed Use ABC to convert from AIGER to Verilog 2019-06-07 11:06:57 -07:00
Eddie Hung ebe29b6659 Use ABC to convert AIGER to Verilog, then sat against Yosys 2019-06-07 11:05:36 -07:00
Eddie Hung 1b113a0574 Add symbols to AIGER test inputs for ABC 2019-06-07 11:05:25 -07:00
Eddie Hung 0f6e914ef6 Another muxpack test 2019-06-07 08:34:58 -07:00
Clifford Wolf 6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983 
elaboration system tasks
 2019-06-07 13:39:46 +02:00
Clifford Wolf f01a61f093 Rename implicit_ports.sv test to implicit_ports.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 13:12:25 +02:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
Eddie Hung 2223ca91b0 Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:22:10 -07:00
Eddie Hung 5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
Eddie Hung eaee250a6e Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:06:59 -07:00
Eddie Hung 0a66720f6f Fix warnings 2019-06-06 14:01:42 -07:00
Eddie Hung ccdf989025 Support cascading $pmux.A with $mux.A and $mux.B 2019-06-06 13:51:22 -07:00
Eddie Hung 705388eb24 Add non exclusive test 2019-06-06 12:44:06 -07:00
Eddie Hung b8620f7b3d One more and tidy up 2019-06-06 12:03:44 -07:00
Eddie Hung 5d4eca5a29 Add a few more special case tests 2019-06-06 11:59:41 -07:00
Eddie Hung 3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
tux3 88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Eddie Hung f81a0ed92e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-03 23:07:08 -07:00
Maciej Kurc 5739cf5265 Added tests for attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-03 09:25:20 +02:00
Eddie Hung 25befbf542 Rename to #23 2019-05-29 15:26:33 -07:00
Eddie Hung aa2380c17a Add abc_test024 2019-05-29 15:24:38 -07:00
Eddie Hung 92197326b8 Add abc9_test022 2019-05-28 12:43:07 -07:00
Clifford Wolf 349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047 
Do not use shiftmul peepopt pattern when mul result is truncated
 2019-05-28 19:02:26 +02:00
Eddie Hung 5f39c262c2 From master 2019-05-28 09:38:58 -07:00
Eddie Hung ba9513b325 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-28 09:30:53 -07:00
Clifford Wolf cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 17:17:56 +02:00
Clifford Wolf e3ebac44df Add actual wandwor test that is part of "make test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:42:50 +02:00
Bogdan Vukobratovic 9a468f81c4 Optimizing DFFs whose initial value prevents their value from changing 
This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
 2019-05-28 08:48:21 +02:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel f68b658b4b reformat wand/wor test 2019-05-27 18:45:54 +02:00
Stefan Biereigel c5fe04acfd remove port direction workaround from test case 2019-05-27 18:10:39 +02:00
Eddie Hung f3e86e06e6 Fix init 2019-05-24 18:43:26 -07:00
Eddie Hung e1cb1bb948 Fix typos 2019-05-24 18:34:27 -07:00
Eddie Hung d15da4bc11 Add more tests 2019-05-24 18:33:18 -07:00
Eddie Hung 4bd9465ed3 Call proc 2019-05-24 18:32:02 -07:00
Eddie Hung f0c6b73b72 Fix duplicate driver 2019-05-24 17:44:57 -07:00
Eddie Hung 68359bcd6f Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux 2019-05-23 13:37:53 -07:00
Eddie Hung 47f9ea142f Add opt_rmdff tests 2019-05-23 11:26:38 -07:00
Stefan Biereigel c2caf85f7c add simple test case for wand/wor 2019-05-23 13:57:27 +02:00
Eddie Hung fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Maciej Kurc 1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00
Clifford Wolf b7ec698d40 Add test case from #997 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-07 19:58:04 +02:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf 1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968 
Re-enable "final loop assignment" feature and fix opt_clean warnings
 2019-05-06 20:53:38 +02:00
Clifford Wolf 7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import 
Improve verific -chparam and add hierarchy -chparam
 2019-05-06 20:51:59 +02:00
Clifford Wolf d97c644bc1 Add tests/various/chparam.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 16:03:15 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf 8c6e94d57c Improve tests/various/specify.ys 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 12:26:15 +02:00
Eddie Hung 554c58715a More testing 2019-05-03 15:54:25 -07:00
Eddie Hung bfb8b3018b Fix spacing 2019-05-03 15:42:02 -07:00
Eddie Hung 09841c2ac1 Add quick-and-dirty specify tests 2019-05-03 15:35:26 -07:00
Eddie Hung 1e5f072c05 iverilog with simcells.v as well 2019-05-03 14:03:51 -07:00
Clifford Wolf 373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff 
Improve pmgen, Add "peepopt" pass with shift-mul pattern
 2019-05-03 20:39:50 +02:00
Clifford Wolf 71ede7cb05
Merge pull request #976 from YosysHQ/clifford/fix974 
Fix width detection of memory access with bit slice
 2019-05-03 15:29:44 +02:00
Clifford Wolf d2aa123226 Fix typo in tests/svinterfaces/runone.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 14:40:51 +02:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Eddie Hung 8829cba901 Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux 2019-05-02 11:25:34 -07:00
Eddie Hung 5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
Jakob Wenzel 98ffe5fb00 fail svinterfaces testcases on yosys error exit 2019-05-02 09:52:30 +02:00
Jim Lawson 38f5424f92 Fix #938 - Crash occurs in case when use write_firrtl command 
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
 2019-05-01 13:16:01 -07:00
Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 10:01:54 +02:00
Clifford Wolf e5cb9435a0 Add additional test cases for for-loops 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:32:07 +02:00
Clifford Wolf b515fd2d25 Add peepopt_muldiv, fixes #930 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 11:25:15 +02:00
Eddie Hung 0f1ba94924 Remove split_shiftx tests 2019-04-26 19:45:47 -07:00
Eddie Hung 880652283c Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux 2019-04-25 18:52:20 -07:00