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1616 Commits

Author SHA1 Message Date
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung 6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung b47bb5c810 Fix typo in check_label() 2019-10-04 21:43:50 -07:00
Eddie Hung a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung 9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung 4e11782cde Oops 2019-10-04 10:36:02 -07:00
Eddie Hung c0f54d3fd5 Ohmilord this wasn't added all this time!?! 2019-10-04 10:34:16 -07:00
Miodrag Milanovic 44c3472b9f FF should be initialized to 0 2019-10-04 13:27:10 +02:00
Miodrag Milanovic 77d557d00b Add missing latch mapping 2019-10-04 12:58:11 +02:00
Eddie Hung 549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Eddie Hung 655f1b2ac5 English 2019-10-03 10:11:25 -07:00
Eddie Hung 5299884f04 More fixes 2019-10-01 13:41:08 -07:00
Eddie Hung 03ebe43e3e Escape Verilog identifiers for legality outside of Yosys 2019-10-01 13:05:56 -07:00
David Shah b424d374db ecp5: Fix shuffle_enable port 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 14:14:46 +01:00
David Shah 7a1538cd36 ecp5: Add support for mapping 36-bit wide PDP BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 13:46:36 +01:00
Eddie Hung e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung 5e9ae90cbb Add explanation to abc_map.v 2019-09-30 15:39:24 -07:00
Eddie Hung 8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung f6203e6bd6 Missing endmodule 2019-09-29 21:55:53 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 18ebb86edb FDCE_1 does not have IS_CLR_INVERTED 2019-09-29 11:25:34 -07:00
Eddie Hung f3e150d9a5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 09:21:51 -07:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung c372e7baf9 Fix box name 2019-09-27 18:49:45 -07:00
Eddie Hung 8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung 143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung 84825f9378 Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once 2019-09-26 10:45:14 -07:00
Eddie Hung 033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung 781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 35aaa8d73a mul2dsp.v slice names 2019-09-25 22:58:55 -07:00
Eddie Hung 34aa3532fb Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit 2019-09-25 17:26:47 -07:00
Eddie Hung a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" 
This reverts commit 234738b103.
 2019-09-25 17:25:44 -07:00
Eddie Hung f4387e817c Revert "No need for $__mul anymore?" 
This reverts commit 1d875ac76a.
 2019-09-25 17:24:11 -07:00
Eddie Hung 63940913d2 Only wreduce on t:$add 2019-09-25 17:22:04 -07:00
Eddie Hung 234738b103 Remove _TECHMAP_CELLTYPE_ check since all $mul 2019-09-25 16:51:31 -07:00
Eddie Hung 1d875ac76a No need for $__mul anymore? 2019-09-25 14:06:21 -07:00
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 93363c94a2 Oops. Actually use __NAME__ in ABC_DSP48E1 macro 2019-09-25 10:33:16 -07:00
Eddie Hung b41d2fb4e4 Add (* techmap_autopurge *) to abc_unmap.v too 2019-09-23 22:02:22 -07:00
Eddie Hung 11ac37733d Add techmap_autopurge to outputs in abc_map.v too 2019-09-23 21:56:28 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 0f53893104 Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" 
This reverts commit 67c2db3486.
 2019-09-23 19:52:55 -07:00
Eddie Hung 29db96fa1f Revert "Vivado does not like zero width port connections" 
This reverts commit 895e2befa7.
 2019-09-23 19:52:54 -07:00
Eddie Hung 895e2befa7 Vivado does not like zero width port connections 2019-09-23 19:04:07 -07:00
Eddie Hung 67c2db3486 Remove (* techmap_autopurge *) from abc_unmap.v since no effect 2019-09-23 18:56:18 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung 4401e5f142 Grammar 2019-09-20 14:24:31 -07:00
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung 289cf688b7 Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 2019-09-20 09:02:29 -07:00
Eddie Hung 829e4f5d2c Revert "Move mul2dsp before wreduce" 
This reverts commit e4f4f6a9d5.
 2019-09-20 08:56:16 -07:00
Eddie Hung e4f4f6a9d5 Move mul2dsp before wreduce 2019-09-20 08:41:40 -07:00
Eddie Hung 691686f92c Tidy up, fix undriven 2019-09-19 20:04:52 -07:00
Eddie Hung 1602516a8b $__ABC_REG to have WIDTH parameter 2019-09-19 19:37:45 -07:00
Eddie Hung e09f80479e Fix DSP48E1 timing by breaking P path if MREG or PREG 2019-09-19 18:59:28 -07:00
Eddie Hung 362a803779 Revert "Different approach to timing" 
This reverts commit 41256f48a5.
 2019-09-19 18:33:38 -07:00
Eddie Hung 41256f48a5 Different approach to timing 2019-09-19 18:33:29 -07:00
Eddie Hung 5ca25b0c59 Suppress $anyseq warnings 2019-09-19 16:27:14 -07:00
Eddie Hung 595fb611a5 Use (* techmap_autopurge *) to suppress techmap warnings 2019-09-19 15:58:01 -07:00
Eddie Hung c15a35db84 D is 25 bits not 24 bits wide 2019-09-19 15:55:49 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 95db2489bd synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 2019-09-19 14:58:06 -07:00
Eddie Hung 3b9b0fcd06 Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 2019-09-19 14:57:38 -07:00
Marcin Kościelnicki 13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Eddie Hung fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Eddie Hung 25e0f0c376 Fix copy-paste 2019-09-18 12:19:16 -07:00
Eddie Hung b77cf6ba48 Mis-spell 2019-09-18 11:12:46 -07:00
Eddie Hung e992dbf2c5 Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
Eddie Hung 3ec28ec53a
Merge pull request #1379 from mmicko/sim_models 
Added simulation models for Efinix and Anlogic
 2019-09-18 10:04:27 -07:00
Miodrag Milanovic 3e9449cb0b make note that it is for latch mode 2019-09-18 17:48:16 +02:00
Miodrag Milanovic b0ca6de472 better lut handling 2019-09-18 17:45:19 +02:00
Miodrag Milanovic 8badd4d812 better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic 2019-09-15 09:37:16 +02:00
Eddie Hung 681be20ca2 Add `undef DSP48E1_INST 2019-09-13 17:07:18 -07:00
Eddie Hung 61877e1370 Fix D -> P{,COUT} delay 2019-09-13 13:32:55 -07:00
Eddie Hung d0b202c58d Add no MULT no DPORT config 2019-09-13 12:05:14 -07:00
Eddie Hung 247a63f55d Add support for MULT and DPORT 2019-09-13 11:45:55 -07:00
Eddie Hung e235dd0785 Refine diagram 2019-09-13 09:34:40 -07:00
Eddie Hung 734034a872 Add an ASCII drawing 2019-09-12 18:13:46 -07:00
Eddie Hung c52863f147 Finish explanation 2019-09-12 18:01:49 -07:00
Eddie Hung aaeaab4ac0 Rename to techmap_guard 2019-09-12 17:45:02 -07:00
Eddie Hung 6bb8e6a726 Initial DSP48E1 box support 2019-09-12 17:11:01 -07:00
Eddie Hung 3a39073302 Set more ports explicitly 2019-09-12 17:10:43 -07:00
Eddie Hung 0ebbecf833 Missing space 2019-09-11 13:06:59 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 5c1271c51c Move "(skip if -nodsp)" message to label 2019-09-10 15:26:56 -07:00
Eddie Hung f2d030a70f Be sensitive to signedness 2019-09-10 15:14:55 -07:00
Eddie Hung 76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung c460d10e60 Remove wreduce call 2019-09-10 14:17:35 -07:00
Eddie Hung f3a55d3f06 Add comment for why opt_expr is necessary 2019-09-10 14:11:56 -07:00
Eddie Hung 8514e7c32e Revert "Remove "opt_expr -fine" call" 
This reverts commit bfda921d03.
 2019-09-10 14:09:21 -07:00
Eddie Hung d3fb308181 Rename label to map_dsp 2019-09-10 13:18:10 -07:00
Eddie Hung bfda921d03 Remove "opt_expr -fine" call 2019-09-10 13:17:47 -07:00
Eddie Hung a7e6032287 Set USE_MULT and USE_SIMD 2019-09-09 20:56:29 -07:00
Marcin Kościelnicki fda94311ee synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
Pepijn de Vos 2fb20f184a Revert "add MUX support" 
It turns out that they make everything worse and they don't PnR.

This reverts commit 3eff2271d0.
 2019-09-06 11:28:17 +02:00
Pepijn de Vos 96efa63f16 fix BRAM width and init 2019-09-06 10:55:04 +02:00
Pepijn de Vos 1b9f7f49b5 add more DFF to sim lib 2019-09-06 09:01:07 +02:00
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Pepijn de Vos 5168b6ffa4 WIP aditional DFF primitives 2019-09-05 19:12:47 +02:00
Pepijn de Vos 47374a495d support bram initialisation 2019-09-05 17:25:51 +02:00
Pepijn de Vos 7a43be5e43 use singleton ground and vcc nets, apparently this makes pnr happier 2019-09-05 16:38:47 +02:00
Pepijn de Vos 3eff2271d0 add MUX support 2019-09-05 13:36:41 +02:00
Eddie Hung aa1491add3 Resolve TODO with pin assignments for SRL* 2019-09-04 15:47:36 -07:00
Eddie Hung 3732d421c5 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-04 12:37:42 -07:00
Pepijn de Vos ae93c034ad set undriven pads to zero 2019-09-04 16:29:40 +02:00
Pepijn de Vos a6d81a8d14 Merge remote-tracking branch 'diego/gowin' 2019-09-04 11:20:05 +02:00
Pepijn de Vos ec56438cf2 gowin: add splitnets to appease the PnR 2019-09-04 10:33:47 +02:00
Diego H 5aa8d7ceeb Updating gowin 2019-09-02 17:43:27 -05:00
Eddie Hung 3459d28349 Add comments 2019-09-02 12:22:15 -07:00
Eddie Hung 696f854801 Rename box 2019-09-02 12:15:11 -07:00
Eddie Hung 2fa3857963 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-02 12:13:44 -07:00
Miodrag Milanovic a3c16a0565 Fix TRELLIS_FF simulation model 2019-08-31 11:12:06 +02:00
David Shah 90b44113d8 ecp5_gsr: Fix typo 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-31 09:58:46 +01:00
Eddie Hung f33abd4eab Remove trailing space 2019-08-30 16:44:11 -07:00
Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-30 13:26:19 -07:00
Eddie Hung f0fef90e9d Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:30:46 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
David Shah 91b46ed816 ecp5: Add simulation equivalence check for Diamond FF implementations 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-30 13:27:36 +01:00
whitequark d9c621f9d1 ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. 2019-08-30 10:05:09 +00:00
whitequark 1e6b60d563 ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives. 2019-08-30 09:56:19 +00:00
whitequark 6fa8ce93e6 ecp5: add missing FD primitives. 2019-08-30 09:54:48 +00:00
whitequark 7e2825a2a4 ecp5: fix CEMUX on IFS/OFS primitives. 2019-08-30 09:42:33 +00:00
Eddie Hung 25b1670a84 Rename boxes too 2019-08-29 07:03:32 -07:00
Eddie Hung c4e5310823 Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
Eddie Hung e8e3830868 Comment out SB_MAC16 arrival time for now, need to handle all its modes 2019-08-28 19:09:29 -07:00
Eddie Hung 309684af16 Add arrival for SB_MAC16.O 2019-08-28 19:07:28 -07:00
Eddie Hung efa4ee5c0e Add arrival times for U 2019-08-28 19:03:29 -07:00
Eddie Hung 4bda902f1b LX -> LP 2019-08-28 19:02:54 -07:00
Eddie Hung 0f4e9f6bc5 Round not floor 2019-08-28 18:57:34 -07:00
Eddie Hung 927f1e3754 Add LP timings 2019-08-28 18:56:25 -07:00
Eddie Hung e3709e5ee6 LX -> LP 2019-08-28 18:51:14 -07:00
Eddie Hung a4f641f230 Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
Eddie Hung c0b99ed0e8 Do not overwrite LUT param 2019-08-28 18:45:09 -07:00