Alberto Gonzalez
|
9d9bbdce5d
|
Further clean up `passes/cmds/select.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
|
2020-03-16 20:35:19 +00:00 |
Alberto Gonzalez
|
70093698f5
|
Cleanup code style and pseudo-private member usage in `passes/cmds/select.cc`.
|
2020-03-16 20:35:11 +00:00 |
Eddie Hung
|
cdf17c4455
|
opt_merge: unordered_map -> dict as per @cliffordwolf review
|
2020-03-16 12:44:33 -07:00 |
Eddie Hung
|
9f30d7f843
|
opt_merge: speedup
|
2020-03-16 12:43:54 -07:00 |
Alberto Gonzalez
|
8ba49a8462
|
Allow specifying multiple regexes to match in `exec` command output, and also to specify regexes that must _not_ match.
|
2020-03-16 07:52:57 +00:00 |
Alberto Gonzalez
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e6c09f1e0e
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Add `exec` command to run shell commands.
|
2020-03-16 07:52:57 +00:00 |
Miodrag Milanovic
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8f221118d2
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Add YS_ prefix to macros, add explanation and apply to older version as well
|
2020-03-13 17:19:54 +01:00 |
Eddie Hung
|
432a09af80
|
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
|
2020-03-13 08:17:39 -07:00 |
Miodrag Milanovic
|
7c54e61979
|
Use boost xpressive for gcc 4.8
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2020-03-13 14:58:35 +01:00 |
N. Engelhardt
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6986371bac
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Merge pull request #1751 from boqwxp/add_assert
Extend `add` command to allow adding $assert cells.
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2020-03-12 11:18:35 +01:00 |
Eddie Hung
|
dd8ebf7873
|
Merge pull request #1743 from YosysHQ/eddie/abc9_keep
abc9: improve (* keep *) handling
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2020-03-11 06:32:15 -07:00 |
Alberto Gonzalez
|
005dd601ab
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Extend `add` command to allow adding cells for verification like $assert, $assume, etc.
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2020-03-10 21:49:22 +00:00 |
David Shah
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f2550d45ff
|
Merge pull request #1753 from YosysHQ/dave/abc9-speedup
Add ScriptPass::run_nocheck and use for abc9
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2020-03-10 13:51:59 +00:00 |
David Shah
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ddcd87b577
|
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
deminout: Don't demote inouts with unused bits
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2020-03-10 13:51:40 +00:00 |
Alberto Gonzalez
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47537f2e42
|
Clean up passes/cmds/add.cc code style.
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2020-03-10 10:37:10 +00:00 |
David Shah
|
b8abf14376
|
Add ScriptPass::run_nocheck and use for abc9
Signed-off-by: David Shah <dave@ds0.me>
|
2020-03-09 14:34:22 +00:00 |
Eddie Hung
|
80dcc8a0d1
|
abc9: for sccs, create a new wire instead of using entirety of existing
|
2020-03-06 10:30:07 -08:00 |
Eddie Hung
|
91a7a74ac4
|
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
|
2020-03-06 10:20:30 -08:00 |
Eddie Hung
|
2335c59e5b
|
abc: add abc.debug scratchpad option
|
2020-03-06 10:09:01 -08:00 |
David Shah
|
5cae9c6e16
|
deminout: Don't demote inouts with unused bits
Signed-off-by: David Shah <dave@ds0.me>
|
2020-03-04 18:44:38 +00:00 |
Claire Wolf
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879124333f
|
Merge pull request #1519 from YosysHQ/eddie/submod_po
submod: several bugfixes
|
2020-03-03 08:19:06 -08:00 |
Marcelina Kościelnicka
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968956badb
|
iopadmap: Look harder for already-present buffers. (#1731)
iopadmap: Look harder for already-present buffers.
Fixes #1720.
|
2020-03-02 21:40:09 +01:00 |
Eddie Hung
|
4f889b2f57
|
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
|
2020-03-02 12:32:27 -08:00 |
Eddie Hung
|
de3e5fcdc6
|
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
|
2020-02-28 12:33:55 -08:00 |
Eddie Hung
|
78929e8c3d
|
Fixes for older compilers
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
88d5997c80
|
abc9_ops: suppress -prep_box warning for abc9_flop
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
6bb3d9f9c0
|
Make TimingInfo::TimingInfo(SigBit) constructor explicit
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
9dcf204dec
|
TimingInfo: index by (port_name,offset)
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
7c3b4b80ea
|
Fix spacing
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
d6cff77751
|
abc9_ops: still emit delay table even box has no timing
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
683c5ce940
|
abc9_ops: demote lack of box timing info to warning
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
1ef1ca812b
|
Get rid of (* abc9_{arrival,required} *) entirely
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
a6fec9fe60
|
abc9_ops: use TimingInfo for -prep_{lut,box} too
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
3ea5506f81
|
abc9_ops: use TimingInfo for -prep_{lut,box} too
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
cda4acb544
|
abc9_ops: add and use new TimingInfo struct
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
e22fee6cdd
|
abc9_ops: ignore (* abc9_flop *) if not '-dff'
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
7c92b6852f
|
abc9_ops: sort LUT delays to be ascending
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
7317521c6f
|
abc9_ops: output LUT area
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
0ed550d83c
|
abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
12d70ca8fb
|
xilinx: improve specify functionality
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
577545488a
|
xilinx: use specify blocks in place of abc9_{arrival,required}
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
0e7c55e2a7
|
Auto-generate .box/.lut files from specify blocks
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
3d6603792d
|
abc9_ops: assert on $specify2 properties
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
74f49b1f55
|
abc9_ops: -prep_box, to be called once
|
2020-02-27 10:17:29 -08:00 |
Eddie Hung
|
5643c1b8c5
|
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
|
2020-02-27 10:17:29 -08:00 |
Claire Wolf
|
ab8826ae36
|
Merge pull request #1709 from rqou/coolrunner2_counter
Improve CoolRunner-II optimization by using extract_counter pass
|
2020-02-27 19:05:56 +01:00 |
Miodrag Milanović
|
036c46de1e
|
Merge pull request #1705 from YosysHQ/logger_pass
Logger pass
|
2020-02-26 13:32:49 +01:00 |
Miodrag Milanovic
|
48eed2860c
|
Fix line endings
|
2020-02-23 10:05:21 +01:00 |
Miodrag Milanovic
|
010d651450
|
Update explanation for expect-no-warnings
|
2020-02-22 10:53:23 +01:00 |
Miodrag Milanovic
|
596bb2d443
|
Check other regex parameters
|
2020-02-22 10:31:56 +01:00 |
Alberto Gonzalez
|
750e7a9a54
|
Closes #1714. Fix make failure when NDEBUG=1.
|
2020-02-22 06:29:11 +00:00 |
Eddie Hung
|
760096e8d2
|
Merge pull request #1703 from YosysHQ/eddie/specify_improve
Improve specify parser
|
2020-02-21 09:15:17 -08:00 |
Miodrag Milanovic
|
419e67c170
|
check for regex errors
|
2020-02-20 11:41:37 +01:00 |
Eddie Hung
|
1d401a7991
|
clean: ignore specify-s inside cells when determining whether to keep
|
2020-02-19 10:45:10 -08:00 |
Miodrag Milanovic
|
5641b0248f
|
Option to expect no warnings
|
2020-02-17 15:36:06 +01:00 |
R. Ou
|
fec7dc5c9e
|
extract_counter: Implement extracting up counters
|
2020-02-17 03:08:52 -08:00 |
R. Ou
|
940bab6841
|
extract_counter: Add support for inverted clock enable
|
2020-02-17 03:08:52 -08:00 |
R. Ou
|
5fc180ed2d
|
extract_counter: Fix clock enable
|
2020-02-17 03:08:52 -08:00 |
R. Ou
|
12fa4a3121
|
extract_counter: Fix outputting count to module port
|
2020-02-17 03:08:52 -08:00 |
R. Ou
|
508f1ff6a1
|
extract_counter: Allow forbidding async reset
|
2020-02-17 03:08:52 -08:00 |
R. Ou
|
7b922c0d89
|
extract_counter: Refactor out extraction settings into struct
|
2020-02-17 03:08:52 -08:00 |
Tim 'mithro' Ansell
|
b9dfdbbfee
|
show: Add -nobg argument.
Makes yosys wait for the viewer command to finish before continuing.
|
2020-02-15 14:03:16 +01:00 |
Eddie Hung
|
f9f86fd758
|
Revert "abc9: fix abc9_arrival for flops"
This reverts commit f7c0dbecee .
|
2020-02-14 16:08:04 -08:00 |
Miodrag Milanovic
|
31b7a9c312
|
Add expect option to logger command
|
2020-02-14 12:21:16 +01:00 |
Eddie Hung
|
0cf7598cd6
|
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
|
2020-02-13 17:32:54 -08:00 |
Eddie Hung
|
3d2a2e8799
|
iopadmap: fixes as suggested by @mwkmwkmwk
|
2020-02-13 14:57:06 -08:00 |
Eddie Hung
|
f7c0dbecee
|
abc9: fix abc9_arrival for flops
|
2020-02-13 12:34:09 -08:00 |
Eddie Hung
|
00d41905df
|
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
|
2020-02-13 12:33:58 -08:00 |
Eddie Hung
|
ebb11bcea4
|
iopadmap: move \init attributes from outpad output to its input
|
2020-02-13 12:05:14 -08:00 |
Miodrag Milanovic
|
0ba2a2b1fa
|
Add new logger pass
|
2020-02-13 13:35:29 +01:00 |
Eddie Hung
|
c244b27b6d
|
abc9: cleanup
|
2020-02-10 10:17:23 -08:00 |
Eddie Hung
|
e6bb7b0782
|
Fix misc.abc9.abc9_abc9_luts
|
2020-02-07 08:27:45 -08:00 |
whitequark
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60f047f136
|
memory_bram: add `attr_icase` option.
Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
|
2020-02-06 14:58:20 +00:00 |
Eddie Hung
|
505557e93e
|
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
|
2020-02-05 14:56:26 -08:00 |
Eddie Hung
|
0b308c6835
|
abc9_ops: -reintegrate to use derived_type for box_ports
|
2020-02-05 14:46:48 -08:00 |
Eddie Hung
|
5ebdc0f8e0
|
Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
|
2020-02-05 19:31:18 +01:00 |
Eddie Hung
|
0671ae7d79
|
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
|
2020-02-05 18:59:40 +01:00 |
Marcelina Kościelnicka
|
34d2fbd2f9
|
Add opt_lut_ins pass. (#1673)
|
2020-02-03 14:57:17 +01:00 |
David Shah
|
4bfd2ef4f3
|
sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
|
2020-02-02 16:12:33 +00:00 |
David Shah
|
7e741714df
|
hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
|
2020-02-02 16:12:33 +00:00 |
David Shah
|
5df591c023
|
hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
|
2020-02-02 16:12:33 +00:00 |
David Shah
|
1055b6b1dd
|
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
|
2020-02-02 14:53:32 +00:00 |
David Shah
|
65716c9982
|
xilinx_dsp: Add multonly scratchpad var to bypass
Signed-off-by: David Shah <dave@ds0.me>
|
2020-02-01 15:30:43 +00:00 |
Eddie Hung
|
136842b1ef
|
Merge branch 'master' into eddie/submod_po
|
2020-02-01 02:14:19 -08:00 |
Gabriel Somlo
|
8106c3d31b
|
abc9: restore ability to use ABCEXTERNAL
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
|
2020-01-30 15:12:43 -05:00 |
Claire Wolf
|
1679682fa3
|
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Also some minor fixes to the original PR.
|
2020-01-29 17:01:24 +01:00 |
Claire Wolf
|
4d0118d0c1
|
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
opt_reduce: Call check() per run rather than per optimised cell
|
2020-01-29 15:27:11 +01:00 |
Eddie Hung
|
a855f23f22
|
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
|
2020-01-28 12:46:18 -08:00 |
Eddie Hung
|
7939727d14
|
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
|
2020-01-28 11:55:51 -08:00 |
Claire Wolf
|
4ddaa70fd6
|
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
|
2020-01-28 17:40:28 +01:00 |
N. Engelhardt
|
086c133ea5
|
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
synth_xilinx: error out if tristate without '-iopad'
|
2020-01-28 17:24:54 +01:00 |
David Shah
|
6fd9cae5ca
|
opt_reduce: Call check() per run rather than per optimised cell
Signed-off-by: David Shah <dave@ds0.me>
|
2020-01-28 09:42:01 +00:00 |
Pepijn de Vos
|
409e532433
|
redirect fuser stderr to /dev/null
|
2020-01-28 10:02:41 +01:00 |
Eddie Hung
|
21ce1b37fb
|
abc9_ops: -check for negative arrival/required times
|
2020-01-27 14:22:46 -08:00 |
Eddie Hung
|
e18aeda7ed
|
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
|
2020-01-27 14:02:13 -08:00 |
Eddie Hung
|
48f3f5213e
|
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
|
2020-01-27 13:29:15 -08:00 |
Eddie Hung
|
f2576c096c
|
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
|
2020-01-27 12:29:28 -08:00 |
Eddie Hung
|
9009b76a69
|
abc9_ops: add comments
|
2020-01-27 11:18:21 -08:00 |
Eddie Hung
|
b178761551
|
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
|
2020-01-24 11:59:48 -08:00 |
Eddie Hung
|
dbf351390e
|
abc9: -reintegrate recover type from existing cell, check against boxid
|
2020-01-23 22:45:34 -08:00 |
Eddie Hung
|
245873d42d
|
abc9: warning message if no modules selected
|
2020-01-23 19:08:51 -08:00 |
Eddie Hung
|
f180dba753
|
abc9_ops: -prep_xaiger to skip (* keep *) cells
|
2020-01-23 18:56:06 -08:00 |
Eddie Hung
|
1d4314d888
|
abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
|
2020-01-23 14:58:56 -08:00 |
Eddie Hung
|
af0e7637a2
|
alumacc: undo accidental commit
|
2020-01-22 20:54:03 -08:00 |
Eddie Hung
|
8eb5bb258c
|
Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
|
2020-01-22 12:30:14 -08:00 |
Eddie Hung
|
a94b41011d
|
abc9: error out if flip-flop init is 1'b1 for '-dff'
Due to ABC sequential synthesis restriction
|
2020-01-22 10:08:48 -08:00 |
Eddie Hung
|
3b44b53e94
|
abc9: fix scratchpad entry abc9.verify
|
2020-01-22 09:36:54 -08:00 |
Eddie Hung
|
3d9737c1bd
|
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
|
2020-01-21 16:27:40 -08:00 |
Claire Wolf
|
5791c52e1b
|
Merge pull request #1637 from YosysHQ/mwk/fix-1634
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
|
2020-01-21 18:37:06 +01:00 |
Claire Wolf
|
f165a74824
|
Merge pull request #1621 from YosysHQ/clifford/fminit
Add fminit pass
|
2020-01-20 22:01:57 +01:00 |
Eddie Hung
|
6a163b5ddd
|
xilinx_dsp: another typo; move xilinx specific test
|
2020-01-17 17:07:03 -08:00 |
Eddie Hung
|
db68e4c2a7
|
ice40_dsp: fix typo
|
2020-01-17 16:08:04 -08:00 |
Eddie Hung
|
e17f3f8c63
|
Consistency
|
2020-01-17 16:06:20 -08:00 |
Eddie Hung
|
ee500b6d8e
|
xilinx_dsp: add parameter defaults
|
2020-01-17 16:05:10 -08:00 |
Eddie Hung
|
4985318263
|
ice40_dsp: add default values for parameters
|
2020-01-17 15:37:52 -08:00 |
Eddie Hung
|
6692e5d558
|
ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
|
2020-01-17 15:28:02 -08:00 |
Eddie Hung
|
d4e188299b
|
abc9: add some log_{push,pop}() as per @nakengelhardt
|
2020-01-17 12:00:14 -08:00 |
Eddie Hung
|
5a63c19747
|
abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
|
2020-01-15 13:14:48 -08:00 |
Eddie Hung
|
e30b6bbbf8
|
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
|
2020-01-15 09:51:31 -08:00 |
Eddie Hung
|
485e08e436
|
abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
|
2020-01-14 16:33:41 -08:00 |
Eddie Hung
|
f60e071e1c
|
abc9_ops: -check to check abc9_{arrival,required}
|
2020-01-14 15:24:44 -08:00 |
Eddie Hung
|
1c88a6c240
|
abc9_ops: implement a requireds_cache
|
2020-01-14 15:20:04 -08:00 |
Eddie Hung
|
0e4285ca0d
|
abc9_ops: generate flop box ids, add abc9_required to FD* cells
|
2020-01-14 15:05:49 -08:00 |
Eddie Hung
|
588a713b54
|
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
|
2020-01-14 14:28:07 -08:00 |
Eddie Hung
|
4656f202c6
|
abc9_ops: -reintegrate to not trim box padding anymore
|
2020-01-14 14:27:29 -08:00 |
Eddie Hung
|
b951ca9e1c
|
abc9_ops: fix -reintegrate handling of $__ABC9_DELAY
|
2020-01-14 14:06:02 -08:00 |
Marcin Kościelnicki
|
a5d2358a60
|
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
Fixes #1634.
|
2020-01-14 22:49:20 +01:00 |
Eddie Hung
|
ec95fbb273
|
abc9_ops: -prep_times -> -prep_delays; add doc
|
2020-01-14 13:21:58 -08:00 |
Eddie Hung
|
593897ffc0
|
abc9_ops: cleanup
|
2020-01-14 13:13:15 -08:00 |
Eddie Hung
|
300003cb78
|
abc9_ops: discard $__ABC9_DELAY boxes
|
2020-01-14 13:09:54 -08:00 |
Eddie Hung
|
915e7dde73
|
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
|
2020-01-14 12:57:56 -08:00 |
Eddie Hung
|
654247abe9
|
abc9_ops/write_xaiger: update doc
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2020-01-14 12:40:36 -08:00 |
Eddie Hung
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468386d67d
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abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger
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2020-01-14 12:25:45 -08:00 |
Eddie Hung
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53a99ade9c
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
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2020-01-14 11:46:56 -08:00 |
Eddie Hung
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61ffd2d199
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Merge pull request #1633 from YosysHQ/eddie/fix_autoname
autoname: do not rename ports
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2020-01-14 11:40:54 -08:00 |
Eddie Hung
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de969adcd8
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autoname: do not autoname ports
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2020-01-14 10:13:29 -08:00 |
Eddie Hung
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531fddf797
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abc9_ops: -break_scc -> -mark_scc using (* keep *), remove -unbreak_scc
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2020-01-13 23:42:27 -08:00 |
Eddie Hung
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b678b15c6d
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abc9_ops: ignore inouts of all cell outputs for topo ordering
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2020-01-13 23:33:37 -08:00 |
Eddie Hung
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2c65e1abac
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abc9: break SCC by setting (* keep *) on output wires
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2020-01-13 21:45:27 -08:00 |
Eddie Hung
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a2c4d98da7
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abc9: add -run option
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2020-01-13 19:22:23 -08:00 |
Eddie Hung
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a6d4ea7463
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abc9: respect (* keep *) on cells
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2020-01-13 19:21:11 -08:00 |
Eddie Hung
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766e16b525
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read_aiger: make $and/$not/$lut the prefix not suffix
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2020-01-13 17:34:37 -08:00 |
Eddie Hung
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808b388e34
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abc9: log which module is being operated on
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2020-01-13 09:43:57 -08:00 |
Eddie Hung
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9f3cb981d7
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
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2020-01-13 09:22:42 -08:00 |
Eddie Hung
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f9aae90e7a
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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
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2020-01-12 15:19:41 -08:00 |
Eddie Hung
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295e241c07
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cleanup
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2020-01-11 17:28:24 -08:00 |
Eddie Hung
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79db12f238
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
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2020-01-11 17:26:25 -08:00 |
Eddie Hung
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556ed0e18a
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MIssed this merge conflict
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2020-01-11 17:05:30 -08:00 |
Eddie Hung
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c063436eea
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Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
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2020-01-11 17:02:20 -08:00 |
Eddie Hung
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11128dccb5
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Merge branch 'eddie/abc9_refactor' of github.com:YosysHQ/yosys into eddie/abc9_refactor
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2020-01-11 13:56:41 -08:00 |