Clifford Wolf
|
9a1eb45c75
|
Added Verilog parser support for asserts
|
2014-01-19 04:18:22 +01:00 |
Clifford Wolf
|
13359d65ba
|
Fixed parsing of verilog macros at end of line
|
2014-01-18 19:22:20 +01:00 |
Clifford Wolf
|
6170cfe9cd
|
Added verilog_defaults command
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2014-01-17 17:22:29 +01:00 |
Clifford Wolf
|
a3d94bf888
|
Fixed typo in frontends/ast/simplify.cc
|
2014-01-12 21:04:42 +01:00 |
Clifford Wolf
|
8f11eaaca6
|
Added updating of RTLIL::autoidx to ilang frontend
|
2014-01-03 17:51:05 +01:00 |
Clifford Wolf
|
fb2bf934dc
|
Added correct handling of $memwr priority
|
2014-01-03 00:22:17 +01:00 |
Clifford Wolf
|
364f277afb
|
Fixed a stupid access after delete bug
|
2013-12-29 20:18:22 +01:00 |
Clifford Wolf
|
1dcbba1abf
|
Fixed parsing of non-arg macro calls followed by "("
|
2013-12-27 16:25:27 +01:00 |
Clifford Wolf
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72026a934e
|
Fixed parsing of macros with no arguments and expansion text starting with "("
|
2013-12-27 15:05:52 +01:00 |
Clifford Wolf
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369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
fbd06a1afc
|
Added elsif preproc support
|
2013-12-18 13:41:36 +01:00 |
Clifford Wolf
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921064c200
|
Added support for macro arguments
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2013-12-18 13:21:02 +01:00 |
Clifford Wolf
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891e4b5b0d
|
Keep strings as strings in const ternary and concat
|
2013-12-05 13:26:17 +01:00 |
Clifford Wolf
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e935bb6eda
|
Added const folding support for $signed and $unsigned
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2013-12-05 13:09:41 +01:00 |
Clifford Wolf
|
5c39948ead
|
Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
Clifford Wolf
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853538d78b
|
Fixed generate-for (and disabled double warning for auto-wire)
|
2013-12-04 21:33:00 +01:00 |
Clifford Wolf
|
3c220e0b32
|
Added support for $clog2 system function
|
2013-12-04 21:19:54 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
10aa08dca1
|
Fixed temp net name generation in rtlil process generator for abbreviated name matching
|
2013-11-28 21:47:08 +01:00 |
Clifford Wolf
|
0e52f3fa01
|
Added "src" attribute to processes
|
2013-11-28 17:37:50 +01:00 |
Clifford Wolf
|
8dafecd34d
|
Added module->avail_parameters (for advanced techmap features)
|
2013-11-24 20:29:07 +01:00 |
Clifford Wolf
|
7d9a90396d
|
Added verilog frontend -ignore_redef option
|
2013-11-24 19:57:42 +01:00 |
Clifford Wolf
|
019b301541
|
Early wire/reg/parameter width calculation in ast/simplify
|
2013-11-24 19:40:23 +01:00 |
Clifford Wolf
|
0ef22c7609
|
Added support for signed parameters in ilang
|
2013-11-24 17:37:27 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
1de12e1efc
|
Improved handling of initialized registers
|
2013-11-23 16:26:59 +01:00 |
Clifford Wolf
|
295e352ba6
|
Renamed "placeholder" to "blackbox"
|
2013-11-22 15:01:12 +01:00 |
Clifford Wolf
|
a362fd81ae
|
Fixed O(n^2) performance bug in verilog preprocessor
|
2013-11-22 14:08:43 +01:00 |
Clifford Wolf
|
e4429c480e
|
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
|
2013-11-22 12:46:02 +01:00 |
Clifford Wolf
|
95c94a02fc
|
Fixed async proc detection in mem2reg
|
2013-11-21 21:26:56 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
08ceb3729e
|
Fixed ilang parser: memory width
|
2013-11-20 19:55:52 +01:00 |
Clifford Wolf
|
65ad556f3d
|
Another name resolution bugfix for generate blocks
|
2013-11-20 13:57:40 +01:00 |
Clifford Wolf
|
92035fb38e
|
Implemented indexed part selects
|
2013-11-20 13:05:27 +01:00 |
Clifford Wolf
|
c4c299eb5a
|
Do not allow memory bit select on the left side of an assignment
|
2013-11-20 12:18:46 +01:00 |
Clifford Wolf
|
0f04738f40
|
Added "synthesis" in (synopsys|synthesis) comment support
|
2013-11-20 11:44:09 +01:00 |
Clifford Wolf
|
ac2be2d892
|
Fixed name resolution of local tasks and functions in generate block
|
2013-11-20 11:05:58 +01:00 |
Clifford Wolf
|
19dba2561e
|
Implemented part/bit select on memory read
|
2013-11-20 10:51:32 +01:00 |
Clifford Wolf
|
e340532ce5
|
Added init= attribute for fpga-style reset values
|
2013-11-20 01:49:37 +01:00 |
Clifford Wolf
|
0dfdbd991a
|
Fixed parsing of module arguments when one type is used for many args
|
2013-11-19 20:35:31 +01:00 |
Clifford Wolf
|
4f2edcf2f9
|
Fixed two bugs in mem2reg functionality in AST frontend
|
2013-11-18 19:55:12 +01:00 |
Clifford Wolf
|
79910a5547
|
Added dumping of attributes in AST frontend
|
2013-11-18 19:54:36 +01:00 |
Clifford Wolf
|
2a25e3bca3
|
Fixed parsing of default cases when not last case
|
2013-11-18 16:10:50 +01:00 |
Clifford Wolf
|
de03184150
|
Fixed mem2reg for reg usage outside always block
|
2013-11-18 12:35:41 +01:00 |
Clifford Wolf
|
63060dcd2e
|
Fixed parsing of "parameter integer"
|
2013-11-13 15:30:23 +01:00 |
Clifford Wolf
|
e5b974fa2a
|
Cleanups and bugfixes in response to new internal cell checker
|
2013-11-11 00:39:45 +01:00 |
Clifford Wolf
|
378cc509cd
|
Call internal checker more often
|
2013-11-10 23:24:21 +01:00 |
Clifford Wolf
|
259cc1391e
|
More undef-propagation related fixes
|
2013-11-08 11:40:36 +01:00 |
Clifford Wolf
|
9f49d538e1
|
Fixed handling of different signedness in power operands
|
2013-11-08 11:06:11 +01:00 |
Clifford Wolf
|
4abc8e695a
|
Implemented const folding of ternary op with undef select
|
2013-11-08 04:44:09 +01:00 |
Clifford Wolf
|
fc6dc0d7b8
|
Fixed handling of power operator
|
2013-11-07 22:20:00 +01:00 |
Clifford Wolf
|
d7cb62ac96
|
Fixed more extend vs. extend_u0 issues
|
2013-11-07 19:20:20 +01:00 |
Clifford Wolf
|
02f4f89fdb
|
Disabled const folding of ternary op when select is undef
|
2013-11-07 18:18:16 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
ed4bcd52e5
|
Fixed sign handling in constants
|
2013-11-07 14:53:10 +01:00 |
Clifford Wolf
|
83a8b8b5ca
|
Fixed const folding in corner cases with parameters
|
2013-11-07 14:08:53 +01:00 |
Clifford Wolf
|
b52bf379b9
|
Fixed width detection for replicate operator
|
2013-11-07 12:43:04 +01:00 |
Clifford Wolf
|
536621a98b
|
Fixed at_zero evaluation of dynamic ranges
|
2013-11-07 11:25:19 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
160adccca2
|
Fixed the fix for propagation of width hints for $signed() and $unsigned()
|
2013-11-07 03:01:28 +01:00 |
Clifford Wolf
|
7fe13faefa
|
Fixed propagation of width hints for $signed() and $unsigned()
|
2013-11-06 22:41:21 +01:00 |
Clifford Wolf
|
baeca48a24
|
Additional fixes for undef propagation in concat and replicate ops
|
2013-11-06 21:16:54 +01:00 |
Clifford Wolf
|
6fcbc79b5c
|
Improved width extension with regard to undef propagation
|
2013-11-06 21:05:11 +01:00 |
Clifford Wolf
|
f2786df146
|
Another fix for early width and sign detection in ast simplifier
|
2013-11-04 21:29:36 +01:00 |
Clifford Wolf
|
d38c67f53d
|
Fixed const folding of ternary operator
|
2013-11-04 16:46:14 +01:00 |
Clifford Wolf
|
8d226da694
|
Use proper bit width ans sign extension for const folding
|
2013-11-04 15:37:09 +01:00 |
Clifford Wolf
|
1325514d33
|
Fixes for early width and sign detection in ast simplifier
|
2013-11-04 08:28:13 +01:00 |
Clifford Wolf
|
472117d532
|
further improved early width and sign detection in ast simplifier
|
2013-11-04 06:04:42 +01:00 |
Clifford Wolf
|
d2b083f5cb
|
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
|
2013-11-03 18:56:45 +01:00 |
Clifford Wolf
|
ada80545fa
|
Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
|
2013-11-02 21:13:01 +01:00 |
Clifford Wolf
|
943329c1dc
|
Various ast changes for early expression width detection (prep for constfold fixes)
|
2013-11-02 13:00:17 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Clifford Wolf
|
eae43e2db4
|
Fixed handling of boolean attributes (kernel)
|
2013-10-24 10:59:27 +02:00 |
Clifford Wolf
|
77726fb5fe
|
Fixed parsing of value-less attributes in ilang
|
2013-10-23 18:38:31 +02:00 |
Johann Glaser
|
f352205635
|
fixed Verilog parser filename and line numbering issue with include files
|
2013-08-21 09:20:59 +02:00 |
Johann Glaser
|
a99c224157
|
Added support for include directories with the new '-I' argument of the
'read_verilog' command
|
2013-08-20 15:48:16 +02:00 |
Johann Glaser
|
6c4cbc03c2
|
Added support for notif0/notif1 primitives
|
2013-08-20 11:23:59 +02:00 |
Clifford Wolf
|
0003743432
|
Fixed width and sign detection for ** operator
|
2013-08-19 20:58:01 +02:00 |
Clifford Wolf
|
8656b1c08f
|
Added support for bufif0/bufif1 primitives
|
2013-08-19 19:50:04 +02:00 |
Clifford Wolf
|
4214561890
|
Improved ast dumping (ast/verilog frontend)
|
2013-08-19 19:49:14 +02:00 |
Clifford Wolf
|
759852914d
|
Added support for "2**n" shifter encoding
|
2013-08-12 14:47:50 +02:00 |
Clifford Wolf
|
c8763301b4
|
Added $div and $mod technology mapping
|
2013-08-09 17:09:24 +02:00 |
Clifford Wolf
|
0f38008ed3
|
Added "design" command (-reset, -save, -load)
|
2013-07-27 14:27:51 +02:00 |
Clifford Wolf
|
3650fd7fbe
|
More fixes in ternary op sign handling
|
2013-07-12 13:13:04 +02:00 |
Clifford Wolf
|
ded769c98c
|
Fixed sign handling in ternary operator
|
2013-07-12 01:15:37 +02:00 |
Clifford Wolf
|
b380c8c790
|
Another vloghammer related bugfix
|
2013-07-11 19:24:59 +02:00 |
Clifford Wolf
|
ed62fcdbe2
|
Fixed sign propagation in bit-wise operators
|
2013-07-09 23:53:55 +02:00 |
Clifford Wolf
|
5dab327b30
|
More fixes in ast expression sign/width handling
|
2013-07-09 23:41:43 +02:00 |
Clifford Wolf
|
00a6c1d9a5
|
Major redesign of expr width/sign detecion (verilog/ast frontend)
|
2013-07-09 14:31:57 +02:00 |
Clifford Wolf
|
e8da3ea7b6
|
Fixed another bug found using vloghammer
|
2013-07-07 16:49:30 +02:00 |
Clifford Wolf
|
eff68560a2
|
Fixed AST_CONSTANT node generation
|
2013-07-07 15:40:26 +02:00 |
Clifford Wolf
|
56432a920f
|
Added defparam support to Verilog/AST frontend
|
2013-07-04 14:12:33 +02:00 |
Clifford Wolf
|
0c6ffc4c65
|
More fixes for bugs found using xsthammer
|
2013-06-13 11:18:45 +02:00 |
Clifford Wolf
|
4b311b7b99
|
Further improved and extended xsthammer
|
2013-06-11 19:49:35 +02:00 |
Clifford Wolf
|
a5c30183b5
|
Sign-extension related fixes in SatGen and AST frontend
|
2013-06-10 17:10:06 +02:00 |