Clifford Wolf
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1d00ad9d4d
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Progress in Verific bindings
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2014-03-15 14:36:11 +01:00 |
Clifford Wolf
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e37d672ae7
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Progress in Verific bindings
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2014-03-14 16:40:25 +01:00 |
Clifford Wolf
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0ac915a757
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Progress in Verific bindings
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2014-03-14 11:46:13 +01:00 |
Clifford Wolf
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9a1accf692
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Progress in Verific bindings
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2014-03-13 18:21:00 +01:00 |
Clifford Wolf
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6a53bc7b27
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Copy Verific vdbs files to Yosys "share" data directory
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2014-03-13 17:34:31 +01:00 |
Clifford Wolf
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7a1ac11203
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Added test_navre.ys for verific frontend
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2014-03-13 13:12:06 +01:00 |
Clifford Wolf
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fad8558eb5
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Merged OSX fixes from Siesh1oo with some modifications
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2014-03-13 12:48:10 +01:00 |
Clifford Wolf
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91704a7853
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Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
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2014-03-11 14:24:24 +01:00 |
Clifford Wolf
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9992026a8d
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Added support for `line compiler directive
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2014-03-11 14:06:57 +01:00 |
Clifford Wolf
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5a15539c9b
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Improved verific command (added support for some operators)
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2014-03-10 12:06:57 +01:00 |
Clifford Wolf
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c71791a1ff
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Improvements in verific command
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2014-03-10 03:03:08 +01:00 |
Clifford Wolf
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8d06f9f2fe
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Added "verific" command
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2014-03-09 20:40:04 +01:00 |
Clifford Wolf
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620d51d9f7
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Bugfix in ilang frontend autoidx recovery
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2014-03-07 17:19:14 +01:00 |
Clifford Wolf
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4d07f88258
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Fixed gcc compiler warning
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2014-03-06 16:37:19 +01:00 |
Clifford Wolf
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09805ee9ec
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Include id2ast pointers when dumping AST
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2014-03-05 19:56:31 +01:00 |
Clifford Wolf
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d6a01fe412
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Fixed merging of compatible wire decls in AST frontend
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2014-03-05 19:55:58 +01:00 |
Clifford Wolf
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de7bd12004
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Bugfix in recursive AST simplification
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2014-03-05 19:45:33 +01:00 |
Clifford Wolf
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ef90236a5d
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Fixed vhdl2verilog temp dir name
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2014-03-01 17:48:15 +01:00 |
Clifford Wolf
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04999f4af0
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Fixed vhdl2verilog help message
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2014-03-01 17:47:19 +01:00 |
Clifford Wolf
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ae5032af84
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Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
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2014-02-26 21:32:19 +01:00 |
Clifford Wolf
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6bc94b7eb2
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Don't blow up constants unneccessarily in Verilog frontend
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2014-02-24 12:41:25 +01:00 |
Clifford Wolf
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f8c9143b2b
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Fixed bug in generation of undefs for $memwr MUXes
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2014-02-22 17:08:00 +01:00 |
Clifford Wolf
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0a60f95224
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Added vhdl2verilog
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2014-02-21 18:59:49 +01:00 |
Clifford Wolf
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4bd25edcd4
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Cleanups in handling of read_verilog -defer and -icells
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2014-02-20 19:12:32 +01:00 |
Clifford Wolf
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02e6f2c5be
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Added Verilog support for "`default_nettype none"
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2014-02-17 14:28:52 +01:00 |
Clifford Wolf
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7d7e068dd1
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Added a warning note about error reporting to read_verilog help message
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2014-02-16 20:20:25 +01:00 |
Clifford Wolf
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7ac524e8e8
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Improved support for constant functions
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2014-02-16 13:16:38 +01:00 |
Clifford Wolf
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118517ca5a
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Added ff and latch support to read_liberty
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2014-02-15 19:44:19 +01:00 |
Clifford Wolf
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96b1ebc8dc
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Bugfix in expression parser of read_liberty
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2014-02-15 19:36:09 +01:00 |
Clifford Wolf
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5e39e6ece2
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Correctly convert constants to RTLIL (fixed undef handling)
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2014-02-15 15:42:10 +01:00 |
Clifford Wolf
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4440610d3f
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Added liberty frontend
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2014-02-15 12:57:28 +01:00 |
Clifford Wolf
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45d2b6ffce
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Be more conservative with new const-function code
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2014-02-14 20:45:30 +01:00 |
Clifford Wolf
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e8af3def7f
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Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
Clifford Wolf
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534c1a5dd0
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Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
Clifford Wolf
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cd9e8741a7
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Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
Clifford Wolf
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007bdff55d
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Added support for functions returning integer
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2014-02-12 23:29:54 +01:00 |
Clifford Wolf
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0defc86519
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renamed ilang "scope error" to "ilang error"
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2014-02-11 19:17:07 +01:00 |
Clifford Wolf
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fb186e6299
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Improved ilang parser error messages
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2014-02-09 15:35:31 +01:00 |
Clifford Wolf
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f4f230d7cc
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Fixed gcc compiler warnings with release build
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2014-02-06 22:49:14 +01:00 |
Clifford Wolf
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aa8e754ae5
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Added read_verilog -setattr
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2014-02-05 11:22:10 +01:00 |
Clifford Wolf
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d267bcde4e
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Fixed bug in sequential sat proofs and improved handling of asserts
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2014-02-04 12:46:16 +01:00 |
Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
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cdd6e11af5
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Added support for blanks after -I and -D in read_verilog
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2014-02-02 13:06:21 +01:00 |
Clifford Wolf
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af325bf206
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Fixed comment/eol parsing in ilang frontend
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2014-02-01 17:28:02 +01:00 |
Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
Clifford Wolf
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4df7e03ec9
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
Clifford Wolf
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375c4dddc1
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Added read_verilog -icells option
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2014-01-29 00:59:28 +01:00 |
Clifford Wolf
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0b47d907d3
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Fixed handling of unsized constants in verilog frontend
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2014-01-24 15:05:24 +01:00 |
Clifford Wolf
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88fbdd4916
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Fixed algorithmic complexity of AST simplification of long expressions
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2014-01-20 20:25:20 +01:00 |
Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |