2013-01-05 04:13:26 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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2021-06-07 17:39:36 -05:00
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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2018-10-13 13:34:44 -05:00
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* This is the AST frontend library.
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*
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* The AST frontend library is not a frontend on it's own but provides a
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* generic abstract syntax tree (AST) abstraction for HDL code and can be
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* used by HDL frontends. See "ast.h" for an overview of the API and the
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* Verilog frontend for an usage example.
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*
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*/
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2014-12-29 07:30:33 -06:00
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#include "kernel/yosys.h"
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2013-02-27 02:32:19 -06:00
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#include "libs/sha1/sha1.h"
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2013-01-05 04:13:26 -06:00
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#include "ast.h"
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2014-07-31 06:19:47 -05:00
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YOSYS_NAMESPACE_BEGIN
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2013-01-05 04:13:26 -06:00
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using namespace AST;
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using namespace AST_INTERNAL;
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2018-12-07 13:14:07 -06:00
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// instantiate global variables (public API)
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2013-01-05 04:13:26 -06:00
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namespace AST {
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std::string current_filename;
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void (*set_line_num)(int) = NULL;
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int (*get_line_num)() = NULL;
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}
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2018-12-07 13:14:07 -06:00
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// instantiate global variables (private API)
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2013-01-05 04:13:26 -06:00
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namespace AST_INTERNAL {
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2019-03-21 14:52:29 -05:00
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bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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2019-06-19 07:38:50 -05:00
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bool flag_nomem2reg, flag_mem2reg, flag_noblackbox, flag_lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_autowire;
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2013-01-05 04:13:26 -06:00
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AstNode *current_ast, *current_ast_mod;
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std::map<std::string, AstNode*> current_scope;
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2014-12-28 12:24:24 -06:00
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const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
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2013-03-31 04:51:12 -05:00
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RTLIL::SigSpec ignoreThisSignalsInInitial;
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2015-02-14 03:49:30 -06:00
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AstNode *current_always, *current_top_block, *current_block, *current_block_child;
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2020-04-20 08:41:55 -05:00
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Module *current_module;
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2016-09-06 10:34:42 -05:00
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bool current_always_clocked;
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2021-02-23 09:48:29 -06:00
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dict<std::string, int> current_memwr_count;
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dict<std::string, pool<int>> current_memwr_visible;
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2013-01-05 04:13:26 -06:00
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}
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// convert node types to string
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std::string AST::type2str(AstNodeType type)
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{
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switch (type)
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{
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#define X(_item) case _item: return #_item;
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X(AST_NONE)
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X(AST_DESIGN)
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X(AST_MODULE)
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X(AST_TASK)
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X(AST_FUNCTION)
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2014-08-21 05:43:51 -05:00
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X(AST_DPI_FUNCTION)
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2013-01-05 04:13:26 -06:00
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X(AST_WIRE)
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X(AST_MEMORY)
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X(AST_AUTOWIRE)
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X(AST_PARAMETER)
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X(AST_LOCALPARAM)
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2013-07-04 07:12:33 -05:00
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X(AST_DEFPARAM)
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2013-01-05 04:13:26 -06:00
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X(AST_PARASET)
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X(AST_ARGUMENT)
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X(AST_RANGE)
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2014-08-06 08:43:46 -05:00
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X(AST_MULTIRANGE)
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2013-01-05 04:13:26 -06:00
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X(AST_CONSTANT)
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2014-06-13 04:29:23 -05:00
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X(AST_REALVALUE)
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2013-01-05 04:13:26 -06:00
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X(AST_CELLTYPE)
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X(AST_IDENTIFIER)
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2013-02-26 06:18:22 -06:00
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X(AST_PREFIX)
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2014-01-18 21:18:22 -06:00
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X(AST_ASSERT)
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2015-02-26 11:47:39 -06:00
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X(AST_ASSUME)
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2017-02-25 03:36:39 -06:00
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X(AST_LIVE)
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X(AST_FAIR)
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2017-02-04 07:14:26 -06:00
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X(AST_COVER)
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2018-03-09 06:47:11 -06:00
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X(AST_ENUM)
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X(AST_ENUM_ITEM)
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2013-01-05 04:13:26 -06:00
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X(AST_FCALL)
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2014-02-01 06:50:23 -06:00
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X(AST_TO_BITS)
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2013-01-05 04:13:26 -06:00
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X(AST_TO_SIGNED)
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X(AST_TO_UNSIGNED)
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2020-04-29 07:28:04 -05:00
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X(AST_SELFSZ)
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2020-06-14 17:15:59 -05:00
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X(AST_CAST_SIZE)
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2013-01-05 04:13:26 -06:00
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X(AST_CONCAT)
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X(AST_REPLICATE)
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X(AST_BIT_NOT)
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X(AST_BIT_AND)
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X(AST_BIT_OR)
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X(AST_BIT_XOR)
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X(AST_BIT_XNOR)
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X(AST_REDUCE_AND)
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X(AST_REDUCE_OR)
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X(AST_REDUCE_XOR)
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X(AST_REDUCE_XNOR)
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X(AST_REDUCE_BOOL)
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X(AST_SHIFT_LEFT)
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X(AST_SHIFT_RIGHT)
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X(AST_SHIFT_SLEFT)
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X(AST_SHIFT_SRIGHT)
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2020-04-27 10:04:47 -05:00
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X(AST_SHIFTX)
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X(AST_SHIFT)
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2013-01-05 04:13:26 -06:00
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X(AST_LT)
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X(AST_LE)
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X(AST_EQ)
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X(AST_NE)
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2013-12-27 06:50:08 -06:00
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X(AST_EQX)
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X(AST_NEX)
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2013-01-05 04:13:26 -06:00
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X(AST_GE)
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X(AST_GT)
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X(AST_ADD)
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X(AST_SUB)
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X(AST_MUL)
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X(AST_DIV)
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X(AST_MOD)
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X(AST_POW)
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X(AST_POS)
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X(AST_NEG)
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X(AST_LOGIC_AND)
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X(AST_LOGIC_OR)
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X(AST_LOGIC_NOT)
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X(AST_TERNARY)
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X(AST_MEMRD)
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X(AST_MEMWR)
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2015-02-14 03:49:30 -06:00
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X(AST_MEMINIT)
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2013-01-05 04:13:26 -06:00
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X(AST_TCALL)
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X(AST_ASSIGN)
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X(AST_CELL)
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X(AST_PRIMITIVE)
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2014-06-07 04:48:50 -05:00
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X(AST_CELLARRAY)
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2013-01-05 04:13:26 -06:00
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X(AST_ALWAYS)
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2013-03-31 04:19:11 -05:00
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X(AST_INITIAL)
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2013-01-05 04:13:26 -06:00
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X(AST_BLOCK)
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X(AST_ASSIGN_EQ)
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X(AST_ASSIGN_LE)
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X(AST_CASE)
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X(AST_COND)
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2016-04-21 08:31:54 -05:00
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X(AST_CONDX)
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X(AST_CONDZ)
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2013-01-05 04:13:26 -06:00
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X(AST_DEFAULT)
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X(AST_FOR)
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2014-02-14 13:33:22 -06:00
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X(AST_WHILE)
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2014-06-06 10:40:04 -05:00
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X(AST_REPEAT)
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2013-01-05 04:13:26 -06:00
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X(AST_GENVAR)
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X(AST_GENFOR)
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X(AST_GENIF)
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2013-12-04 14:06:54 -06:00
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X(AST_GENCASE)
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2013-01-05 04:13:26 -06:00
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X(AST_GENBLOCK)
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2019-05-02 19:10:43 -05:00
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X(AST_TECALL)
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2013-01-05 04:13:26 -06:00
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X(AST_POSEDGE)
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X(AST_NEGEDGE)
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X(AST_EDGE)
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2019-09-20 05:16:20 -05:00
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X(AST_INTERFACE)
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X(AST_INTERFACEPORT)
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X(AST_INTERFACEPORTTYPE)
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X(AST_MODPORT)
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X(AST_MODPORTMEMBER)
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2016-06-18 03:24:21 -05:00
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X(AST_PACKAGE)
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2019-09-19 14:43:13 -05:00
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X(AST_WIRETYPE)
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X(AST_TYPEDEF)
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2020-05-08 08:40:49 -05:00
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X(AST_STRUCT)
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2020-05-12 08:25:33 -05:00
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X(AST_UNION)
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2020-05-08 08:40:49 -05:00
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X(AST_STRUCT_ITEM)
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2020-05-21 11:36:29 -05:00
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X(AST_BIND)
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2013-01-05 04:13:26 -06:00
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#undef X
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default:
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2013-05-24 07:38:36 -05:00
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log_abort();
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2013-01-05 04:13:26 -06:00
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}
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}
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2013-10-24 04:20:13 -05:00
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// check if attribute exists and has non-zero value
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bool AstNode::get_bool_attribute(RTLIL::IdString id)
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{
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if (attributes.count(id) == 0)
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return false;
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AstNode *attr = attributes.at(id);
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if (attr->type != AST_CONSTANT)
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2023-04-04 04:53:50 -05:00
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attr->input_error("Attribute `%s' with non-constant value!\n", id.c_str());
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2013-10-24 04:20:13 -05:00
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return attr->integer != 0;
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}
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2013-01-05 04:13:26 -06:00
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// create new node (AstNode constructor)
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// (the optional child arguments make it easier to create AST trees)
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2021-05-20 19:27:06 -05:00
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AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3, AstNode *child4)
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2013-01-05 04:13:26 -06:00
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{
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2014-12-28 20:11:50 -06:00
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static unsigned int hashidx_count = 123456789;
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hashidx_count = mkhash_xorshift(hashidx_count);
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hashidx_ = hashidx_count;
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2013-01-05 04:13:26 -06:00
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this->type = type;
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filename = current_filename;
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is_input = false;
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is_output = false;
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is_reg = false;
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2018-03-09 02:35:33 -06:00
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is_logic = false;
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2013-01-05 04:13:26 -06:00
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is_signed = false;
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2013-12-05 06:26:17 -06:00
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is_string = false;
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2018-03-09 06:47:11 -06:00
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is_enum = false;
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2019-05-23 06:42:30 -05:00
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is_wand = false;
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is_wor = false;
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2019-05-27 04:42:10 -05:00
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is_unsized = false;
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2018-06-05 09:44:24 -05:00
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was_checked = false;
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2013-01-05 04:13:26 -06:00
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range_valid = false;
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2014-07-28 07:25:03 -05:00
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range_swapped = false;
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2019-09-19 14:43:13 -05:00
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is_custom_type = false;
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2013-01-05 04:13:26 -06:00
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port_id = 0;
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range_left = -1;
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range_right = 0;
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integer = 0;
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2014-06-14 05:00:47 -05:00
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realvalue = 0;
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2013-01-05 04:13:26 -06:00
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id2ast = NULL;
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2014-01-20 13:25:20 -06:00
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basic_prep = false;
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2020-04-15 13:36:40 -05:00
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lookahead = false;
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2013-01-05 04:13:26 -06:00
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if (child1)
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children.push_back(child1);
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if (child2)
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children.push_back(child2);
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2016-07-27 08:40:17 -05:00
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if (child3)
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children.push_back(child3);
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2021-05-20 19:27:06 -05:00
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if (child4)
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children.push_back(child4);
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2013-01-05 04:13:26 -06:00
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}
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// create a (deep recursive) copy of a node
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2017-09-29 23:37:38 -05:00
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AstNode *AstNode::clone() const
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2013-01-05 04:13:26 -06:00
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{
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AstNode *that = new AstNode;
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*that = *this;
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for (auto &it : that->children)
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it = it->clone();
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for (auto &it : that->attributes)
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it.second = it.second->clone();
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return that;
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}
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// create a (deep recursive) copy of a node use 'other' as target root node
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2017-09-29 23:37:38 -05:00
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void AstNode::cloneInto(AstNode *other) const
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2013-01-05 04:13:26 -06:00
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{
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AstNode *tmp = clone();
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other->delete_children();
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*other = *tmp;
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tmp->children.clear();
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tmp->attributes.clear();
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delete tmp;
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}
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// delete all children in this node
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void AstNode::delete_children()
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{
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for (auto &it : children)
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delete it;
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children.clear();
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for (auto &it : attributes)
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delete it.second;
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attributes.clear();
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}
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// AstNode destructor
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AstNode::~AstNode()
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{
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delete_children();
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}
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// create a nice text representation of the node
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// (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
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2017-09-29 23:37:38 -05:00
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void AstNode::dumpAst(FILE *f, std::string indent) const
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2013-01-05 04:13:26 -06:00
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{
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if (f == NULL) {
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for (auto f : log_files)
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2013-08-19 12:49:14 -05:00
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dumpAst(f, indent);
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2013-01-05 04:13:26 -06:00
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return;
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}
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std::string type_name = type2str(type);
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2021-02-23 12:22:53 -06:00
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fprintf(f, "%s%s <%s>", indent.c_str(), type_name.c_str(), loc_string().c_str());
|
2014-03-05 12:56:31 -06:00
|
|
|
|
2018-08-23 07:19:46 -05:00
|
|
|
if (!flag_no_dump_ptr) {
|
|
|
|
if (id2ast)
|
|
|
|
fprintf(f, " [%p -> %p]", this, id2ast);
|
|
|
|
else
|
|
|
|
fprintf(f, " [%p]", this);
|
|
|
|
}
|
2014-03-05 12:56:31 -06:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (!str.empty())
|
|
|
|
fprintf(f, " str='%s'", str.c_str());
|
|
|
|
if (!bits.empty()) {
|
|
|
|
fprintf(f, " bits='");
|
|
|
|
for (size_t i = bits.size(); i > 0; i--)
|
2019-08-07 13:12:38 -05:00
|
|
|
fprintf(f, "%c", bits[i-1] == State::S0 ? '0' :
|
|
|
|
bits[i-1] == State::S1 ? '1' :
|
2013-01-05 04:13:26 -06:00
|
|
|
bits[i-1] == RTLIL::Sx ? 'x' :
|
|
|
|
bits[i-1] == RTLIL::Sz ? 'z' : '?');
|
2014-10-11 04:42:08 -05:00
|
|
|
fprintf(f, "'(%d)", GetSize(bits));
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
if (is_input)
|
|
|
|
fprintf(f, " input");
|
|
|
|
if (is_output)
|
|
|
|
fprintf(f, " output");
|
2018-03-09 02:35:33 -06:00
|
|
|
if (is_logic)
|
|
|
|
fprintf(f, " logic");
|
|
|
|
if (is_reg) // this is an AST dump, not Verilog - if we see "logic reg" that's fine.
|
2013-01-05 04:13:26 -06:00
|
|
|
fprintf(f, " reg");
|
|
|
|
if (is_signed)
|
|
|
|
fprintf(f, " signed");
|
2021-03-03 13:36:19 -06:00
|
|
|
if (is_unsized)
|
|
|
|
fprintf(f, " unsized");
|
2020-04-15 13:36:40 -05:00
|
|
|
if (basic_prep)
|
|
|
|
fprintf(f, " basic_prep");
|
|
|
|
if (lookahead)
|
|
|
|
fprintf(f, " lookahead");
|
2013-01-05 04:13:26 -06:00
|
|
|
if (port_id > 0)
|
|
|
|
fprintf(f, " port=%d", port_id);
|
|
|
|
if (range_valid || range_left != -1 || range_right != 0)
|
2014-07-28 07:25:03 -05:00
|
|
|
fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
|
2013-01-05 04:13:26 -06:00
|
|
|
if (integer != 0)
|
|
|
|
fprintf(f, " int=%u", (int)integer);
|
2014-06-14 05:00:47 -05:00
|
|
|
if (realvalue != 0)
|
|
|
|
fprintf(f, " real=%e", realvalue);
|
2014-08-06 08:43:46 -05:00
|
|
|
if (!multirange_dimensions.empty()) {
|
|
|
|
fprintf(f, " multirange=[");
|
|
|
|
for (int v : multirange_dimensions)
|
|
|
|
fprintf(f, " %d", v);
|
|
|
|
fprintf(f, " ]");
|
|
|
|
}
|
2020-09-15 12:49:52 -05:00
|
|
|
if (!multirange_swapped.empty()) {
|
|
|
|
fprintf(f, " multirange_swapped=[");
|
2022-01-18 01:17:08 -06:00
|
|
|
for (bool v : multirange_swapped)
|
2020-09-15 12:49:52 -05:00
|
|
|
fprintf(f, " %d", v);
|
|
|
|
fprintf(f, " ]");
|
|
|
|
}
|
2018-03-09 06:47:11 -06:00
|
|
|
if (is_enum) {
|
|
|
|
fprintf(f, " type=enum");
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
fprintf(f, "\n");
|
|
|
|
|
2013-11-18 12:54:36 -06:00
|
|
|
for (auto &it : attributes) {
|
|
|
|
fprintf(f, "%s ATTR %s:\n", indent.c_str(), it.first.c_str());
|
|
|
|
it.second->dumpAst(f, indent + " ");
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
for (size_t i = 0; i < children.size(); i++)
|
2013-08-19 12:49:14 -05:00
|
|
|
children[i]->dumpAst(f, indent + " ");
|
2016-08-21 06:18:09 -05:00
|
|
|
|
|
|
|
fflush(f);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
// helper function for AstNode::dumpVlog()
|
|
|
|
static std::string id2vl(std::string txt)
|
|
|
|
{
|
|
|
|
if (txt.size() > 1 && txt[0] == '\\')
|
|
|
|
txt = txt.substr(1);
|
|
|
|
for (size_t i = 0; i < txt.size(); i++) {
|
|
|
|
if ('A' <= txt[i] && txt[i] <= 'Z') continue;
|
|
|
|
if ('a' <= txt[i] && txt[i] <= 'z') continue;
|
|
|
|
if ('0' <= txt[i] && txt[i] <= '9') continue;
|
|
|
|
if (txt[i] == '_') continue;
|
|
|
|
txt = "\\" + txt + " ";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return txt;
|
|
|
|
}
|
|
|
|
|
2015-08-14 15:23:01 -05:00
|
|
|
// dump AST node as Verilog pseudo-code
|
2017-09-29 23:37:38 -05:00
|
|
|
void AstNode::dumpVlog(FILE *f, std::string indent) const
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
|
|
|
bool first = true;
|
|
|
|
std::string txt;
|
|
|
|
std::vector<AstNode*> rem_children1, rem_children2;
|
|
|
|
|
|
|
|
if (f == NULL) {
|
|
|
|
for (auto f : log_files)
|
|
|
|
dumpVlog(f, indent);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-11-18 12:54:36 -06:00
|
|
|
for (auto &it : attributes) {
|
2014-08-01 17:45:25 -05:00
|
|
|
fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first.str()).c_str());
|
2013-11-18 12:54:36 -06:00
|
|
|
it.second->dumpVlog(f, "");
|
|
|
|
fprintf(f, " *)%s", indent.empty() ? "" : "\n");
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
switch (type)
|
|
|
|
{
|
|
|
|
case AST_MODULE:
|
|
|
|
fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
|
|
|
|
for (auto child : children)
|
|
|
|
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
|
|
|
|
fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, ");\n");
|
|
|
|
|
|
|
|
for (auto child : children)
|
2013-07-04 07:12:33 -05:00
|
|
|
if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_DEFPARAM)
|
2013-01-05 04:13:26 -06:00
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
else
|
|
|
|
rem_children1.push_back(child);
|
|
|
|
|
|
|
|
for (auto child : rem_children1)
|
|
|
|
if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
else
|
|
|
|
rem_children2.push_back(child);
|
|
|
|
rem_children1.clear();
|
|
|
|
|
|
|
|
for (auto child : rem_children2)
|
|
|
|
if (child->type == AST_TASK || child->type == AST_FUNCTION)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
else
|
|
|
|
rem_children1.push_back(child);
|
|
|
|
rem_children2.clear();
|
|
|
|
|
|
|
|
for (auto child : rem_children1)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
rem_children1.clear();
|
|
|
|
|
|
|
|
fprintf(f, "%s" "endmodule\n", indent.c_str());
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_WIRE:
|
|
|
|
if (is_input && is_output)
|
|
|
|
fprintf(f, "%s" "inout", indent.c_str());
|
|
|
|
else if (is_input)
|
|
|
|
fprintf(f, "%s" "input", indent.c_str());
|
|
|
|
else if (is_output)
|
|
|
|
fprintf(f, "%s" "output", indent.c_str());
|
|
|
|
else if (!is_reg)
|
|
|
|
fprintf(f, "%s" "wire", indent.c_str());
|
|
|
|
if (is_reg)
|
|
|
|
fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
|
|
|
|
if (is_signed)
|
|
|
|
fprintf(f, " signed");
|
|
|
|
for (auto child : children) {
|
|
|
|
fprintf(f, " ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
}
|
|
|
|
fprintf(f, " %s", id2vl(str).c_str());
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_MEMORY:
|
|
|
|
fprintf(f, "%s" "memory", indent.c_str());
|
|
|
|
if (is_signed)
|
|
|
|
fprintf(f, " signed");
|
|
|
|
for (auto child : children) {
|
|
|
|
fprintf(f, " ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
if (first)
|
|
|
|
fprintf(f, " %s", id2vl(str).c_str());
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_RANGE:
|
2019-03-21 16:20:16 -05:00
|
|
|
if (range_valid) {
|
|
|
|
if (range_swapped)
|
|
|
|
fprintf(f, "[%d:%d]", range_right, range_left);
|
|
|
|
else
|
|
|
|
fprintf(f, "[%d:%d]", range_left, range_right);
|
|
|
|
} else {
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : children) {
|
|
|
|
fprintf(f, "%c", first ? '[' : ':');
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, "]");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_ALWAYS:
|
2016-08-21 06:18:09 -05:00
|
|
|
fprintf(f, "%s" "always @", indent.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
|
|
|
|
continue;
|
2016-08-21 06:18:09 -05:00
|
|
|
fprintf(f, first ? "(" : ", ");
|
2013-01-05 04:13:26 -06:00
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
2016-08-21 06:18:09 -05:00
|
|
|
fprintf(f, first ? "*\n" : ")\n");
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2013-03-31 04:19:11 -05:00
|
|
|
case AST_INITIAL:
|
|
|
|
fprintf(f, "%s" "initial\n", indent.c_str());
|
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
case AST_POSEDGE:
|
|
|
|
case AST_NEGEDGE:
|
|
|
|
case AST_EDGE:
|
|
|
|
if (type == AST_POSEDGE)
|
|
|
|
fprintf(f, "posedge ");
|
|
|
|
if (type == AST_NEGEDGE)
|
|
|
|
fprintf(f, "negedge ");
|
|
|
|
for (auto child : children)
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_IDENTIFIER:
|
2023-02-28 11:45:55 -06:00
|
|
|
{
|
|
|
|
AST::AstNode *member_node = AST::get_struct_member(this);
|
|
|
|
if (member_node)
|
|
|
|
fprintf(f, "%s[%d:%d]", id2vl(str).c_str(), member_node->range_left, member_node->range_right);
|
|
|
|
else
|
|
|
|
fprintf(f, "%s", id2vl(str).c_str());
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : children)
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_CONSTANT:
|
|
|
|
if (!str.empty())
|
|
|
|
fprintf(f, "\"%s\"", str.c_str());
|
|
|
|
else if (bits.size() == 32)
|
|
|
|
fprintf(f, "%d", RTLIL::Const(bits).as_int());
|
|
|
|
else
|
2014-10-11 04:42:08 -05:00
|
|
|
fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
|
|
|
|
2014-06-13 04:29:23 -05:00
|
|
|
case AST_REALVALUE:
|
|
|
|
fprintf(f, "%e", realvalue);
|
|
|
|
break;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
case AST_BLOCK:
|
|
|
|
if (children.size() == 1) {
|
|
|
|
children[0]->dumpVlog(f, indent);
|
|
|
|
} else {
|
|
|
|
fprintf(f, "%s" "begin\n", indent.c_str());
|
|
|
|
for (auto child : children)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
fprintf(f, "%s" "end\n", indent.c_str());
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_CASE:
|
2021-01-27 17:31:50 -06:00
|
|
|
if (children.size() > 1 && children[1]->type == AST_CONDX)
|
2016-04-21 08:31:54 -05:00
|
|
|
fprintf(f, "%s" "casex (", indent.c_str());
|
2021-01-27 17:31:50 -06:00
|
|
|
else if (children.size() > 1 && children[1]->type == AST_CONDZ)
|
2016-04-21 08:31:54 -05:00
|
|
|
fprintf(f, "%s" "casez (", indent.c_str());
|
|
|
|
else
|
|
|
|
fprintf(f, "%s" "case (", indent.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")\n");
|
|
|
|
for (size_t i = 1; i < children.size(); i++) {
|
|
|
|
AstNode *child = children[i];
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
}
|
|
|
|
fprintf(f, "%s" "endcase\n", indent.c_str());
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_COND:
|
2016-04-21 08:31:54 -05:00
|
|
|
case AST_CONDX:
|
|
|
|
case AST_CONDZ:
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type == AST_BLOCK) {
|
|
|
|
fprintf(f, ":\n");
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
first = true;
|
|
|
|
} else {
|
|
|
|
fprintf(f, "%s", first ? indent.c_str() : ", ");
|
|
|
|
if (child->type == AST_DEFAULT)
|
|
|
|
fprintf(f, "default");
|
|
|
|
else
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2016-08-21 06:18:09 -05:00
|
|
|
case AST_ASSIGN:
|
|
|
|
fprintf(f, "%sassign ", indent.c_str());
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, " = ");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
case AST_ASSIGN_EQ:
|
|
|
|
case AST_ASSIGN_LE:
|
|
|
|
fprintf(f, "%s", indent.c_str());
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, " %s ", type == AST_ASSIGN_EQ ? "=" : "<=");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_CONCAT:
|
|
|
|
fprintf(f, "{");
|
2019-03-21 14:52:29 -05:00
|
|
|
for (int i = GetSize(children)-1; i >= 0; i--) {
|
|
|
|
auto child = children[i];
|
2013-01-05 04:13:26 -06:00
|
|
|
if (!first)
|
|
|
|
fprintf(f, ", ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, "}");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_REPLICATE:
|
|
|
|
fprintf(f, "{");
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, "{");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, "}}");
|
|
|
|
break;
|
2015-07-02 04:14:30 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (0) { case AST_BIT_NOT: txt = "~"; }
|
|
|
|
if (0) { case AST_REDUCE_AND: txt = "&"; }
|
|
|
|
if (0) { case AST_REDUCE_OR: txt = "|"; }
|
|
|
|
if (0) { case AST_REDUCE_XOR: txt = "^"; }
|
|
|
|
if (0) { case AST_REDUCE_XNOR: txt = "~^"; }
|
|
|
|
if (0) { case AST_REDUCE_BOOL: txt = "|"; }
|
|
|
|
if (0) { case AST_POS: txt = "+"; }
|
|
|
|
if (0) { case AST_NEG: txt = "-"; }
|
|
|
|
if (0) { case AST_LOGIC_NOT: txt = "!"; }
|
2020-04-29 07:28:04 -05:00
|
|
|
if (0) { case AST_SELFSZ: txt = "@selfsz@"; }
|
2013-01-05 04:13:26 -06:00
|
|
|
fprintf(f, "%s(", txt.c_str());
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")");
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (0) { case AST_BIT_AND: txt = "&"; }
|
|
|
|
if (0) { case AST_BIT_OR: txt = "|"; }
|
|
|
|
if (0) { case AST_BIT_XOR: txt = "^"; }
|
|
|
|
if (0) { case AST_BIT_XNOR: txt = "~^"; }
|
|
|
|
if (0) { case AST_SHIFT_LEFT: txt = "<<"; }
|
|
|
|
if (0) { case AST_SHIFT_RIGHT: txt = ">>"; }
|
|
|
|
if (0) { case AST_SHIFT_SLEFT: txt = "<<<"; }
|
|
|
|
if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; }
|
2020-04-27 10:04:47 -05:00
|
|
|
if (0) { case AST_SHIFTX: txt = "@shiftx@"; }
|
|
|
|
if (0) { case AST_SHIFT: txt = "@shift@"; }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (0) { case AST_LT: txt = "<"; }
|
|
|
|
if (0) { case AST_LE: txt = "<="; }
|
|
|
|
if (0) { case AST_EQ: txt = "=="; }
|
|
|
|
if (0) { case AST_NE: txt = "!="; }
|
2013-12-27 06:50:08 -06:00
|
|
|
if (0) { case AST_EQX: txt = "==="; }
|
|
|
|
if (0) { case AST_NEX: txt = "!=="; }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (0) { case AST_GE: txt = ">="; }
|
|
|
|
if (0) { case AST_GT: txt = ">"; }
|
|
|
|
if (0) { case AST_ADD: txt = "+"; }
|
|
|
|
if (0) { case AST_SUB: txt = "-"; }
|
|
|
|
if (0) { case AST_MUL: txt = "*"; }
|
|
|
|
if (0) { case AST_DIV: txt = "/"; }
|
|
|
|
if (0) { case AST_MOD: txt = "%"; }
|
|
|
|
if (0) { case AST_POW: txt = "**"; }
|
|
|
|
if (0) { case AST_LOGIC_AND: txt = "&&"; }
|
|
|
|
if (0) { case AST_LOGIC_OR: txt = "||"; }
|
|
|
|
fprintf(f, "(");
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")%s(", txt.c_str());
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_TERNARY:
|
|
|
|
fprintf(f, "(");
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ") ? (");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ") : (");
|
|
|
|
children[2]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")");
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
std::string type_name = type2str(type);
|
|
|
|
fprintf(f, "%s" "/** %s **/%s", indent.c_str(), type_name.c_str(), indent.empty() ? "" : "\n");
|
|
|
|
// dumpAst(f, indent, NULL);
|
|
|
|
}
|
2016-08-21 06:18:09 -05:00
|
|
|
|
|
|
|
fflush(f);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
// check if two AST nodes are identical
|
|
|
|
bool AstNode::operator==(const AstNode &other) const
|
|
|
|
{
|
|
|
|
if (type != other.type)
|
|
|
|
return false;
|
|
|
|
if (children.size() != other.children.size())
|
|
|
|
return false;
|
|
|
|
if (str != other.str)
|
|
|
|
return false;
|
|
|
|
if (bits != other.bits)
|
|
|
|
return false;
|
|
|
|
if (is_input != other.is_input)
|
|
|
|
return false;
|
|
|
|
if (is_output != other.is_output)
|
|
|
|
return false;
|
2018-03-09 02:35:33 -06:00
|
|
|
if (is_logic != other.is_logic)
|
|
|
|
return false;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (is_reg != other.is_reg)
|
|
|
|
return false;
|
|
|
|
if (is_signed != other.is_signed)
|
|
|
|
return false;
|
2013-12-05 06:26:17 -06:00
|
|
|
if (is_string != other.is_string)
|
|
|
|
return false;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (range_valid != other.range_valid)
|
|
|
|
return false;
|
2014-07-28 07:25:03 -05:00
|
|
|
if (range_swapped != other.range_swapped)
|
|
|
|
return false;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (port_id != other.port_id)
|
|
|
|
return false;
|
|
|
|
if (range_left != other.range_left)
|
|
|
|
return false;
|
|
|
|
if (range_right != other.range_right)
|
|
|
|
return false;
|
|
|
|
if (integer != other.integer)
|
|
|
|
return false;
|
|
|
|
for (size_t i = 0; i < children.size(); i++)
|
|
|
|
if (*children[i] != *other.children[i])
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// check if two AST nodes are not identical
|
|
|
|
bool AstNode::operator!=(const AstNode &other) const
|
|
|
|
{
|
|
|
|
return !(*this == other);
|
|
|
|
}
|
|
|
|
|
|
|
|
// check if this AST contains the given node
|
|
|
|
bool AstNode::contains(const AstNode *other) const
|
|
|
|
{
|
|
|
|
if (this == other)
|
|
|
|
return true;
|
|
|
|
for (auto child : children)
|
|
|
|
if (child->contains(other))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create an AST node for a constant (using a 32 bit int as value)
|
|
|
|
AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
|
|
|
|
{
|
|
|
|
AstNode *node = new AstNode(AST_CONSTANT);
|
|
|
|
node->integer = v;
|
|
|
|
node->is_signed = is_signed;
|
|
|
|
for (int i = 0; i < width; i++) {
|
2019-08-07 13:12:38 -05:00
|
|
|
node->bits.push_back((v & 1) ? State::S1 : State::S0);
|
2013-01-05 04:13:26 -06:00
|
|
|
v = v >> 1;
|
|
|
|
}
|
|
|
|
node->range_valid = true;
|
|
|
|
node->range_left = width-1;
|
|
|
|
node->range_right = 0;
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create an AST node for a constant (using a bit vector as value)
|
2019-05-27 04:42:10 -05:00
|
|
|
AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
|
|
|
AstNode *node = new AstNode(AST_CONSTANT);
|
|
|
|
node->is_signed = is_signed;
|
|
|
|
node->bits = v;
|
|
|
|
for (size_t i = 0; i < 32; i++) {
|
|
|
|
if (i < node->bits.size())
|
2019-08-07 13:12:38 -05:00
|
|
|
node->integer |= (node->bits[i] == State::S1) << i;
|
2015-09-24 04:21:20 -05:00
|
|
|
else if (is_signed && !node->bits.empty())
|
2019-08-07 13:12:38 -05:00
|
|
|
node->integer |= (node->bits.back() == State::S1) << i;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
node->range_valid = true;
|
2013-07-07 08:40:26 -05:00
|
|
|
node->range_left = node->bits.size()-1;
|
2013-01-05 04:13:26 -06:00
|
|
|
node->range_right = 0;
|
2019-05-27 04:42:10 -05:00
|
|
|
node->is_unsized = is_unsized;
|
2013-01-05 04:13:26 -06:00
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
2019-05-27 04:42:10 -05:00
|
|
|
AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
|
|
|
|
{
|
|
|
|
return mkconst_bits(v, is_signed, false);
|
|
|
|
}
|
|
|
|
|
2013-12-05 06:26:17 -06:00
|
|
|
// create an AST node for a constant (using a string in bit vector form as value)
|
|
|
|
AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
|
|
|
|
{
|
|
|
|
AstNode *node = mkconst_str(RTLIL::Const(v).decode_string());
|
2014-10-25 11:23:53 -05:00
|
|
|
while (GetSize(node->bits) < GetSize(v))
|
|
|
|
node->bits.push_back(RTLIL::State::S0);
|
2013-12-05 06:26:17 -06:00
|
|
|
log_assert(node->bits == v);
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
2013-12-05 05:53:49 -06:00
|
|
|
// create an AST node for a constant (using a string as value)
|
|
|
|
AstNode *AstNode::mkconst_str(const std::string &str)
|
|
|
|
{
|
|
|
|
std::vector<RTLIL::State> data;
|
|
|
|
data.reserve(str.size() * 8);
|
|
|
|
for (size_t i = 0; i < str.size(); i++) {
|
|
|
|
unsigned char ch = str[str.size() - i - 1];
|
|
|
|
for (int j = 0; j < 8; j++) {
|
2019-08-07 13:12:38 -05:00
|
|
|
data.push_back((ch & 1) ? State::S1 : State::S0);
|
2013-12-05 05:53:49 -06:00
|
|
|
ch = ch >> 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
AstNode *node = AstNode::mkconst_bits(data, false);
|
2013-12-05 06:26:17 -06:00
|
|
|
node->is_string = true;
|
2013-12-05 05:53:49 -06:00
|
|
|
node->str = str;
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
2017-09-29 23:37:38 -05:00
|
|
|
bool AstNode::bits_only_01() const
|
2014-08-17 17:02:30 -05:00
|
|
|
{
|
|
|
|
for (auto bit : bits)
|
2019-08-07 13:12:38 -05:00
|
|
|
if (bit != State::S0 && bit != State::S1)
|
2014-08-17 17:02:30 -05:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-05-27 04:42:10 -05:00
|
|
|
RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
|
|
|
|
{
|
|
|
|
RTLIL::State extbit = bits.back();
|
|
|
|
while (width > int(bits.size()))
|
|
|
|
bits.push_back(extbit);
|
|
|
|
return RTLIL::Const(bits);
|
|
|
|
}
|
|
|
|
|
2013-11-02 07:00:17 -05:00
|
|
|
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
|
|
|
|
{
|
|
|
|
std::vector<RTLIL::State> bits = this->bits;
|
|
|
|
if (width >= 0 && width < int(bits.size()))
|
|
|
|
bits.resize(width);
|
|
|
|
if (width >= 0 && width > int(bits.size())) {
|
|
|
|
RTLIL::State extbit = RTLIL::State::S0;
|
2023-04-20 05:12:50 -05:00
|
|
|
if ((is_signed || is_unsized) && !bits.empty())
|
2013-11-02 07:00:17 -05:00
|
|
|
extbit = bits.back();
|
|
|
|
while (width > int(bits.size()))
|
|
|
|
bits.push_back(extbit);
|
|
|
|
}
|
|
|
|
return RTLIL::Const(bits);
|
|
|
|
}
|
|
|
|
|
|
|
|
RTLIL::Const AstNode::bitsAsConst(int width)
|
|
|
|
{
|
|
|
|
return bitsAsConst(width, is_signed);
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
RTLIL::Const AstNode::asAttrConst() const
|
2013-12-04 07:14:05 -06:00
|
|
|
{
|
|
|
|
log_assert(type == AST_CONSTANT);
|
|
|
|
|
|
|
|
RTLIL::Const val;
|
|
|
|
val.bits = bits;
|
|
|
|
|
2013-12-05 06:26:17 -06:00
|
|
|
if (is_string) {
|
2013-12-04 07:14:05 -06:00
|
|
|
val.flags |= RTLIL::CONST_FLAG_STRING;
|
|
|
|
log_assert(val.decode_string() == str);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
RTLIL::Const AstNode::asParaConst() const
|
2013-12-04 07:14:05 -06:00
|
|
|
{
|
2021-10-19 19:46:26 -05:00
|
|
|
if (type == AST_REALVALUE)
|
|
|
|
{
|
|
|
|
AstNode *strnode = AstNode::mkconst_str(stringf("%f", realvalue));
|
|
|
|
RTLIL::Const val = strnode->asAttrConst();
|
|
|
|
val.flags |= RTLIL::CONST_FLAG_REAL;
|
|
|
|
delete strnode;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2013-12-04 07:14:05 -06:00
|
|
|
RTLIL::Const val = asAttrConst();
|
|
|
|
if (is_signed)
|
|
|
|
val.flags |= RTLIL::CONST_FLAG_SIGNED;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2017-09-29 23:37:38 -05:00
|
|
|
bool AstNode::asBool() const
|
2013-12-04 14:06:54 -06:00
|
|
|
{
|
|
|
|
log_assert(type == AST_CONSTANT);
|
|
|
|
for (auto &bit : bits)
|
|
|
|
if (bit == RTLIL::State::S1)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-09-29 23:37:38 -05:00
|
|
|
int AstNode::isConst() const
|
2014-06-14 01:51:22 -05:00
|
|
|
{
|
|
|
|
if (type == AST_CONSTANT)
|
|
|
|
return 1;
|
|
|
|
if (type == AST_REALVALUE)
|
|
|
|
return 2;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-21 10:11:51 -05:00
|
|
|
uint64_t AstNode::asInt(bool is_signed)
|
|
|
|
{
|
|
|
|
if (type == AST_CONSTANT)
|
|
|
|
{
|
|
|
|
RTLIL::Const v = bitsAsConst(64, is_signed);
|
|
|
|
uint64_t ret = 0;
|
|
|
|
|
|
|
|
for (int i = 0; i < 64; i++)
|
|
|
|
if (v.bits.at(i) == RTLIL::State::S1)
|
|
|
|
ret |= uint64_t(1) << i;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (type == AST_REALVALUE)
|
2016-02-13 10:31:24 -06:00
|
|
|
return uint64_t(realvalue);
|
2014-08-21 10:11:51 -05:00
|
|
|
|
|
|
|
log_abort();
|
|
|
|
}
|
|
|
|
|
2014-06-14 01:51:22 -05:00
|
|
|
double AstNode::asReal(bool is_signed)
|
|
|
|
{
|
2014-08-21 10:11:51 -05:00
|
|
|
if (type == AST_CONSTANT)
|
|
|
|
{
|
2014-06-15 01:38:31 -05:00
|
|
|
RTLIL::Const val(bits);
|
2014-06-14 01:51:22 -05:00
|
|
|
|
2015-09-25 05:38:01 -05:00
|
|
|
bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1;
|
2014-06-15 01:38:31 -05:00
|
|
|
if (is_negative)
|
|
|
|
val = const_neg(val, val, false, false, val.bits.size());
|
2014-06-14 01:51:22 -05:00
|
|
|
|
2014-06-15 01:38:31 -05:00
|
|
|
double v = 0;
|
|
|
|
for (size_t i = 0; i < val.bits.size(); i++)
|
2014-06-16 08:05:37 -05:00
|
|
|
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
|
|
|
|
// the net or the variable shall be treated as zero upon conversion.
|
2014-06-15 01:38:31 -05:00
|
|
|
if (val.bits.at(i) == RTLIL::State::S1)
|
|
|
|
v += exp2(i);
|
|
|
|
if (is_negative)
|
|
|
|
v *= -1;
|
|
|
|
|
|
|
|
return v;
|
2014-06-14 01:51:22 -05:00
|
|
|
}
|
2014-06-14 05:00:47 -05:00
|
|
|
|
2014-06-14 01:51:22 -05:00
|
|
|
if (type == AST_REALVALUE)
|
|
|
|
return realvalue;
|
2014-06-14 05:00:47 -05:00
|
|
|
|
|
|
|
log_abort();
|
2014-06-14 01:51:22 -05:00
|
|
|
}
|
|
|
|
|
2014-06-14 13:38:05 -05:00
|
|
|
RTLIL::Const AstNode::realAsConst(int width)
|
|
|
|
{
|
|
|
|
double v = round(realvalue);
|
|
|
|
RTLIL::Const result;
|
2014-08-22 09:09:13 -05:00
|
|
|
#ifdef EMSCRIPTEN
|
|
|
|
if (!isfinite(v)) {
|
|
|
|
#else
|
2014-07-31 06:19:47 -05:00
|
|
|
if (!std::isfinite(v)) {
|
2014-08-22 09:09:13 -05:00
|
|
|
#endif
|
2014-06-14 13:38:05 -05:00
|
|
|
result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
|
|
|
|
} else {
|
|
|
|
bool is_negative = v < 0;
|
|
|
|
if (is_negative)
|
|
|
|
v *= -1;
|
|
|
|
for (int i = 0; i < width; i++, v /= 2)
|
2014-06-15 02:27:09 -05:00
|
|
|
result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
|
2014-06-14 13:38:05 -05:00
|
|
|
if (is_negative)
|
|
|
|
result = const_neg(result, result, false, false, result.bits.size());
|
|
|
|
}
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2021-02-23 12:22:53 -06:00
|
|
|
std::string AstNode::loc_string() const
|
|
|
|
{
|
|
|
|
return stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
|
|
|
}
|
|
|
|
|
|
|
|
void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
|
|
|
|
{
|
|
|
|
obj->attributes[ID::src] = ast->loc_string();
|
|
|
|
}
|
|
|
|
|
2021-03-02 09:43:53 -06:00
|
|
|
static bool param_has_no_default(const AstNode *param) {
|
|
|
|
const auto &children = param->children;
|
|
|
|
log_assert(param->type == AST_PARAMETER);
|
|
|
|
log_assert(children.size() <= 2);
|
|
|
|
return children.empty() ||
|
|
|
|
(children.size() == 1 && children[0]->type == AST_RANGE);
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:43:30 -05:00
|
|
|
static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2020-04-22 07:51:20 -05:00
|
|
|
log_assert(current_scope.empty());
|
2018-10-11 16:33:31 -05:00
|
|
|
log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
|
2014-02-13 06:59:13 -06:00
|
|
|
|
|
|
|
if (defer)
|
|
|
|
log("Storing AST representation for module `%s'.\n", ast->str.c_str());
|
2020-02-18 17:32:56 -06:00
|
|
|
else if (!quiet) {
|
2014-02-13 06:59:13 -06:00
|
|
|
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
|
2020-02-18 17:32:56 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2020-04-20 08:41:55 -05:00
|
|
|
AstModule *module = new AstModule;
|
|
|
|
current_module = module;
|
|
|
|
|
|
|
|
module->ast = NULL;
|
|
|
|
module->name = ast->str;
|
|
|
|
set_src_attr(module, ast);
|
|
|
|
module->set_bool_attribute(ID::cells_not_processed);
|
2013-11-02 07:00:17 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
current_ast_mod = ast;
|
2018-10-20 04:58:25 -05:00
|
|
|
AstNode *ast_before_simplify;
|
|
|
|
if (original_ast != NULL)
|
|
|
|
ast_before_simplify = original_ast;
|
|
|
|
else
|
|
|
|
ast_before_simplify = ast->clone();
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-08-19 12:49:14 -05:00
|
|
|
if (flag_dump_ast1) {
|
2019-03-21 14:52:29 -05:00
|
|
|
log("Dumping AST before simplification:\n");
|
2013-08-19 12:49:14 -05:00
|
|
|
ast->dumpAst(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
2019-03-21 14:52:29 -05:00
|
|
|
if (flag_dump_vlog1) {
|
|
|
|
log("Dumping Verilog AST before simplification:\n");
|
|
|
|
ast->dumpVlog(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
2013-08-19 12:49:14 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (!defer)
|
|
|
|
{
|
2021-03-02 09:43:53 -06:00
|
|
|
for (const AstNode *node : ast->children)
|
|
|
|
if (node->type == AST_PARAMETER && param_has_no_default(node))
|
2023-04-04 04:53:50 -05:00
|
|
|
node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str());
|
2021-03-02 09:43:53 -06:00
|
|
|
|
2019-04-21 04:40:09 -05:00
|
|
|
bool blackbox_module = flag_lib;
|
|
|
|
|
|
|
|
if (!blackbox_module && !flag_noblackbox) {
|
|
|
|
blackbox_module = true;
|
|
|
|
for (auto child : ast->children) {
|
|
|
|
if (child->type == AST_WIRE && (child->is_input || child->is_output))
|
|
|
|
continue;
|
|
|
|
if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
|
|
|
|
continue;
|
2019-04-22 02:59:49 -05:00
|
|
|
if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
|
2019-04-23 08:46:40 -05:00
|
|
|
(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule"))
|
2019-04-22 02:59:49 -05:00
|
|
|
continue;
|
2019-04-21 04:40:09 -05:00
|
|
|
blackbox_module = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
// simplify this module or interface using the current design as context
|
|
|
|
// for lookup up ports and wires within cells
|
|
|
|
set_simplify_design_context(design);
|
2023-04-04 15:53:01 -05:00
|
|
|
while (ast->simplify(!flag_noopt, false, 0, -1, false, false)) { }
|
2021-10-19 19:46:26 -05:00
|
|
|
set_simplify_design_context(nullptr);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (flag_dump_ast2) {
|
2019-03-21 14:52:29 -05:00
|
|
|
log("Dumping AST after simplification:\n");
|
2014-02-13 06:59:13 -06:00
|
|
|
ast->dumpAst(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2019-03-21 14:52:29 -05:00
|
|
|
if (flag_dump_vlog2) {
|
|
|
|
log("Dumping Verilog AST after simplification:\n");
|
2014-02-13 06:59:13 -06:00
|
|
|
ast->dumpVlog(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (flag_nowb && ast->attributes.count(ID::whitebox)) {
|
|
|
|
delete ast->attributes.at(ID::whitebox);
|
|
|
|
ast->attributes.erase(ID::whitebox);
|
2019-04-20 15:24:50 -05:00
|
|
|
}
|
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (ast->attributes.count(ID::lib_whitebox)) {
|
2019-04-20 15:24:50 -05:00
|
|
|
if (!flag_lib || flag_nowb) {
|
2020-04-02 11:51:32 -05:00
|
|
|
delete ast->attributes.at(ID::lib_whitebox);
|
|
|
|
ast->attributes.erase(ID::lib_whitebox);
|
2019-04-20 15:24:50 -05:00
|
|
|
} else {
|
2020-04-02 11:51:32 -05:00
|
|
|
if (ast->attributes.count(ID::whitebox)) {
|
|
|
|
delete ast->attributes.at(ID::whitebox);
|
|
|
|
ast->attributes.erase(ID::whitebox);
|
2019-04-20 15:24:50 -05:00
|
|
|
}
|
2020-04-02 11:51:32 -05:00
|
|
|
AstNode *n = ast->attributes.at(ID::lib_whitebox);
|
|
|
|
ast->attributes[ID::whitebox] = n;
|
|
|
|
ast->attributes.erase(ID::lib_whitebox);
|
2019-04-20 15:24:50 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (!blackbox_module && ast->attributes.count(ID::blackbox)) {
|
|
|
|
AstNode *n = ast->attributes.at(ID::blackbox);
|
2019-04-20 15:24:50 -05:00
|
|
|
if (n->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
ast->input_error("Got blackbox attribute with non-constant value!\n");
|
2019-04-20 15:24:50 -05:00
|
|
|
blackbox_module = n->asBool();
|
|
|
|
}
|
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (blackbox_module && ast->attributes.count(ID::whitebox)) {
|
|
|
|
AstNode *n = ast->attributes.at(ID::whitebox);
|
2019-04-18 10:42:12 -05:00
|
|
|
if (n->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
ast->input_error("Got whitebox attribute with non-constant value!\n");
|
2019-04-20 15:24:50 -05:00
|
|
|
blackbox_module = !n->asBool();
|
2019-04-18 10:42:12 -05:00
|
|
|
}
|
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (ast->attributes.count(ID::noblackbox)) {
|
2019-04-21 04:40:09 -05:00
|
|
|
if (blackbox_module) {
|
2020-04-02 11:51:32 -05:00
|
|
|
AstNode *n = ast->attributes.at(ID::noblackbox);
|
2019-04-21 04:40:09 -05:00
|
|
|
if (n->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
ast->input_error("Got noblackbox attribute with non-constant value!\n");
|
2019-04-21 04:40:09 -05:00
|
|
|
blackbox_module = !n->asBool();
|
|
|
|
}
|
2020-04-02 11:51:32 -05:00
|
|
|
delete ast->attributes.at(ID::noblackbox);
|
|
|
|
ast->attributes.erase(ID::noblackbox);
|
2019-04-21 04:40:09 -05:00
|
|
|
}
|
|
|
|
|
2019-04-20 15:24:50 -05:00
|
|
|
if (blackbox_module)
|
|
|
|
{
|
2020-04-02 11:51:32 -05:00
|
|
|
if (ast->attributes.count(ID::whitebox)) {
|
|
|
|
delete ast->attributes.at(ID::whitebox);
|
|
|
|
ast->attributes.erase(ID::whitebox);
|
2019-04-20 15:24:50 -05:00
|
|
|
}
|
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (ast->attributes.count(ID::lib_whitebox)) {
|
|
|
|
delete ast->attributes.at(ID::lib_whitebox);
|
|
|
|
ast->attributes.erase(ID::lib_whitebox);
|
2019-04-20 15:24:50 -05:00
|
|
|
}
|
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
std::vector<AstNode*> new_children;
|
|
|
|
for (auto child : ast->children) {
|
2016-10-22 04:05:49 -05:00
|
|
|
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
|
2014-02-13 06:59:13 -06:00
|
|
|
new_children.push_back(child);
|
2016-10-22 04:05:49 -05:00
|
|
|
} else if (child->type == AST_PARAMETER) {
|
|
|
|
new_children.push_back(child);
|
2019-04-22 02:59:49 -05:00
|
|
|
} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
|
2019-04-23 08:46:40 -05:00
|
|
|
(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) {
|
2019-04-22 02:59:49 -05:00
|
|
|
new_children.push_back(child);
|
2016-10-22 04:05:49 -05:00
|
|
|
} else {
|
2014-02-13 06:59:13 -06:00
|
|
|
delete child;
|
2016-10-22 04:05:49 -05:00
|
|
|
}
|
2014-02-13 06:59:13 -06:00
|
|
|
}
|
2019-04-20 15:24:50 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ast->children.swap(new_children);
|
2019-04-20 15:24:50 -05:00
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (ast->attributes.count(ID::blackbox) == 0) {
|
|
|
|
ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false);
|
2019-04-18 10:42:12 -05:00
|
|
|
}
|
2013-03-28 03:20:10 -05:00
|
|
|
}
|
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ignoreThisSignalsInInitial = RTLIL::SigSpec();
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2019-08-29 11:02:10 -05:00
|
|
|
for (auto &attr : ast->attributes) {
|
|
|
|
if (attr.second->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
2020-04-20 08:41:55 -05:00
|
|
|
module->attributes[attr.first] = attr.second->asAttrConst();
|
2019-08-29 11:02:10 -05:00
|
|
|
}
|
2014-02-13 06:59:13 -06:00
|
|
|
for (size_t i = 0; i < ast->children.size(); i++) {
|
|
|
|
AstNode *node = ast->children[i];
|
|
|
|
if (node->type == AST_WIRE || node->type == AST_MEMORY)
|
|
|
|
node->genRTLIL();
|
|
|
|
}
|
|
|
|
for (size_t i = 0; i < ast->children.size(); i++) {
|
|
|
|
AstNode *node = ast->children[i];
|
|
|
|
if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
|
|
|
|
node->genRTLIL();
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ignoreThisSignalsInInitial.sort_and_unify();
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
for (size_t i = 0; i < ast->children.size(); i++) {
|
|
|
|
AstNode *node = ast->children[i];
|
|
|
|
if (node->type == AST_INITIAL)
|
|
|
|
node->genRTLIL();
|
|
|
|
}
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ignoreThisSignalsInInitial = RTLIL::SigSpec();
|
2020-04-22 07:51:20 -05:00
|
|
|
current_scope.clear();
|
2014-02-13 06:59:13 -06:00
|
|
|
}
|
2019-08-29 11:02:10 -05:00
|
|
|
else {
|
|
|
|
for (auto &attr : ast->attributes) {
|
|
|
|
if (attr.second->type != AST_CONSTANT)
|
|
|
|
continue;
|
2020-04-20 08:41:55 -05:00
|
|
|
module->attributes[attr.first] = attr.second->asAttrConst();
|
2019-08-29 11:02:10 -05:00
|
|
|
}
|
2021-10-19 19:46:26 -05:00
|
|
|
for (const AstNode *node : ast->children)
|
|
|
|
if (node->type == AST_PARAMETER)
|
|
|
|
current_module->avail_parameters(node->str);
|
2019-08-28 21:59:09 -05:00
|
|
|
}
|
|
|
|
|
2018-10-11 16:33:31 -05:00
|
|
|
if (ast->type == AST_INTERFACE)
|
2020-04-20 08:41:55 -05:00
|
|
|
module->set_bool_attribute(ID::is_interface);
|
|
|
|
module->ast = ast_before_simplify;
|
|
|
|
module->nolatches = flag_nolatches;
|
|
|
|
module->nomeminit = flag_nomeminit;
|
|
|
|
module->nomem2reg = flag_nomem2reg;
|
|
|
|
module->mem2reg = flag_mem2reg;
|
|
|
|
module->noblackbox = flag_noblackbox;
|
|
|
|
module->lib = flag_lib;
|
|
|
|
module->nowb = flag_nowb;
|
|
|
|
module->noopt = flag_noopt;
|
|
|
|
module->icells = flag_icells;
|
|
|
|
module->pwires = flag_pwires;
|
|
|
|
module->autowire = flag_autowire;
|
|
|
|
module->fixup_ports();
|
2016-07-27 08:40:17 -05:00
|
|
|
|
|
|
|
if (flag_dump_rtlil) {
|
|
|
|
log("Dumping generated RTLIL:\n");
|
2020-04-20 08:41:55 -05:00
|
|
|
log_module(module);
|
2016-07-27 08:40:17 -05:00
|
|
|
log("--- END OF RTLIL DUMP ---\n");
|
|
|
|
}
|
|
|
|
|
2021-03-23 11:49:11 -05:00
|
|
|
design->add(current_module);
|
2021-10-19 19:43:30 -05:00
|
|
|
return current_module;
|
|
|
|
}
|
|
|
|
|
|
|
|
RTLIL::Module *
|
|
|
|
AST_INTERNAL::process_and_replace_module(RTLIL::Design *design,
|
|
|
|
RTLIL::Module *old_module,
|
|
|
|
AstNode *new_ast,
|
|
|
|
AstNode *original_ast)
|
|
|
|
{
|
|
|
|
// The old module will be deleted. Rename and mark for deletion, using
|
|
|
|
// a static counter to make sure we get a unique name.
|
|
|
|
static unsigned counter;
|
|
|
|
std::ostringstream new_name;
|
|
|
|
new_name << old_module->name.str()
|
|
|
|
<< "_before_process_and_replace_module_"
|
|
|
|
<< counter;
|
|
|
|
++counter;
|
|
|
|
|
|
|
|
design->rename(old_module, new_name.str());
|
|
|
|
old_module->set_bool_attribute(ID::to_delete);
|
|
|
|
|
|
|
|
// Check if the module was the top module. If it was, we need to remove
|
|
|
|
// the top attribute and put it on the new module.
|
|
|
|
bool is_top = false;
|
|
|
|
if (old_module->get_bool_attribute(ID::initial_top)) {
|
|
|
|
old_module->attributes.erase(ID::initial_top);
|
|
|
|
is_top = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Generate RTLIL from AST for the new module and add to the design:
|
|
|
|
RTLIL::Module* new_module = process_module(design, new_ast, false, original_ast);
|
|
|
|
|
|
|
|
if (is_top)
|
|
|
|
new_module->set_bool_attribute(ID::top);
|
|
|
|
|
|
|
|
return new_module;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2021-05-27 15:47:02 -05:00
|
|
|
// renames identifiers in tasks and functions within a package
|
|
|
|
static void rename_in_package_stmts(AstNode *pkg)
|
|
|
|
{
|
|
|
|
std::unordered_set<std::string> idents;
|
|
|
|
for (AstNode *item : pkg->children)
|
|
|
|
idents.insert(item->str);
|
|
|
|
std::function<void(AstNode*)> rename =
|
|
|
|
[&rename, &idents, pkg](AstNode *node) {
|
|
|
|
for (AstNode *child : node->children) {
|
|
|
|
if (idents.count(child->str))
|
|
|
|
child->str = pkg->str + "::" + child->str.substr(1);
|
|
|
|
rename(child);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
for (AstNode *item : pkg->children)
|
|
|
|
if (item->type == AST_FUNCTION || item->type == AST_TASK)
|
|
|
|
rename(item);
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// create AstModule instances for all modules in the AST tree and add them to 'design'
|
2019-03-21 14:52:29 -05:00
|
|
|
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
|
2019-06-19 07:38:50 -05:00
|
|
|
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
|
|
|
current_ast = ast;
|
2020-04-16 04:27:59 -05:00
|
|
|
current_ast_mod = nullptr;
|
2013-08-19 12:49:14 -05:00
|
|
|
flag_dump_ast1 = dump_ast1;
|
|
|
|
flag_dump_ast2 = dump_ast2;
|
2018-08-23 07:19:46 -05:00
|
|
|
flag_no_dump_ptr = no_dump_ptr;
|
2019-03-21 14:52:29 -05:00
|
|
|
flag_dump_vlog1 = dump_vlog1;
|
|
|
|
flag_dump_vlog2 = dump_vlog2;
|
2016-07-27 08:40:17 -05:00
|
|
|
flag_dump_rtlil = dump_rtlil;
|
2013-01-05 04:13:26 -06:00
|
|
|
flag_nolatches = nolatches;
|
2015-02-14 04:21:12 -06:00
|
|
|
flag_nomeminit = nomeminit;
|
2013-01-05 04:13:26 -06:00
|
|
|
flag_nomem2reg = nomem2reg;
|
2013-03-24 05:13:32 -05:00
|
|
|
flag_mem2reg = mem2reg;
|
2019-04-20 15:24:50 -05:00
|
|
|
flag_noblackbox = noblackbox;
|
2013-03-28 03:20:10 -05:00
|
|
|
flag_lib = lib;
|
2019-04-20 15:24:50 -05:00
|
|
|
flag_nowb = nowb;
|
2013-06-10 06:19:04 -05:00
|
|
|
flag_noopt = noopt;
|
2014-01-28 17:59:28 -06:00
|
|
|
flag_icells = icells;
|
2019-06-19 07:38:50 -05:00
|
|
|
flag_pwires = pwires;
|
2014-02-17 07:28:52 -06:00
|
|
|
flag_autowire = autowire;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(current_ast->type == AST_DESIGN);
|
2020-04-20 10:24:57 -05:00
|
|
|
for (AstNode *child : current_ast->children)
|
2014-08-21 05:42:28 -05:00
|
|
|
{
|
2020-04-20 10:24:57 -05:00
|
|
|
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
|
2014-08-21 05:42:28 -05:00
|
|
|
{
|
2016-11-15 05:42:43 -06:00
|
|
|
for (auto n : design->verilog_globals)
|
2020-04-20 10:24:57 -05:00
|
|
|
child->children.push_back(n->clone());
|
2014-08-21 05:42:28 -05:00
|
|
|
|
2020-03-15 14:02:47 -05:00
|
|
|
// append nodes from previous packages using package-qualified names
|
|
|
|
for (auto &n : design->verilog_packages) {
|
|
|
|
for (auto &o : n->children) {
|
2016-06-18 03:24:21 -05:00
|
|
|
AstNode *cloned_node = o->clone();
|
2020-03-15 14:02:47 -05:00
|
|
|
// log("cloned node %s\n", type2str(cloned_node->type).c_str());
|
|
|
|
if (cloned_node->type == AST_ENUM) {
|
|
|
|
for (auto &e : cloned_node->children) {
|
2018-03-09 06:47:11 -06:00
|
|
|
log_assert(e->type == AST_ENUM_ITEM);
|
|
|
|
e->str = n->str + std::string("::") + e->str.substr(1);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
|
|
|
|
}
|
2020-04-20 10:24:57 -05:00
|
|
|
child->children.push_back(cloned_node);
|
2016-06-18 03:24:21 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-04-20 10:24:57 -05:00
|
|
|
if (flag_icells && child->str.compare(0, 2, "\\$") == 0)
|
|
|
|
child->str = child->str.substr(1);
|
2014-08-21 05:42:28 -05:00
|
|
|
|
2021-03-02 09:43:53 -06:00
|
|
|
bool defer_local = defer;
|
|
|
|
if (!defer_local)
|
2020-04-20 10:24:57 -05:00
|
|
|
for (const AstNode *node : child->children)
|
2021-03-02 09:43:53 -06:00
|
|
|
if (node->type == AST_PARAMETER && param_has_no_default(node))
|
|
|
|
{
|
2020-04-20 10:24:57 -05:00
|
|
|
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str());
|
2021-03-02 09:43:53 -06:00
|
|
|
defer_local = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (defer_local)
|
2020-04-20 10:24:57 -05:00
|
|
|
child->str = "$abstract" + child->str;
|
2014-08-21 05:42:28 -05:00
|
|
|
|
2020-04-20 10:24:57 -05:00
|
|
|
if (design->has(child->str)) {
|
|
|
|
RTLIL::Module *existing_mod = design->module(child->str);
|
2019-08-12 14:06:45 -05:00
|
|
|
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
|
2020-04-20 10:24:57 -05:00
|
|
|
log_file_error(child->filename, child->location.first_line, "Re-definition of module `%s'!\n", child->str.c_str());
|
2018-05-03 08:25:59 -05:00
|
|
|
} else if (nooverwrite) {
|
2021-02-23 12:22:53 -06:00
|
|
|
log("Ignoring re-definition of module `%s' at %s.\n",
|
2020-04-20 10:24:57 -05:00
|
|
|
child->str.c_str(), child->loc_string().c_str());
|
2018-05-03 08:25:59 -05:00
|
|
|
continue;
|
|
|
|
} else {
|
2021-02-23 12:22:53 -06:00
|
|
|
log("Replacing existing%s module `%s' at %s.\n",
|
2020-04-02 11:51:32 -05:00
|
|
|
existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",
|
2020-04-20 10:24:57 -05:00
|
|
|
child->str.c_str(), child->loc_string().c_str());
|
2018-05-03 08:25:59 -05:00
|
|
|
design->remove(existing_mod);
|
|
|
|
}
|
2014-08-21 05:42:28 -05:00
|
|
|
}
|
|
|
|
|
2020-04-20 10:24:57 -05:00
|
|
|
process_module(design, child, defer_local);
|
2020-04-16 04:27:59 -05:00
|
|
|
current_ast_mod = nullptr;
|
2013-11-24 12:57:42 -06:00
|
|
|
}
|
2020-04-20 10:24:57 -05:00
|
|
|
else if (child->type == AST_PACKAGE) {
|
2020-03-15 14:02:47 -05:00
|
|
|
// process enum/other declarations
|
2023-04-04 15:53:01 -05:00
|
|
|
child->simplify(true, false, 1, -1, false, false);
|
2021-05-27 15:47:02 -05:00
|
|
|
rename_in_package_stmts(child);
|
2020-04-20 10:24:57 -05:00
|
|
|
design->verilog_packages.push_back(child->clone());
|
2020-04-22 07:51:20 -05:00
|
|
|
current_scope.clear();
|
2018-03-09 06:47:11 -06:00
|
|
|
}
|
2020-04-20 10:06:53 -05:00
|
|
|
else if (child->type == AST_BIND) {
|
|
|
|
// top-level bind construct
|
|
|
|
for (RTLIL::Binding *binding : child->genBindings())
|
|
|
|
design->add(binding);
|
|
|
|
}
|
2018-03-09 06:47:11 -06:00
|
|
|
else {
|
|
|
|
// must be global definition
|
2020-04-20 10:24:57 -05:00
|
|
|
if (child->type == AST_PARAMETER)
|
|
|
|
child->type = AST_LOCALPARAM; // cannot be overridden
|
|
|
|
design->verilog_globals.push_back(child->clone());
|
2020-04-22 07:51:20 -05:00
|
|
|
current_scope.clear();
|
2018-03-09 06:47:11 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// AstModule destructor
|
|
|
|
AstModule::~AstModule()
|
|
|
|
{
|
|
|
|
if (ast != NULL)
|
|
|
|
delete ast;
|
|
|
|
}
|
|
|
|
|
2018-10-20 05:45:51 -05:00
|
|
|
|
|
|
|
// An interface port with modport is specified like this:
|
|
|
|
// <interface_name>.<modport_name>
|
|
|
|
// This function splits the interface_name from the modport_name, and fails if it is not a valid combination
|
|
|
|
std::pair<std::string,std::string> AST::split_modport_from_type(std::string name_type)
|
|
|
|
{
|
|
|
|
std::string interface_type = "";
|
|
|
|
std::string interface_modport = "";
|
|
|
|
size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
|
|
|
|
// Separate the interface instance name from any modports:
|
|
|
|
if (ndots == 0) { // Does not have modport
|
|
|
|
interface_type = name_type;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
std::stringstream name_type_stream(name_type);
|
|
|
|
std::string segment;
|
|
|
|
std::vector<std::string> seglist;
|
|
|
|
while(std::getline(name_type_stream, segment, '.')) {
|
|
|
|
seglist.push_back(segment);
|
|
|
|
}
|
|
|
|
if (ndots == 1) { // Has modport
|
|
|
|
interface_type = seglist[0];
|
|
|
|
interface_modport = seglist[1];
|
|
|
|
}
|
|
|
|
else { // Erroneous port type
|
|
|
|
log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return std::pair<std::string,std::string>(interface_type, interface_modport);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode * AST::find_modport(AstNode *intf, std::string name)
|
|
|
|
{
|
|
|
|
for (auto &ch : intf->children)
|
|
|
|
if (ch->type == AST_MODPORT)
|
|
|
|
if (ch->str == name) // Modport found
|
|
|
|
return ch;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Iterate over all wires in an interface and add them as wires in the AST module:
|
|
|
|
void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport)
|
|
|
|
{
|
2020-03-19 01:15:53 -05:00
|
|
|
for (auto w : intfmodule->wires()){
|
|
|
|
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
|
|
|
|
std::string origname = log_id(w->name);
|
2018-10-20 05:45:51 -05:00
|
|
|
std::string newname = intfname + "." + origname;
|
|
|
|
wire->str = newname;
|
|
|
|
if (modport != NULL) {
|
|
|
|
bool found_in_modport = false;
|
|
|
|
// Search for the current wire in the wire list for the current modport
|
|
|
|
for (auto &ch : modport->children) {
|
|
|
|
if (ch->type == AST_MODPORTMEMBER) {
|
|
|
|
std::string compare_name = "\\" + origname;
|
|
|
|
if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
|
|
|
|
found_in_modport = true;
|
|
|
|
wire->is_input = ch->is_input;
|
|
|
|
wire->is_output = ch->is_output;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (found_in_modport) {
|
|
|
|
module_ast->children.push_back(wire);
|
|
|
|
}
|
|
|
|
else { // If not found in modport, do not create port
|
|
|
|
delete wire;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else { // If no modport, set inout
|
|
|
|
wire->is_input = true;
|
|
|
|
wire->is_output = true;
|
|
|
|
module_ast->children.push_back(wire);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
// AstModules may contain cells marked with ID::reprocess_after, which indicates
|
|
|
|
// that it should be reprocessed once the specified module has been elaborated.
|
|
|
|
bool AstModule::reprocess_if_necessary(RTLIL::Design *design)
|
|
|
|
{
|
|
|
|
for (const RTLIL::Cell *cell : cells())
|
|
|
|
{
|
|
|
|
std::string modname = cell->get_string_attribute(ID::reprocess_after);
|
|
|
|
if (modname.empty())
|
|
|
|
continue;
|
|
|
|
if (design->module(modname) || design->module("$abstract" + modname)) {
|
|
|
|
log("Reprocessing module %s because instantiated module %s has become available.\n",
|
|
|
|
log_id(name), log_id(modname));
|
|
|
|
loadconfig();
|
|
|
|
process_and_replace_module(design, this, ast, NULL);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-10-13 13:34:44 -05:00
|
|
|
// When an interface instance is found in a module, the whole RTLIL for the module will be rederived again
|
|
|
|
// from AST. The interface members are copied into the AST module with the prefix of the interface.
|
2021-10-19 19:43:30 -05:00
|
|
|
void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module*> &local_interfaces)
|
2018-10-11 16:33:31 -05:00
|
|
|
{
|
2019-09-20 05:16:20 -05:00
|
|
|
loadconfig();
|
|
|
|
|
2018-10-11 16:33:31 -05:00
|
|
|
AstNode *new_ast = ast->clone();
|
|
|
|
for (auto &intf : local_interfaces) {
|
|
|
|
std::string intfname = intf.first.str();
|
|
|
|
RTLIL::Module *intfmodule = intf.second;
|
2020-03-19 01:15:53 -05:00
|
|
|
for (auto w : intfmodule->wires()){
|
|
|
|
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
|
|
|
|
std::string newname = log_id(w->name);
|
2018-10-11 16:33:31 -05:00
|
|
|
newname = intfname + "." + newname;
|
|
|
|
wire->str = newname;
|
|
|
|
new_ast->children.push_back(wire);
|
|
|
|
}
|
|
|
|
}
|
2018-10-13 13:34:44 -05:00
|
|
|
|
2018-10-20 04:58:25 -05:00
|
|
|
AstNode *ast_before_replacing_interface_ports = new_ast->clone();
|
|
|
|
|
2018-10-20 05:45:51 -05:00
|
|
|
// Explode all interface ports. Note this will only have an effect on 'top
|
|
|
|
// level' modules. Other sub-modules will have their interface ports
|
|
|
|
// exploded via the derive(..) function
|
2018-10-20 04:58:25 -05:00
|
|
|
for (size_t i =0; i<new_ast->children.size(); i++)
|
|
|
|
{
|
|
|
|
AstNode *ch2 = new_ast->children[i];
|
2018-10-20 05:45:51 -05:00
|
|
|
if (ch2->type == AST_INTERFACEPORT) { // Is an interface port
|
|
|
|
std::string name_port = ch2->str; // Name of the interface port
|
2018-10-20 04:58:25 -05:00
|
|
|
if (ch2->children.size() > 0) {
|
|
|
|
for(size_t j=0; j<ch2->children.size();j++) {
|
|
|
|
AstNode *ch = ch2->children[j];
|
2018-10-20 05:45:51 -05:00
|
|
|
if(ch->type == AST_INTERFACEPORTTYPE) { // Found the AST node containing the type of the interface
|
|
|
|
std::pair<std::string,std::string> res = split_modport_from_type(ch->str);
|
|
|
|
std::string interface_type = res.first;
|
|
|
|
std::string interface_modport = res.second; // Is "", if no modport
|
2020-03-19 01:15:53 -05:00
|
|
|
if (design->module(interface_type) != nullptr) {
|
2018-10-20 05:45:51 -05:00
|
|
|
// Add a cell to the module corresponding to the interface port such that
|
|
|
|
// it can further propagated down if needed:
|
2018-10-20 04:58:25 -05:00
|
|
|
AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE);
|
|
|
|
celltype_for_intf->str = interface_type;
|
|
|
|
AstNode *cell_for_intf = new AstNode(AST_CELL, celltype_for_intf);
|
|
|
|
cell_for_intf->str = name_port + "_inst_from_top_dummy";
|
|
|
|
new_ast->children.push_back(cell_for_intf);
|
|
|
|
|
2018-10-20 05:45:51 -05:00
|
|
|
// Get all members of this non-overridden dummy interface instance:
|
2020-03-19 01:15:53 -05:00
|
|
|
RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming
|
2018-10-20 05:45:51 -05:00
|
|
|
// reprocess_module is called from the hierarchy pass) be
|
|
|
|
// present in design->modules_
|
2018-10-20 04:58:25 -05:00
|
|
|
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
|
|
|
|
std::string interface_modport_compare_str = "\\" + interface_modport;
|
2018-10-20 05:45:51 -05:00
|
|
|
AstNode *modport = find_modport(ast_module_of_interface->ast, interface_modport_compare_str); // modport == NULL if no modport
|
|
|
|
// Iterate over all wires in the interface and add them to the module:
|
|
|
|
explode_interface_port(new_ast, intfmodule, name_port, modport);
|
2018-10-20 04:58:25 -05:00
|
|
|
}
|
2018-10-20 05:45:51 -05:00
|
|
|
break;
|
2018-10-20 04:58:25 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:43:30 -05:00
|
|
|
// Generate RTLIL from AST for the new module and add to the design,
|
|
|
|
// renaming this module to move it out of the way.
|
|
|
|
RTLIL::Module* new_module =
|
|
|
|
process_and_replace_module(design, this, new_ast, ast_before_replacing_interface_ports);
|
2018-10-13 13:34:44 -05:00
|
|
|
|
2021-10-19 19:43:30 -05:00
|
|
|
delete new_ast;
|
2018-10-13 13:34:44 -05:00
|
|
|
|
|
|
|
// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
|
2021-10-19 19:43:30 -05:00
|
|
|
new_module->set_bool_attribute(ID::interfaces_replaced_in_module);
|
2018-10-11 16:33:31 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
|
2018-10-13 13:34:44 -05:00
|
|
|
// This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
|
2020-03-18 13:21:53 -05:00
|
|
|
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/)
|
2018-10-11 16:33:31 -05:00
|
|
|
{
|
|
|
|
AstNode *new_ast = NULL;
|
2019-09-30 16:11:01 -05:00
|
|
|
std::string modname = derive_common(design, parameters, &new_ast);
|
2018-10-11 16:33:31 -05:00
|
|
|
|
|
|
|
// Since interfaces themselves may be instantiated with different parameters,
|
|
|
|
// "modname" must also take those into account, so that unique modules
|
|
|
|
// are derived for any variant of interface connections:
|
|
|
|
std::string interf_info = "";
|
|
|
|
|
|
|
|
bool has_interfaces = false;
|
|
|
|
for(auto &intf : interfaces) {
|
|
|
|
interf_info += log_id(intf.second->name);
|
|
|
|
has_interfaces = true;
|
|
|
|
}
|
|
|
|
|
2019-09-30 16:52:04 -05:00
|
|
|
std::string new_modname = modname;
|
2018-10-11 16:33:31 -05:00
|
|
|
if (has_interfaces)
|
2019-09-30 16:52:04 -05:00
|
|
|
new_modname += "$interfaces$" + interf_info;
|
2018-10-11 16:33:31 -05:00
|
|
|
|
|
|
|
|
2019-09-30 16:52:04 -05:00
|
|
|
if (!design->has(new_modname)) {
|
|
|
|
if (!new_ast) {
|
|
|
|
auto mod = dynamic_cast<AstModule*>(design->module(modname));
|
|
|
|
new_ast = mod->ast->clone();
|
|
|
|
}
|
|
|
|
modname = new_modname;
|
2018-10-11 16:33:31 -05:00
|
|
|
new_ast->str = modname;
|
2018-10-13 13:34:44 -05:00
|
|
|
|
|
|
|
// Iterate over all interfaces which are ports in this module:
|
2018-10-11 16:33:31 -05:00
|
|
|
for(auto &intf : interfaces) {
|
|
|
|
RTLIL::Module * intfmodule = intf.second;
|
|
|
|
std::string intfname = intf.first.str();
|
2018-10-13 13:34:44 -05:00
|
|
|
// Check if a modport applies for the interface port:
|
2018-10-12 13:58:37 -05:00
|
|
|
AstNode *modport = NULL;
|
|
|
|
if (modports.count(intfname) > 0) {
|
|
|
|
std::string interface_modport = modports.at(intfname).str();
|
|
|
|
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
|
|
|
|
AstNode *ast_node_of_interface = ast_module_of_interface->ast;
|
2018-10-20 05:45:51 -05:00
|
|
|
modport = find_modport(ast_node_of_interface, interface_modport);
|
2018-10-12 13:58:37 -05:00
|
|
|
}
|
2018-10-13 13:34:44 -05:00
|
|
|
// Iterate over all wires in the interface and add them to the module:
|
2018-10-20 05:45:51 -05:00
|
|
|
explode_interface_port(new_ast, intfmodule, intfname, modport);
|
2018-10-11 16:33:31 -05:00
|
|
|
}
|
|
|
|
|
2021-03-23 11:49:11 -05:00
|
|
|
process_module(design, new_ast, false);
|
2018-10-11 16:33:31 -05:00
|
|
|
design->module(modname)->check();
|
|
|
|
|
|
|
|
RTLIL::Module* mod = design->module(modname);
|
|
|
|
|
2018-10-13 13:34:44 -05:00
|
|
|
// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
|
2018-10-11 16:33:31 -05:00
|
|
|
for(auto &intf : interfaces) {
|
2020-03-19 01:15:53 -05:00
|
|
|
if(mod->wire(intf.first) != nullptr) {
|
2020-03-30 13:08:25 -05:00
|
|
|
// Normally, removing wires would be batched together as it's an
|
|
|
|
// expensive operation, however, in this case doing so would mean
|
|
|
|
// that a cell with the same name cannot be created (below)...
|
|
|
|
// Since we won't expect many interfaces to exist in a module,
|
|
|
|
// we can let this slide...
|
2020-03-27 04:46:40 -05:00
|
|
|
pool<RTLIL::Wire*> to_remove;
|
2020-03-19 01:15:53 -05:00
|
|
|
to_remove.insert(mod->wire(intf.first));
|
2020-03-27 04:46:40 -05:00
|
|
|
mod->remove(to_remove);
|
2018-10-11 16:33:31 -05:00
|
|
|
mod->fixup_ports();
|
2020-03-30 13:08:25 -05:00
|
|
|
// We copy the cell of the interface to the sub-module such that it
|
|
|
|
// can further be found if it is propagated down to sub-sub-modules etc.
|
|
|
|
RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name);
|
2020-03-12 14:57:01 -05:00
|
|
|
new_subcell->set_bool_attribute(ID::is_interface);
|
2018-10-11 16:33:31 -05:00
|
|
|
}
|
|
|
|
else {
|
2018-10-12 15:02:29 -05:00
|
|
|
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
|
2018-10-11 16:33:31 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-10-13 13:34:44 -05:00
|
|
|
// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
|
2018-10-11 16:33:31 -05:00
|
|
|
if (interfaces.size() > 0) {
|
2020-04-02 11:51:32 -05:00
|
|
|
mod->set_bool_attribute(ID::interfaces_replaced_in_module);
|
2018-10-11 16:33:31 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
2020-11-26 06:28:28 -06:00
|
|
|
modname = new_modname;
|
2018-10-11 16:33:31 -05:00
|
|
|
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
|
|
|
|
}
|
|
|
|
|
|
|
|
delete new_ast;
|
|
|
|
return modname;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
|
2020-03-18 13:21:53 -05:00
|
|
|
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool /*mayfail*/)
|
2018-10-11 16:33:31 -05:00
|
|
|
{
|
2020-04-02 11:51:32 -05:00
|
|
|
bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
|
2020-02-18 17:32:56 -06:00
|
|
|
|
2018-10-11 16:33:31 -05:00
|
|
|
AstNode *new_ast = NULL;
|
2020-02-18 17:32:56 -06:00
|
|
|
std::string modname = derive_common(design, parameters, &new_ast, quiet);
|
2018-10-11 16:33:31 -05:00
|
|
|
|
2023-01-17 05:58:08 -06:00
|
|
|
if (!design->has(modname) && new_ast) {
|
2018-10-11 16:33:31 -05:00
|
|
|
new_ast->str = modname;
|
2021-03-23 11:49:11 -05:00
|
|
|
process_module(design, new_ast, false, NULL, quiet);
|
2018-10-11 16:33:31 -05:00
|
|
|
design->module(modname)->check();
|
2020-02-18 17:32:56 -06:00
|
|
|
} else if (!quiet) {
|
2018-10-11 16:33:31 -05:00
|
|
|
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
|
|
|
|
}
|
|
|
|
|
|
|
|
delete new_ast;
|
|
|
|
return modname;
|
|
|
|
}
|
|
|
|
|
2021-03-17 12:30:49 -05:00
|
|
|
static std::string serialize_param_value(const RTLIL::Const &val) {
|
|
|
|
std::string res;
|
|
|
|
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_STRING)
|
|
|
|
res.push_back('t');
|
|
|
|
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED)
|
|
|
|
res.push_back('s');
|
|
|
|
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_REAL)
|
|
|
|
res.push_back('r');
|
|
|
|
res += stringf("%d", GetSize(val));
|
|
|
|
res.push_back('\'');
|
|
|
|
for (int i = GetSize(val) - 1; i >= 0; i--) {
|
|
|
|
switch (val.bits[i]) {
|
|
|
|
case RTLIL::State::S0: res.push_back('0'); break;
|
|
|
|
case RTLIL::State::S1: res.push_back('1'); break;
|
|
|
|
case RTLIL::State::Sx: res.push_back('x'); break;
|
|
|
|
case RTLIL::State::Sz: res.push_back('z'); break;
|
|
|
|
case RTLIL::State::Sa: res.push_back('?'); break;
|
|
|
|
case RTLIL::State::Sm: res.push_back('m'); break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
std::string AST::derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> ¶meters) {
|
|
|
|
std::string para_info;
|
|
|
|
for (const auto &elem : parameters)
|
|
|
|
para_info += stringf("%s=%s", elem.first.c_str(), serialize_param_value(elem.second).c_str());
|
|
|
|
|
|
|
|
if (para_info.size() > 60)
|
|
|
|
return "$paramod$" + sha1(para_info) + stripped_name;
|
|
|
|
else
|
|
|
|
return "$paramod" + stripped_name + para_info;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// create a new parametric module (when needed) and return the name of the generated module
|
2020-03-18 13:21:53 -05:00
|
|
|
std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2014-08-01 17:45:25 -05:00
|
|
|
std::string stripped_name = name.str();
|
2023-01-17 05:58:08 -06:00
|
|
|
(*new_ast_out) = nullptr;
|
2014-02-13 06:59:13 -06:00
|
|
|
|
2019-08-07 14:20:08 -05:00
|
|
|
if (stripped_name.compare(0, 9, "$abstract") == 0)
|
2014-02-13 06:59:13 -06:00
|
|
|
stripped_name = stripped_name.substr(9);
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
int para_counter = 0;
|
2021-10-19 19:46:26 -05:00
|
|
|
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
|
2019-09-30 16:11:01 -05:00
|
|
|
for (const auto child : ast->children) {
|
2013-01-05 04:13:26 -06:00
|
|
|
if (child->type != AST_PARAMETER)
|
|
|
|
continue;
|
|
|
|
para_counter++;
|
2020-03-18 13:21:53 -05:00
|
|
|
auto it = parameters.find(child->str);
|
|
|
|
if (it != parameters.end()) {
|
2020-02-18 17:32:56 -06:00
|
|
|
if (!quiet)
|
2020-03-18 13:21:53 -05:00
|
|
|
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
|
2021-10-19 19:46:26 -05:00
|
|
|
named_parameters.emplace_back(child->str, it->second);
|
2013-01-05 04:13:26 -06:00
|
|
|
continue;
|
|
|
|
}
|
2020-03-18 13:21:53 -05:00
|
|
|
it = parameters.find(stringf("$%d", para_counter));
|
|
|
|
if (it != parameters.end()) {
|
2020-02-18 17:32:56 -06:00
|
|
|
if (!quiet)
|
2020-03-18 13:21:53 -05:00
|
|
|
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
|
2021-10-19 19:46:26 -05:00
|
|
|
named_parameters.emplace_back(child->str, it->second);
|
2019-09-30 16:11:01 -05:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
std::string modname = stripped_name;
|
|
|
|
if (parameters.size()) // not named_parameters to cover hierarchical defparams
|
|
|
|
modname = derived_module_name(stripped_name, named_parameters);
|
2019-09-30 16:11:01 -05:00
|
|
|
|
|
|
|
if (design->has(modname))
|
|
|
|
return modname;
|
|
|
|
|
2020-02-18 17:32:56 -06:00
|
|
|
if (!quiet)
|
|
|
|
log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
|
2019-09-30 16:11:01 -05:00
|
|
|
loadconfig();
|
|
|
|
|
2020-03-18 13:21:53 -05:00
|
|
|
pool<IdString> rewritten;
|
|
|
|
rewritten.reserve(GetSize(parameters));
|
|
|
|
|
2019-09-30 16:11:01 -05:00
|
|
|
AstNode *new_ast = ast->clone();
|
2020-04-17 22:43:15 -05:00
|
|
|
if (!new_ast->attributes.count(ID::hdlname))
|
|
|
|
new_ast->attributes[ID::hdlname] = AstNode::mkconst_str(stripped_name);
|
|
|
|
|
2019-09-30 16:11:01 -05:00
|
|
|
para_counter = 0;
|
|
|
|
for (auto child : new_ast->children) {
|
|
|
|
if (child->type != AST_PARAMETER)
|
|
|
|
continue;
|
|
|
|
para_counter++;
|
2020-03-18 13:21:53 -05:00
|
|
|
auto it = parameters.find(child->str);
|
|
|
|
if (it != parameters.end()) {
|
2020-02-18 17:32:56 -06:00
|
|
|
if (!quiet)
|
2020-03-18 13:21:53 -05:00
|
|
|
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
|
2019-09-30 16:11:01 -05:00
|
|
|
goto rewrite_parameter;
|
|
|
|
}
|
2020-03-18 13:21:53 -05:00
|
|
|
it = parameters.find(stringf("$%d", para_counter));
|
|
|
|
if (it != parameters.end()) {
|
2020-02-18 17:32:56 -06:00
|
|
|
if (!quiet)
|
2020-03-18 13:21:53 -05:00
|
|
|
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
|
2013-01-05 04:13:26 -06:00
|
|
|
goto rewrite_parameter;
|
|
|
|
}
|
2019-09-30 16:11:01 -05:00
|
|
|
continue;
|
|
|
|
rewrite_parameter:
|
2021-03-02 09:43:53 -06:00
|
|
|
if (param_has_no_default(child))
|
|
|
|
child->children.insert(child->children.begin(), nullptr);
|
2019-09-30 16:11:01 -05:00
|
|
|
delete child->children.at(0);
|
2020-03-18 13:21:53 -05:00
|
|
|
if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {
|
2019-09-30 16:11:01 -05:00
|
|
|
child->children[0] = new AstNode(AST_REALVALUE);
|
2020-03-18 13:21:53 -05:00
|
|
|
child->children[0]->realvalue = std::stod(it->second.decode_string());
|
|
|
|
} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
|
|
|
child->children[0] = AstNode::mkconst_str(it->second.decode_string());
|
2019-09-30 16:11:01 -05:00
|
|
|
else
|
2020-03-18 13:21:53 -05:00
|
|
|
child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
|
|
|
|
rewritten.insert(it->first);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2016-11-15 06:35:19 -06:00
|
|
|
|
2020-03-18 13:21:53 -05:00
|
|
|
if (GetSize(rewritten) < GetSize(parameters))
|
|
|
|
for (const auto ¶m : parameters) {
|
|
|
|
if (rewritten.count(param.first))
|
|
|
|
continue;
|
|
|
|
AstNode *defparam = new AstNode(AST_DEFPARAM, new AstNode(AST_IDENTIFIER));
|
|
|
|
defparam->children[0]->str = param.first.str();
|
|
|
|
if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
|
|
|
defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string()));
|
|
|
|
else
|
|
|
|
defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
|
|
|
|
new_ast->children.push_back(defparam);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2018-10-11 16:33:31 -05:00
|
|
|
(*new_ast_out) = new_ast;
|
2013-01-05 04:13:26 -06:00
|
|
|
return modname;
|
|
|
|
}
|
|
|
|
|
2013-07-27 07:27:51 -05:00
|
|
|
RTLIL::Module *AstModule::clone() const
|
|
|
|
{
|
|
|
|
AstModule *new_mod = new AstModule;
|
2014-07-27 14:12:09 -05:00
|
|
|
new_mod->name = name;
|
2013-07-27 07:27:51 -05:00
|
|
|
cloneInto(new_mod);
|
|
|
|
|
|
|
|
new_mod->ast = ast->clone();
|
|
|
|
new_mod->nolatches = nolatches;
|
2015-02-14 04:21:12 -06:00
|
|
|
new_mod->nomeminit = nomeminit;
|
2013-07-27 07:27:51 -05:00
|
|
|
new_mod->nomem2reg = nomem2reg;
|
|
|
|
new_mod->mem2reg = mem2reg;
|
2019-07-22 03:37:40 -05:00
|
|
|
new_mod->noblackbox = noblackbox;
|
2013-07-27 07:27:51 -05:00
|
|
|
new_mod->lib = lib;
|
2019-07-22 03:37:40 -05:00
|
|
|
new_mod->nowb = nowb;
|
2013-07-27 07:27:51 -05:00
|
|
|
new_mod->noopt = noopt;
|
2014-01-28 17:59:28 -06:00
|
|
|
new_mod->icells = icells;
|
2019-06-19 07:38:50 -05:00
|
|
|
new_mod->pwires = pwires;
|
2014-02-17 07:28:52 -06:00
|
|
|
new_mod->autowire = autowire;
|
2013-07-27 07:27:51 -05:00
|
|
|
|
|
|
|
return new_mod;
|
|
|
|
}
|
|
|
|
|
2019-09-20 05:16:20 -05:00
|
|
|
void AstModule::loadconfig() const
|
|
|
|
{
|
|
|
|
current_ast = NULL;
|
|
|
|
flag_dump_ast1 = false;
|
|
|
|
flag_dump_ast2 = false;
|
|
|
|
flag_dump_vlog1 = false;
|
|
|
|
flag_dump_vlog2 = false;
|
|
|
|
flag_nolatches = nolatches;
|
|
|
|
flag_nomeminit = nomeminit;
|
|
|
|
flag_nomem2reg = nomem2reg;
|
|
|
|
flag_mem2reg = mem2reg;
|
|
|
|
flag_noblackbox = noblackbox;
|
|
|
|
flag_lib = lib;
|
|
|
|
flag_nowb = nowb;
|
|
|
|
flag_noopt = noopt;
|
|
|
|
flag_icells = icells;
|
|
|
|
flag_pwires = pwires;
|
|
|
|
flag_autowire = autowire;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2023-04-04 04:53:50 -05:00
|
|
|
void AstNode::input_error(const char *format, ...) const
|
|
|
|
{
|
|
|
|
va_list ap;
|
|
|
|
va_start(ap, format);
|
|
|
|
logv_file_error(filename, location.first_line, format, ap);
|
|
|
|
}
|
|
|
|
|
2014-07-31 06:19:47 -05:00
|
|
|
YOSYS_NAMESPACE_END
|