mirror of https://github.com/YosysHQ/yosys.git
module->derive() to be lazy and not touch ast if already derived
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a274b7cc86
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08b55a20e3
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@ -1382,10 +1382,10 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
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// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
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// This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool /*mayfail*/)
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{
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AstNode *new_ast = NULL;
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std::string modname = derive_common(design, parameters, &new_ast, mayfail);
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std::string modname = derive_common(design, parameters, &new_ast);
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// Since interfaces themselves may be instantiated with different parameters,
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// "modname" must also take those into account, so that unique modules
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@ -1455,10 +1455,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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}
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// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool /*mayfail*/)
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{
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AstNode *new_ast = NULL;
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std::string modname = derive_common(design, parameters, &new_ast, mayfail);
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std::string modname = derive_common(design, parameters, &new_ast);
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if (!design->has(modname)) {
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new_ast->str = modname;
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@ -1473,47 +1473,75 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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}
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// create a new parametric module (when needed) and return the name of the generated module
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std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool)
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std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out)
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{
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std::string stripped_name = name.str();
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if (stripped_name.compare(0, 9, "$abstract") == 0)
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stripped_name = stripped_name.substr(9);
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log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
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loadconfig();
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std::string para_info;
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AstNode *new_ast = ast->clone();
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int para_counter = 0;
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int orig_parameters_n = parameters.size();
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for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
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AstNode *child = *it;
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for (const auto child : ast->children) {
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if (child->type != AST_PARAMETER)
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continue;
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para_counter++;
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std::string para_id = child->str;
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if (parameters.count(para_id) > 0) {
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
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rewrite_parameter:
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para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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delete child->children.at(0);
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if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) {
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child->children[0] = new AstNode(AST_REALVALUE);
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child->children[0]->realvalue = std::stod(parameters[para_id].decode_string());
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} else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0)
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child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string());
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else
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child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0);
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parameters.erase(para_id);
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continue;
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}
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para_id = stringf("$%d", para_counter);
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if (parameters.count(para_id) > 0) {
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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continue;
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}
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}
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std::string modname;
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if (parameters.size() == 0)
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modname = stripped_name;
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else if (para_info.size() > 60)
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modname = "$paramod$" + sha1(para_info) + stripped_name;
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else
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modname = "$paramod" + stripped_name + para_info;
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if (design->has(modname))
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return modname;
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log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
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loadconfig();
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AstNode *new_ast = ast->clone();
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para_counter = 0;
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for (auto child : new_ast->children) {
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if (child->type != AST_PARAMETER)
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continue;
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para_counter++;
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std::string para_id = child->str;
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if (parameters.count(para_id) > 0) {
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
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goto rewrite_parameter;
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}
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para_id = stringf("$%d", para_counter);
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if (parameters.count(para_id) > 0) {
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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goto rewrite_parameter;
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}
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continue;
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rewrite_parameter:
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delete child->children.at(0);
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if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) {
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child->children[0] = new AstNode(AST_REALVALUE);
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child->children[0]->realvalue = std::stod(parameters[para_id].decode_string());
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} else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0)
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child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string());
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else
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child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0);
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parameters.erase(para_id);
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}
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for (auto param : parameters) {
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@ -1526,16 +1554,6 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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new_ast->children.push_back(defparam);
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}
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std::string modname;
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if (orig_parameters_n == 0)
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modname = stripped_name;
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else if (para_info.size() > 60)
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modname = "$paramod$" + sha1(para_info) + stripped_name;
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else
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modname = "$paramod" + stripped_name + para_info;
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(*new_ast_out) = new_ast;
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return modname;
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}
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@ -296,7 +296,7 @@ namespace AST
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~AstModule() YS_OVERRIDE;
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RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
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RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;
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std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
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std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out);
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void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
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RTLIL::Module *clone() const YS_OVERRIDE;
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void loadconfig() const;
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