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caravel
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379 Commits

Author SHA1 Message Date
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the 
same file), errors (buffer output pin name, power supplies not
passed at the top level).  Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation.  The buffering has now been properly
verified.
 2022-10-14 10:51:29 -04:00
Passant 4609abd7e2 remove unpowered gate level netlist 2022-10-14 02:42:37 -07:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
Marwan Abbas b8651328f9
Merge branch 'caravel_redesign' into cocotb 2022-10-13 21:14:42 +02:00
marwaneltoukhy b07d91ef7a resolve conflict 2022-10-13 12:11:42 -07:00
Passant c3a2c8650e update caravel top-level rtl to add `buff_flash_clkrst` module 2022-10-13 12:11:22 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst 
Buff flash clkrst
 2022-10-13 20:53:18 +02:00
Marwan Abbas 14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views 
Housekeeping final views
 2022-10-13 20:47:09 +02:00
passant5 acd6aeb0dc
Delete housekeeping.nl.v 2022-10-13 20:35:24 +02:00
Marwan Abbas e72f819020
Merge pull request #210 from mo-hosni/final_views 
mgmt_protect final views
 2022-10-13 20:33:57 +02:00
passant5 dd2c99b3de
Delete mgmt_protect.nl.v 2022-10-13 20:31:42 +02:00
Marwan Abbas 08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering 
Caravel clocking reharden
 2022-10-13 20:13:45 +02:00
passant5 9b009167a4
Delete mgmt_protect.nl.v 2022-10-13 20:09:00 +02:00
kareem d5379ab6f9 fix power pins assignment of clockp buffers again 2022-10-13 11:02:35 -07:00
kareem fdf1f11ece fix power pins assignment of clockp buffers 2022-10-13 11:00:04 -07:00
kareem c922241c3f reharden: caravel_clocking 
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
 2022-10-13 10:54:04 -07:00
mo-hosni 889aa7e308 add buff_flash_clkrst 2022-10-13 10:35:51 -07:00
Tim Edwards f7ec0cd012 Added buffers to the top level, inside a macro called 
gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
 2022-10-13 13:29:27 -04:00
mo-hosni 0389423ea6 add housekeeping 2022-10-13 10:15:05 -07:00
mo-hosni 1aaebf5cbb add mgmt_protect 2022-10-13 10:11:45 -07:00
M0stafaRady 1bae9af845 delete trash files 2022-10-13 09:55:18 -07:00
M0stafaRady c538f2923d Remove wrong sys.exit from cocotb script 2022-10-13 08:55:01 -07:00
M0stafaRady a8a3be6a8c Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 08:43:56 -07:00
M0stafaRady ae249eb8db update sdf files location 2022-10-13 08:43:50 -07:00
M0stafaRady 1d8eac5f48 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 08:18:17 -07:00
M0stafaRady 86f2c04d3e Add mem_dff2 test and update script to change the linker script 2022-10-13 08:18:08 -07:00
M0stafaRady 27e6272987 move primetime sdfs under signoff/caravel/primetime_signoff/ 2022-10-13 07:00:03 -07:00
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem 0eed96f33f reharden: digital_pll 
~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
 2022-10-13 06:21:08 -07:00
kareem bb2d983e03 + add a size 16 buf for clockp signal in digital_pll 2022-10-13 05:57:09 -07:00
M0stafaRady 8991af8ff1 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 04:25:18 -07:00
M0stafaRady 5d3766edf7 update script and top level testbench for sdf 2022-10-13 04:25:14 -07:00
M0stafaRady f5e1060c6d Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 04:05:38 -07:00
M0stafaRady ceac6defa1 fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
M0stafaRady 95cca2dec0 optimize bitbang tests 2022-10-12 16:06:02 -07:00
M0stafaRady 7e6ec8d394 Merge branch 'caravel_redesign' into cocotb 2022-10-12 14:49:27 -07:00
M0stafaRady dce509ab11 update script and testbench top level to include sdf 2022-10-12 14:41:37 -07:00
kareem 8c95a58e0d ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
M0stafaRady ac6284599d Merge branch 'caravel_redesign' into cocotb 2022-10-12 10:42:57 -07:00
M0stafaRady e8870d6a8b fix errors for gate level 2022-10-12 10:29:56 -07:00
kareem 9ccb0ff2ed reharden!: caravel 
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
 2022-10-12 04:45:08 -07:00
mo-hosni db2cc848b2 Added constant block openlane files and powered gl and modified housekeeping config.tcl 2022-10-12 04:12:27 -07:00
M0stafaRady 471e150167 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-12 03:57:56 -07:00
M0stafaRady d994a2e741 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-12 03:57:33 -07:00
M0stafaRady d464a475e0 update gpio tests to release housekeeping spi csb 2022-10-12 03:57:22 -07:00
M0stafaRady 10618bd41c Merge branch 'caravel_redesign' into cocotb 2022-10-12 02:05:27 -07:00
M0stafaRady 685518477d add folder to store important sessions 2022-10-12 02:03:06 -07:00
mo-hosni 76f8d37496 Rehardened housekeeping to fix Antenna violations. 2022-10-11 16:41:50 -07:00
M0stafaRady 71829abbc5 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-11 14:00:58 -07:00
M0stafaRady 2a5c7b876b fix some timeout and errors due to cpu became slower and sram interface are deleted 2022-10-11 14:00:49 -07:00
M0stafaRady de6d55f3ee trial for increase SPI clock 2022-10-11 13:44:56 -07:00
M0stafaRady bd40646465 Update caravel to force high at gpio3 at the start of test 2022-10-11 08:30:02 -07:00
kareem b0abb4e164 add chip_io gl 
~ update interactive script for chip_io.v for recent openlane
~ update config.tcl for recent openlane
~ add a verilog stub for sky130_fd_io__top_xres4v2 as
the io verilog models are not readable by yosys
 2022-10-11 07:35:13 -07:00
M0stafaRady 9cc8ebf28a update verify_cocotb script to include sdf 2022-10-11 07:30:37 -07:00
M0stafaRady 3fe7f3f38b fix tests timeout 2022-10-11 06:04:16 -07:00
M0stafaRady 327900b526 fix bug of wrapper ack 2022-10-11 06:02:44 -07:00
M0stafaRady 150d83fe48 Merge branch 'caravel_redesign' into cocotb 2022-10-11 03:56:05 -07:00
Mohamed Shalan 68b7d7f99f
Merge pull request #173 from mo-hosni/caravel_redesign 
Caravel redesign
 2022-10-11 10:48:50 +02:00
Mohamed Shalan 11530f691e
Merge pull request #165 from efabless/misc-rtl-changes 
some rtl changes
 2022-10-11 10:48:18 +02:00
Mohamed Hosni ee17bcf177
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-11 01:47:06 -07:00
mo-hosni df05079b6f update houskeepong powere netlst and fixed some antenna violations 2022-10-11 01:46:23 -07:00
Mohamed Shalan fe3d2b927f
Merge pull request #139 from efabless/cocotb 
new environment for simulation automation with cocotb and vcs
 2022-10-11 10:41:22 +02:00
mo-hosni e1b2509aad update mgmt_protect gl to be powered 2022-10-11 01:40:51 -07:00
Mohamed Shalan 344f806980
Merge pull request #166 from efabless/gpio_control_block-sparecell 
gpio_control_block sparecell
 2022-10-11 10:39:50 +02:00
Mohamed Shalan db9362d858
Merge branch 'caravel_redesign' into misc-rtl-changes 2022-10-11 10:39:32 +02:00
M0stafaRady 7fe790649d Add gpio_all_bidir_user test 2022-10-10 15:59:20 -07:00
M0stafaRady 8cca3a5002 Add gpio_all_i_pd_user and gpio_all_i_pu_user 2022-10-10 14:49:24 -07:00
M0stafaRady 01a9fd928f
Fix typo at mprj_io (#168) 
* Fix typo at mprj_io

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
 2022-10-10 12:11:05 -07:00
M0stafaRady a572a8ec14 add gpio_all_i_user test 2022-10-10 09:07:32 -07:00
M0stafaRady e2245ad333 enhance gpio_all_i test to include more checkers 2022-10-10 07:42:02 -07:00
M0stafaRady 71d53b9958 added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list 2022-10-10 06:23:47 -07:00
kareem f4218ddde9 reharden!: gpio_control_block 
- reimplement using a sparecell
- reimplement using newest open_pdks

!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible

!important override abstract lef generated by openlane. openlane
 generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
 2022-10-10 05:42:29 -07:00
kareem 3a81dde555 add sky130_fd_sc_hd__macro_sparecell inside gpio_control_block rtl 2022-10-10 05:24:25 -07:00
kareem 71e309a923 some rtl changes 
- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
 2022-10-10 05:13:48 -07:00
Mohamed Hosni 40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 05:08:33 -07:00
M0stafaRady 0f0a495906 merge with caravel_redesign 2022-10-10 05:04:44 -07:00
kareem 285ef6b642 reharden!: caravel 
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
 2022-10-10 04:51:05 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady 45a885caaa update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT 2022-10-10 04:34:26 -07:00
Mohamed Hosni fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 01:24:24 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni 7e5891dd9f Update mgmt_protect 2022-10-10 01:19:40 -07:00
M0stafaRady 00364eb092 Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
Mohamed Shalan 7538c8c776
Merge pull request #161 from efabless/chip_io_rework 2022-10-09 16:31:28 +02:00
M0stafaRady 1690c8e068 enhance gpio_all_o test 2022-10-09 06:07:19 -07:00
M0stafaRady 08229d6a9b Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
mo-hosni dde6e034e0 added constant_block view 2022-10-08 12:05:53 -07:00
Tim Edwards d1a3922dbb Initial commit for rework of chip_io and chip_io_alt layouts; 
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
 2022-10-08 12:05:10 -04:00
M0stafaRady e94a8e0477 add test la test 2022-10-08 06:25:26 -07:00
M0stafaRady d90001eac2 update caravel.py to disable bin 3 also 2022-10-08 01:56:41 -07:00
mo-hosni d6ca7f9091 rehardened housekeeping after rtl update, and fixed all hold and transition violations. 2022-10-07 16:59:01 -07:00
Mohamed Hosni 5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-07 16:52:16 -07:00
R. Timothy Edwards 7b271a7808
Effectively reverted the change to add spare logic blocks near each (#157) 
* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
 2022-10-07 09:28:13 -07:00
M0stafaRady 2dc29bb207 comment disabling the housekeeping at the begining of each test as it's not needed anymore 2022-10-07 07:02:58 -07:00
M0stafaRady 0f167fc041 update timeout for gpio_all_i_pd and gpio_all_i_pu 2022-10-07 07:02:09 -07:00
M0stafaRady f072e9cb2d Add gpio_all_i_pd 2022-10-07 06:41:21 -07:00
M0stafaRady 6f832589c0 merge caravel_redesign 2022-10-07 06:06:14 -07:00
M0stafaRady e1eba1d534 update gpio_all_i_pu test 2022-10-07 06:04:18 -07:00
kareem 6d1d618974 reharden!: gpio_control_block 
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations

!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
 2022-10-07 05:02:14 -07:00