add chip_io gl

~ update interactive script for chip_io.v for recent openlane
~ update config.tcl for recent openlane
~ add a verilog stub for sky130_fd_io__top_xres4v2 as
the io verilog models are not readable by yosys

openlane/chip_io/config.tcl

@@ -13,28 +13,31 @@
 # limitations under the License.
 # SPDX-License-Identifier: Apache-2.0
 
-set script_dir [file dirname [file normalize [info script]]]
 
 set ::env(DESIGN_NAME) chip_io
 set ::env(DESIGN_IS_PADFRAME) 1
 
-set ::env(STD_CELL_LIBRARY_OPT) $::env(STD_CELL_LIBRARY)
 
 set ::env(VERILOG_FILES) "\
-	$script_dir/../../verilog/rtl/defines.v\
-	$script_dir/../../verilog/rtl/pads.v\
-	$script_dir/../../verilog/rtl/mprj_io.v\
-	$script_dir/../../verilog/rtl/chip_io.v"
+	$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
+	$::env(DESIGN_DIR)/../../verilog/rtl/pads.v\
+	$::env(DESIGN_DIR)/../../verilog/rtl/mprj_io.v\
+	$::env(DESIGN_DIR)/../../verilog/rtl/chip_io.v"
+
+set ::env(VERILOG_FILES_BLACKBOX) "
+    $::env(DESIGN_DIR)/../../verilog/gl/constant_block.v
+"
 
 set ::env(USE_GPIO_PADS) 1
 
 # The removal of this line is pending the IO verilog files being parsable by yosys...
-set ::env(VERILOG_FILES_BLACKBOX) "\
-    $script_dir/../../verilog/stubs/sky130_fd_io__top_xres4v2.v\
-    $script_dir/../../verilog/stubs/sky130_fd_io__top_ground_lvc_wpad.v\
-    $script_dir/../../verilog/stubs/sky130_fd_io__top_power_lvc_wpad.v"
+#set ::env(VERILOG_FILES_BLACKBOX) "\
+#    $::env(DESIGN_DIR)/../../verilog/stubs/sky130_fd_io__top_xres4v2.v\
+#    $::env(DESIGN_DIR)/../../verilog/stubs/sky130_fd_io__top_ground_lvc_wpad.v\
+#    $::env(DESIGN_DIR)/../../verilog/stubs/sky130_fd_io__top_power_lvc_wpad.v"
 
 set ::env(GPIO_PADS_VERILOG) "\
+    $::env(DESIGN_DIR)/sky130_fd_io__top_xres4v2-stub.v
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
 
 
@@ -45,7 +48,7 @@ set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 ## Floorplan
 set ::env(FP_SIZING) absolute
 
-set fd [open "$script_dir/../chip_dimensions.txt" "r"]
+set fd [open "$::env(DESIGN_DIR)/../chip_dimensions.txt" "r"]
 set ::env(DIE_AREA) [read $fd]
 close $fd
 
@@ -53,11 +56,11 @@ close $fd
 set ::env(DIODE_INSERTION_STRATEGY) 0
 
 ## Routing
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_UNIDIRECTIONAL) 0
-set ::env(GLB_RT_ALLOW_CONGESTION) 1
-set ::env(GLB_RT_OVERFLOW_ITERS) 150
-
+#set ::env(GLB_RT_MAXLAYER) 4
+#set ::env(GLB_RT_UNIDIRECTIONAL) 0
+#set ::env(GLB_RT_ALLOW_CONGESTION) 1
+#set ::env(GLB_RT_OVERFLOW_ITERS) 150
+#
 ## LVS
 set ::env(LVS_CONNECT_BY_LABEL) 1
 

openlane/chip_io/interactive.tcl

@@ -25,7 +25,8 @@ set ::env(SYNTH_DEFINES) ""
 verilog_elaborate
 #init_floorplan
 #file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
-file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
+save_views -pnl_path $::env(CURRENT_NETLIST) -save_path $::env(CARAVEL_ROOT) 
+exit
 
 # ACTUAL CHIP INTEGRATION
 set ::env(USE_GPIO_ROUTING_LEF) 1
@@ -123,4 +124,4 @@ save_views       -lef_path $::env(magic_result_file_tag).lef \
                  -save_path $save_path \
                  -tag $::env(RUN_TAG)
 
-run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v
+run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v

openlane/chip_io/sky130_fd_io__top_xres4v2-stub.v

@@ -0,0 +1,32 @@
+module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H,  XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
+    AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
+    DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
+    ,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
+     );
+    output XRES_H_N;
+    inout AMUXBUS_A;
+    inout AMUXBUS_B;
+    inout PAD;
+    input DISABLE_PULLUP_H;
+    input ENABLE_H; 
+    input EN_VDDIO_SIG_H; 
+    input INP_SEL_H; 
+    input FILT_IN_H;
+    inout PULLUP_H;
+    input ENABLE_VDDIO;
+    input VCCD;
+    input VCCHIB;
+    input VDDA;
+    input VDDIO;
+    input VDDIO_Q;
+    input VSSA;
+    input VSSD;
+    input VSSIO;
+    input VSSIO_Q;
+    input VSWITCH;
+    inout PAD_A_ESD_H;
+    output TIE_HI_ESD;
+    output TIE_LO_ESD;
+    inout TIE_WEAK_HI_H;
+endmodule
+