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caravel
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fix errors for gate level

This commit is contained in:
M0stafaRady 2022-10-12 10:29:56 -07:00
parent 471e150167
commit e8870d6a8b
18 changed files with 127 additions and 111 deletions
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6
verilog/dv/cocotb/interfaces/caravel.py
View File

@ -58,7 +58,7 @@ class Caravel_env:
async def disable_bins(self):
for i in range(38):
if i ==3:
if i in [3,4]: #CSB and SCK
continue
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
@ -110,7 +110,7 @@ class Caravel_env:
"""drive csb signal bin E8 mprj[3]"""
async def drive_csb(self,bit):
self.drive_gpio_in((3,3),bit)
self.drive_gpio_in((2,2),0)
self.drive_gpio_in((4,4),0)
await ClockCycles(self.clk, 1)
@ -123,7 +123,7 @@ class Caravel_env:
async def release_csb(self ):
cocotb.log.info(f' [caravel] release housekeeping spi transmission')
self.release_gpio(3)
self.release_gpio(2)
self.release_gpio(4)
await ClockCycles(self.clk, 1)
"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""

176
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c
View File

@ -3,96 +3,96 @@
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
// Configure all as output except reg_mprj_io_3
clock_in_right_o_left_o_standard(0); // 18 and 19
clock_in_right_o_left_o_standard(0); // 17 and 20
clock_in_right_o_left_o_standard(0); // 16 and 21
clock_in_right_o_left_o_standard(0); // 15 and 22
clock_in_right_o_left_o_standard(0); // 14 and 23
clock_in_right_o_left_o_standard(0); // 13 and 24
clock_in_right_o_left_o_standard(0); // 12 and 25
clock_in_right_o_left_o_standard(0); // 11 and 26
clock_in_right_o_left_o_standard(0); // 10 and 27
clock_in_right_o_left_o_standard(0); // 9 and 28
clock_in_right_o_left_o_standard(0); // 8 and 29
clock_in_right_o_left_o_standard(0); // 7 and 30
clock_in_right_o_left_o_standard(0); // 6 and 31
clock_in_right_o_left_o_standard(0); // 5 and 32
clock_in_right_o_left_o_standard(0); // 4 and 33
clock_in_right_o_left_i_standard(0); // 3 and 34
clock_in_right_o_left_o_standard(0); // 2 and 35
clock_in_right_o_left_o_standard(0); // 1 and 36
clock_in_right_o_left_o_standard(0); // 0 and 37
load();
reg_debug_1 = 0xFF; // finish configuration
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
// bitbang
// Configure all as output except reg_mprj_io_3
clock_in_right_o_left_o_standard(0); // 18 and 19
clock_in_right_o_left_o_standard(0); // 17 and 20
clock_in_right_o_left_o_standard(0); // 16 and 21
clock_in_right_o_left_o_standard(0); // 15 and 22
clock_in_right_o_left_o_standard(0); // 14 and 23
clock_in_right_o_left_o_standard(0); // 13 and 24
clock_in_right_o_left_o_standard(0); // 12 and 25
clock_in_right_o_left_o_standard(0); // 11 and 26
clock_in_right_o_left_o_standard(0); // 10 and 27
clock_in_right_o_left_o_standard(0); // 9 and 28
clock_in_right_o_left_o_standard(0); // 8 and 29
clock_in_right_o_left_o_standard(0); // 7 and 30
clock_in_right_o_left_o_standard(0); // 6 and 31
clock_in_right_o_left_o_standard(0); // 5 and 32
clock_in_right_o_left_o_standard(0); // 4 and 33
clock_in_right_o_left_o_standard(0); // 3 and 34
clock_in_right_o_left_o_standard(0); // 2 and 35
clock_in_right_o_left_o_standard(0); // 1 and 36
clock_in_right_o_left_o_standard(0); // 0 and 37
load();
reg_debug_1 = 0xFF; // finish configuration
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
}

2
verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c
View File

@ -9,7 +9,7 @@ void main()
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;

13
verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c
View File

@ -9,7 +9,7 @@ void main()
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
@ -43,14 +43,15 @@ void main()
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = 0x1803;
reg_mprj_io_3 = 0x1803;
reg_mprj_io_2 = 0x1803;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// reg_mprj_io_4 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
// reg_mprj_io_3 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
// reg_mprj_io_2 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
// reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
// reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_debug_1 = 0xFF; // finish configuration
while (reg_debug_2 != 0xFF); // finish bit bang
reg_hkspi_disable = 1;
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;

20
verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
View File

@ -25,26 +25,26 @@ async def bitbang_cpu_all_o(dut):
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,0)).integer != i<<32:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
if caravelEnv.monitor_gpio((31,0)).integer != i :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000

1
verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c
View File

@ -53,5 +53,6 @@ void main(){
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

1
verilog/dv/cocotb/tests/gpio/gpio_all_i_pd_user.c
View File

@ -52,6 +52,7 @@ void main(){
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

2
verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c
View File

@ -52,6 +52,6 @@ void main(){
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

1
verilog/dv/cocotb/tests/gpio/gpio_all_i_pu_user.c
View File

@ -59,5 +59,6 @@ void main(){
reg_debug_1 = 0XAA; // configuration done
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
while (true);
}

1
verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c
View File

@ -11,4 +11,5 @@ void main(){
reg_hkspi_disable = 0;
// reg_hkspi_pll_ena =0;
reg_debug_1 =0xBB;
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

1
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c
View File

@ -5,6 +5,7 @@
void main()
{
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

1
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c
View File

@ -5,6 +5,7 @@
void main()
{
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

1
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c
View File

@ -5,6 +5,7 @@
void main()
{
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
return;
}

1
verilog/dv/cocotb/tests/logicAnalyzer/la.c
View File

@ -108,4 +108,5 @@ void main(){
reg_debug_2 = 0xFF;
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

1
verilog/dv/cocotb/tests/spi_master/spi_master_rd.c
View File

@ -176,5 +176,6 @@ void main()
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

1
verilog/dv/cocotb/tests/spi_master/spi_master_temp.c
View File

@ -107,5 +107,6 @@ void main()
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
print("adding a very very long delay because cpu produces X's when code finish and this break the simulation");
}

7
verilog/dv/cocotb/tests/uart/uart.py
View File

@ -9,6 +9,7 @@ from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from interfaces.common import Macros
bit_time_ns = 0
@ -112,7 +113,11 @@ async def uart_send_char(caravelEnv,char):
async def uart_check_char_recieved(caravelEnv,cpu):
# check cpu recieved the correct character
while True:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
if not Macros['GL']:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
else:
reg_uart_data = "1001110"
reg1 = cpu.read_debug_reg1()
cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
if reg1 == 0x1B:

2
verilog/dv/cocotb/verify_cocotb.py
View File

@ -116,7 +116,7 @@ class RunTest:
os.environ["SIM"] = self.sim_type
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vcs {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")