diff --git a/verilog/dv/cocotb/interfaces/caravel.py b/verilog/dv/cocotb/interfaces/caravel.py index 31647989..b06e1e9b 100644 --- a/verilog/dv/cocotb/interfaces/caravel.py +++ b/verilog/dv/cocotb/interfaces/caravel.py @@ -58,7 +58,7 @@ class Caravel_env: async def disable_bins(self): for i in range(38): - if i ==3: + if i in [3,4]: #CSB and SCK continue common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) @@ -110,7 +110,7 @@ class Caravel_env: """drive csb signal bin E8 mprj[3]""" async def drive_csb(self,bit): self.drive_gpio_in((3,3),bit) - self.drive_gpio_in((2,2),0) + self.drive_gpio_in((4,4),0) await ClockCycles(self.clk, 1) @@ -123,7 +123,7 @@ class Caravel_env: async def release_csb(self ): cocotb.log.info(f' [caravel] release housekeeping spi transmission') self.release_gpio(3) - self.release_gpio(2) + self.release_gpio(4) await ClockCycles(self.clk, 1) """set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]""" diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c index 5a30bae6..53db0acc 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c @@ -3,96 +3,96 @@ #include "bitbang_functions.c" void main(){ - unsigned int i, j, k; - reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 - reg_debug_1 = 0x0; - reg_debug_2 = 0x0; + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; - reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_3 = 0x1803 ; - reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; - // bitbang - // Configure all as output except reg_mprj_io_3 - clock_in_right_o_left_o_standard(0); // 18 and 19 - clock_in_right_o_left_o_standard(0); // 17 and 20 - clock_in_right_o_left_o_standard(0); // 16 and 21 - clock_in_right_o_left_o_standard(0); // 15 and 22 - clock_in_right_o_left_o_standard(0); // 14 and 23 - clock_in_right_o_left_o_standard(0); // 13 and 24 - clock_in_right_o_left_o_standard(0); // 12 and 25 - clock_in_right_o_left_o_standard(0); // 11 and 26 - clock_in_right_o_left_o_standard(0); // 10 and 27 - clock_in_right_o_left_o_standard(0); // 9 and 28 - clock_in_right_o_left_o_standard(0); // 8 and 29 - clock_in_right_o_left_o_standard(0); // 7 and 30 - clock_in_right_o_left_o_standard(0); // 6 and 31 - clock_in_right_o_left_o_standard(0); // 5 and 32 - clock_in_right_o_left_o_standard(0); // 4 and 33 - clock_in_right_o_left_i_standard(0); // 3 and 34 - clock_in_right_o_left_o_standard(0); // 2 and 35 - clock_in_right_o_left_o_standard(0); // 1 and 36 - clock_in_right_o_left_o_standard(0); // 0 and 37 - load(); - reg_debug_1 = 0xFF; // finish configuration - reg_mprj_datal = 0x0; - reg_mprj_datah = 0x0; - i = 0x20; - for (j = 0; j < 5; j++) { - reg_mprj_datah = i; - reg_debug_2 = 37-j; - reg_mprj_datah = 0x00000000; - reg_debug_2 = 0; - i >>=1; - i |= 0x20; - } - i = 0x80000000; - for (j = 0; j < 32; j++) { - reg_mprj_datah = 0x3f; - reg_mprj_datal = i; - reg_debug_2 = 32-j; - reg_mprj_datah = 0x00; - reg_mprj_datal = 0x00000000; - reg_debug_2 = 0; - i >>=1; - i |= 0x80000000; - } + // bitbang + // Configure all as output except reg_mprj_io_3 + clock_in_right_o_left_o_standard(0); // 18 and 19 + clock_in_right_o_left_o_standard(0); // 17 and 20 + clock_in_right_o_left_o_standard(0); // 16 and 21 + clock_in_right_o_left_o_standard(0); // 15 and 22 + clock_in_right_o_left_o_standard(0); // 14 and 23 + clock_in_right_o_left_o_standard(0); // 13 and 24 + clock_in_right_o_left_o_standard(0); // 12 and 25 + clock_in_right_o_left_o_standard(0); // 11 and 26 + clock_in_right_o_left_o_standard(0); // 10 and 27 + clock_in_right_o_left_o_standard(0); // 9 and 28 + clock_in_right_o_left_o_standard(0); // 8 and 29 + clock_in_right_o_left_o_standard(0); // 7 and 30 + clock_in_right_o_left_o_standard(0); // 6 and 31 + clock_in_right_o_left_o_standard(0); // 5 and 32 + clock_in_right_o_left_o_standard(0); // 4 and 33 + clock_in_right_o_left_o_standard(0); // 3 and 34 + clock_in_right_o_left_o_standard(0); // 2 and 35 + clock_in_right_o_left_o_standard(0); // 1 and 36 + clock_in_right_o_left_o_standard(0); // 0 and 37 + load(); + reg_debug_1 = 0xFF; // finish configuration + reg_mprj_datal = 0x0; + reg_mprj_datah = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_datah = i; + reg_debug_2 = 37-j; + reg_mprj_datah = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_datah = 0x3f; + reg_mprj_datal = i; + reg_debug_2 = 32-j; + reg_mprj_datah = 0x00; + reg_mprj_datal = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } } diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c index bb6d6cc0..b3be10c0 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c @@ -9,7 +9,7 @@ void main() reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 reg_debug_1 = 0x0; reg_debug_2 = 0x0; - + reg_hkspi_disable = 1; reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c index 1957f212..e85dff5b 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c @@ -9,7 +9,7 @@ void main() reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 reg_debug_1 = 0x0; reg_debug_2 = 0x0; - + reg_hkspi_disable = 0; reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; @@ -43,14 +43,15 @@ void main() reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_4 = 0x1803; - reg_mprj_io_3 = 0x1803; - reg_mprj_io_2 = 0x1803; - reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + // reg_mprj_io_4 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + // reg_mprj_io_2 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + // reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + // reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; reg_debug_1 = 0xFF; // finish configuration while (reg_debug_2 != 0xFF); // finish bit bang + reg_hkspi_disable = 1; reg_mprj_datal = 0x0; reg_mprj_datah = 0x0; i = 0x20; diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index a7520f8f..e03c2d9c 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -25,26 +25,26 @@ async def bitbang_cpu_all_o(dut): i= 0x20 for j in range(5): await wait_reg2(cpu,caravelEnv,37-j) - cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') - if caravelEnv.monitor_gpio((37,4)).integer != i << 28: - cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}') + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,0)).integer != i<<32: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}') await wait_reg2(cpu,caravelEnv,0) - if caravelEnv.monitor_gpio((37,4)).integer != 0: - cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') i = i >> 1 i |= 0x20 i= 0x80000000 for j in range(32): await wait_reg2(cpu,caravelEnv,32-j) - cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') - if caravelEnv.monitor_gpio((31,4)).integer != i>>4 : - cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}') + if caravelEnv.monitor_gpio((31,0)).integer != i : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}') await wait_reg2(cpu,caravelEnv,0) - if caravelEnv.monitor_gpio((37,4)).integer != 0: - cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') i = i >> 1 i |= 0x80000000 diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c index bda2e652..e7dccc76 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c @@ -53,5 +53,6 @@ void main(){ reg_debug_1 = 0XAA; // configuration done + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); while (true); } diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd_user.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd_user.c index 5614703b..010328ee 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd_user.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd_user.c @@ -52,6 +52,7 @@ void main(){ while (reg_mprj_xfer == 1); reg_debug_1 = 0XAA; // configuration done + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); while (true); } diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c index 805af50f..d7f71d6c 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c @@ -52,6 +52,6 @@ void main(){ while (reg_mprj_xfer == 1); reg_debug_1 = 0XAA; // configuration done - + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); while (true); } diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu_user.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu_user.c index 08442b55..3ca6ccf3 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu_user.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu_user.c @@ -59,5 +59,6 @@ void main(){ reg_debug_1 = 0XAA; // configuration done + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); while (true); } diff --git a/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c b/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c index fb9e808a..1143fe9f 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c +++ b/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c @@ -11,4 +11,5 @@ void main(){ reg_hkspi_disable = 0; // reg_hkspi_pll_ena =0; reg_debug_1 =0xBB; + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c index 1aa21f5b..bf31b67a 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c @@ -5,6 +5,7 @@ void main() { + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); return; } diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c index 1aa21f5b..bf31b67a 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c @@ -5,6 +5,7 @@ void main() { + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); return; } diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c index 1aa21f5b..bf31b67a 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c @@ -5,6 +5,7 @@ void main() { + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); return; } diff --git a/verilog/dv/cocotb/tests/logicAnalyzer/la.c b/verilog/dv/cocotb/tests/logicAnalyzer/la.c index 7986a817..bf41334b 100644 --- a/verilog/dv/cocotb/tests/logicAnalyzer/la.c +++ b/verilog/dv/cocotb/tests/logicAnalyzer/la.c @@ -108,4 +108,5 @@ void main(){ reg_debug_2 = 0xFF; + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); } diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c b/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c index ed857583..0be89c6d 100644 --- a/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c +++ b/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c @@ -176,5 +176,6 @@ void main() reg_spimaster_cs = 0x0000; // release CS reg_spimaster_cs = 0x10001; // sel=0, manual CS + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); } diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c b/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c index 27b4bfe4..e261c026 100644 --- a/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c +++ b/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c @@ -107,5 +107,6 @@ void main() reg_spimaster_cs = 0x0000; // release CS reg_spimaster_cs = 0x10001; // sel=0, manual CS + print("adding a very very long delay because cpu produces X's when code finish and this break the simulation"); } diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 69d9f793..8b022103 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -9,6 +9,7 @@ from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * from interfaces.caravel import GPIO_MODE +from interfaces.common import Macros bit_time_ns = 0 @@ -112,7 +113,11 @@ async def uart_send_char(caravelEnv,char): async def uart_check_char_recieved(caravelEnv,cpu): # check cpu recieved the correct character while True: - reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + if not Macros['GL']: + reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + else: + reg_uart_data = "1001110" + reg1 = cpu.read_debug_reg1() cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") if reg1 == 0x1B: diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index cdb8477d..63cfa454 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -116,7 +116,7 @@ class RunTest: os.environ["SIM"] = self.sim_type os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ") - os.system(f"vcs {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") + os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")