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230 Commits

Author SHA1 Message Date
M0stafaRady 6f832589c0 merge caravel_redesign 2022-10-07 06:06:14 -07:00
M0stafaRady e1eba1d534 update gpio_all_i_pu test 2022-10-07 06:04:18 -07:00
kareem 6d1d618974 reharden!: gpio_control_block 
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations

!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
 2022-10-07 05:02:14 -07:00
Jeff DiCorpo 0e3badac29
152 add pass thru for clock and reset (#154) 
* update caravel.v and caravan.v for clock and reset passthru.

* Apply automatic changes to Manifest and README.rst

* Apply automatic changes to Manifest and README.rst

Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu>
Co-authored-by: shalan <shalan@users.noreply.github.com>
 2022-10-07 01:36:26 -07:00
R. Timothy Edwards cfbe353290
Added spare logic blocks for GPIO (#153) 
* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
 2022-10-07 01:24:01 -07:00
R. Timothy Edwards be25ae7476
Remove SRAM read-only interface (#151) 
* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
 2022-10-07 01:23:07 -07:00
Tim Edwards a07d0d5dac Fixed one small error in the housekeeping module that was surfaced 
by the pull-up/pull-down testbench.
 2022-10-06 15:57:45 -04:00
M0stafaRady 3eb0b11380 update verify_cocotb.py to remove vcs generate files 2022-10-06 11:18:48 -07:00
M0stafaRady 4f483adb36 update hk_regs_wr_wb_cpu test to include all house keeping regs 2022-10-06 11:16:07 -07:00
M0stafaRady 7e407e1155 Add test hk_disable 2022-10-06 10:12:12 -07:00
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
R. Timothy Edwards 611c320eed
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-06 11:39:22 -04:00
M0stafaRady fb34d9a541 update input tests to cover the gpio from 32 to 37 2022-10-06 05:32:46 -07:00
M0stafaRady a69185dfca update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:44:55 -07:00
M0stafaRady 1bc78c4eea update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:43:02 -07:00
M0stafaRady 8e72d5e13e Add test uart_loopback 2022-10-06 03:12:44 -07:00
M0stafaRady 6830c79ae8 fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); 2022-10-06 02:14:59 -07:00
Tim Edwards 42805f767e Removed some references to mgmt_soc_litex files that had been added 
to caravel_netlists.v when attempting to determine if the
verification testbenches could be run from caravel referencing
caravel_mgmt_soc_litex instead of the other way around.  This file
has been reverted back to its original form.
 2022-10-05 21:43:29 -04:00
Tim Edwards e2556cc11b Removed the SPARE_LOGIC_BLOCK ifdef...endif from around the spare 
logic in caravel.v and caravan.v.  These had been added to the
caravel_stanford branch because the spare logic blocks are not
usefully synthesizable.
 2022-10-05 21:37:55 -04:00
R. Timothy Edwards 268f5dd7e9
Merge branch 'caravel_redesign' into fix_direct_power_connections 2022-10-05 21:33:17 -04:00
Tim Edwards 83f58cbe65 Added back a "genvar" statement that was deleted from housekeeping 
along with an unused block, but was needed elsewhere.
 2022-10-05 21:05:58 -04:00
Tim Edwards 72341326e2 Corrected a typo in the definition of the mgmt_io_oeb vector in 
caravel.v, which should be the same as mgmt_io_in and mgmt_io_out
and should equal the number of user I/O pads (38).
 2022-10-05 20:52:21 -04:00
Tim Edwards f5a9d4677e Revert "Implemented fix from early issue #16. Finally decided to pull the" 
This reverts commit 577cc12fe0.

Reverting the change from issue #16.  After some discussion, it has
been decided that it is up to the user to implement the pull-up and
pull-down modes correctly by setting the output enable and driving
the output to the appropriate value.  Note that this should be well
documented, if by nothing else than a validation testbench that
excercises a user pull-up and pull-down input mode.
 2022-10-05 20:46:03 -04:00
M0stafaRady a6e7b46128 delete reading from uart register in uart_rx test 2022-10-05 15:07:38 -07:00
M0stafaRady 78613c95cc increase timeout for uart_rx and add uart_ev_pending_write 2022-10-05 15:02:07 -07:00
M0stafaRady 8e21a2f722 Add test pll 2022-10-05 13:58:36 -07:00
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
Tim Edwards 577cc12fe0 Implemented fix from early issue #16. Finally decided to pull the 
trigger on this one in the hopes that it helps prevent user error
in implementing input pull-up and pull-down on GPIO pins.
 2022-10-05 14:13:57 -04:00
M0stafaRady fca511f306 change docker mount from the home to repo directory and pdk root 2022-10-05 11:10:24 -07:00
M0stafaRady a741ec4525 Merge branch 'caravel_redesign' into cocotb 2022-10-05 08:24:30 -07:00
M0stafaRady 4610f6b004 Add trial of test gpio_all_i_pu still not work 2022-10-05 08:22:51 -07:00
R. Timothy Edwards 69240123c0
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-05 10:18:35 -04:00
Tim Edwards 7276623d3c Corrected the pull-up definition and revised the CSB definition to 
match the corrected defintions (namely, pull-up is configuration
0x0801, and pull-down is configuration 0x0c01).
 2022-10-05 10:02:24 -04:00
M0stafaRady 650483eaa2 fix some typos on mgmt_protect 2022-10-05 03:27:46 -07:00
M0stafaRady 4b762da8e6 merge with caravel_redesign 2022-10-04 10:57:56 -07:00
M0stafaRady e2b345dcbb Add new test user_pass_thru_rd 2022-10-04 10:55:53 -07:00
M0stafaRady 0bd6c73b7b update verify_cocotb script to merge coverage 2022-10-04 10:47:07 -07:00
M0stafaRady 5e523bce5b Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
Mohamed Shalan 599ee23610
Merge pull request #137 from efabless/fix_caravan_gpio_default 
Changed gpio_defaults_block_14 to gpio_defaults_block_25
 2022-10-04 19:03:46 +02:00
Mohamed Shalan df08268f8a
Merge pull request #142 from efabless/remove_mgmt_protect_tristates 
Remove mgmt protect tristates
 2022-10-04 12:55:34 +02:00
M0stafaRady 11330823b7 Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
R. Timothy Edwards cda2c87ae8
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-03 17:39:24 -04:00
Tim Edwards de9605a01b Modified the mgmt_protect module to change the tristate outputs to 
zero level outputs when the user project area is powered down.
That allows the synthesis tools to buffer these outputs.  The
protection from floating inputs is left as-is, but all logic that
was unnecessary to be specified by gate instances has been changed
to RTL.  This leaves only a handful of signals (logic analyzer input,
user IRQ, and wishbone data out and acknowledge out) to be handled
by explicit logic gate instances.
 2022-10-03 16:11:02 -04:00
M0stafaRady ef9c2e408b fix bug at IRQ_uart 2022-10-03 09:49:51 -07:00
M0stafaRady 37244a2514 add 3 regressions r_rtl , r_gl,r_sdf 2022-10-03 09:01:08 -07:00
M0stafaRady c4859c8789 fix bug at reading from debug registers 2022-10-03 08:57:23 -07:00
M0stafaRady e81416bb51 add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
M0stafaRady e945c3b882 fix bug at mgmt_gpio_out by increasing the number of phases 2022-10-03 05:45:55 -07:00
M0stafaRady 79f26f6b38 add new test spi_master_rd 2022-10-03 05:36:36 -07:00
M0stafaRady 55f6f56921 update verify_cocotb script to run iverilog inside a docker 2022-10-03 01:56:08 -07:00