tangxifan
|
8c1158fc5c
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
tangxifan
|
4171a674b1
|
refactored clb2clb direct connects for cross-column/row
|
2019-10-17 23:06:59 -06:00 |
|
tangxifan
|
190449c06f
|
refactoring top-level module with clb2clb direct connection
|
2019-10-17 17:29:04 -06:00 |
|
tangxifan
|
c9d8311a93
|
bug fixing for grid-gsb connections in top module when using compact routing
|
2019-10-15 18:00:55 -06:00 |
|
tangxifan
|
6a13120208
|
rename grid modules to be clear
|
2019-10-15 16:28:46 -06:00 |
|
tangxifan
|
071757dc52
|
add module nets to connect grids and sbs
|
2019-10-15 16:08:51 -06:00 |
|
tangxifan
|
f779ad7ecf
|
bug fixing for global and gpio port wiring; start refactoring top-level module
|
2019-10-14 15:53:04 -06:00 |
|
tangxifan
|
6793c67c8d
|
refactored pb_type and grid Verilog generation
|
2019-10-13 21:07:30 -06:00 |
|
tangxifan
|
b581399761
|
add memory ports and nets to intermediate pb_types
|
2019-10-13 17:45:32 -06:00 |
|
tangxifan
|
cab4bd6807
|
add gpio ports to pb_type modules
|
2019-10-13 16:23:22 -06:00 |
|
tangxifan
|
d1948c82eb
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
tangxifan
|
b3ca0d32a4
|
remove configuration bus naming dependency on SRAM circuit models
|
2019-10-11 19:47:36 -06:00 |
|
tangxifan
|
73a5977e0d
|
Debugged Verilog generation for primitive pb_types
|
2019-10-11 18:00:37 -06:00 |
|
tangxifan
|
50f7d1eae3
|
bug fixing in Verilog port merging and instanciation
|
2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
|
refactorint net addition for configuration signals in module graph
|
2019-10-11 13:07:14 -06:00 |
|
tangxifan
|
c9950162d1
|
start plug in new Verilog writer. Start debugging
|
2019-10-10 22:02:46 -06:00 |
|
tangxifan
|
1f650aac73
|
add local direct connection Verilog code generation
|
2019-10-10 20:54:31 -06:00 |
|
tangxifan
|
f2b3341d87
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
|
developing verilog writer for modules
|
2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
edad988ebb
|
add net accessor and mutators to module manager
|
2019-10-09 21:14:30 -06:00 |
|
tangxifan
|
557d8b60f3
|
start implementing module graph-based connection
|
2019-10-09 20:30:16 -06:00 |
|
tangxifan
|
9cb6e64ab3
|
refactoring instanciation inside primitive pb_type Verilog module
|
2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
|
2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
ea2942640e
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
|
2019-10-08 12:10:26 -06:00 |
|
tangxifan
|
173b886314
|
add module name generation for pb_types
|
2019-10-07 21:09:54 -06:00 |
|
tangxifan
|
3ca6f08aa4
|
start refactoring physical block Verilog generation
|
2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
|
refactored shared config bits calculation
|
2019-10-06 16:57:53 -06:00 |
|
tangxifan
|
393f0b0ac3
|
align formal verification port inside refactored routing blocks
|
2019-10-05 21:16:48 -06:00 |
|
tangxifan
|
c920047ee8
|
refactored Verilog generation for connection blocks
|
2019-10-05 18:14:23 -06:00 |
|
tangxifan
|
2d7e8d9811
|
add check codes for memory buses
|
2019-10-05 11:07:26 -06:00 |
|
tangxifan
|
6b301d9f44
|
Merge branch 'dev' into refactoring
|
2019-10-04 22:47:29 -06:00 |
|
tangxifan
|
b905c0c68c
|
refactored memory module Verilog generation for scan-chains
|
2019-10-04 22:45:45 -06:00 |
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
633a12ee08
|
Buggy version but need help on debugging
|
2019-10-01 14:49:42 -06:00 |
|
tangxifan
|
b082e60c10
|
start refactoring instanciation of memory modules
|
2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
|
simplify the local wire generation for ccffs
|
2019-09-28 21:36:56 -06:00 |
|
tangxifan
|
1983e56557
|
make local configuration bus generation more general
|
2019-09-28 21:02:14 -06:00 |
|
tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
|
2019-09-27 23:10:43 -06:00 |
|
tangxifan
|
4da5035627
|
Connect CCFFs in a chain in a Verilog module
|
2019-09-27 20:50:12 -06:00 |
|
tangxifan
|
1e187f3d15
|
start adding memory circuit to Switch blocks
|
2019-09-27 18:08:37 -06:00 |
|
tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
|
2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
8ccf681749
|
Merge branch 'dev' into refactoring
|
2019-09-26 21:00:19 -06:00 |
|
tangxifan
|
f0589cc2cf
|
refactoring mux Verilog generation for switch blocks
|
2019-09-26 20:59:19 -06:00 |
AurelienUoU
|
3b13c959f3
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
AurelienUoU
|
c4449b667f
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-26 11:34:59 -06:00 |
|
AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
tangxifan
|
ea0da49e04
|
Merge branch 'dev' into refactoring
|
2019-09-25 21:06:06 -06:00 |
|
tangxifan
|
5bb40e7f74
|
refactored local wire generation for Switch block
|
2019-09-25 21:05:02 -06:00 |
|
AurelienUoU
|
e5faeb1400
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-25 16:50:53 -06:00 |
|
AurelienUoU
|
a35e2936b2
|
Fix verilog generation for direct connexion from directlist
|
2019-09-25 16:44:00 -06:00 |
|
tangxifan
|
2b0e2615fa
|
refactored sram port addition to module manager
|
2019-09-25 16:09:58 -06:00 |
|
tangxifan
|
c911f15a67
|
add formal verification port to SB Verilog generation
|
2019-09-23 21:15:45 -06:00 |
|
tangxifan
|
e1742b68ef
|
add pre-processing flag support for module manager
|
2019-09-23 20:25:53 -06:00 |
|
tangxifan
|
d2ddbc19a3
|
refactoring the reserved sram port generation
|
2019-09-22 16:38:16 -06:00 |
|
tangxifan
|
2c4372c506
|
add reserved BLB/WL port naming
|
2019-09-22 12:16:43 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
tangxifan
|
d83cad7c2e
|
refactoring Verilog generation for routing channels
|
2019-09-16 17:35:51 -06:00 |
|
Baudouin Chauviere
|
d5ebe66ad9
|
Bug fix
|
2019-09-16 10:57:52 -06:00 |
|
tangxifan
|
29e80d157c
|
Start developing BitstreamContext
|
2019-09-13 21:27:47 -06:00 |
|
tangxifan
|
e64cfc5852
|
start refactoring memory decoders
|
2019-09-13 20:58:55 -06:00 |
|
tangxifan
|
009c0d63b5
|
refactored the memory bank. Ready to plug-in the test
|
2019-09-13 15:05:31 -06:00 |
|
tangxifan
|
99c30fa7dd
|
keep refactoring the memory Verilog generation
|
2019-09-13 14:02:04 -06:00 |
|
tangxifan
|
2b829238b5
|
refactored wire Verilog generation
|
2019-09-12 20:49:02 -06:00 |
|
tangxifan
|
62853c092f
|
refactoring local encoders. Ready to plug in
|
2019-09-10 15:16:29 -06:00 |
|
tangxifan
|
e623c19055
|
implementing mux Verilog generation. Bugs detected, fixing ongoing
|
2019-09-04 23:54:53 -06:00 |
|
tangxifan
|
4d183a3fe4
|
start developing mux Verilog module generation
|
2019-09-03 16:59:03 -06:00 |
|
tangxifan
|
a8c803f08f
|
try to fix bugs in explicit port mapping
|
2019-09-02 16:37:43 -06:00 |
|
tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
|
tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |
|
tangxifan
|
ad06e9c98c
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
|
2019-08-23 18:41:16 -06:00 |
|
tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
37a092e885
|
add recursive global port searching for circuit library
|
2019-08-23 16:36:30 -06:00 |
|
tangxifan
|
931b042750
|
refactoring module manager
|
2019-08-23 12:52:01 -06:00 |
|
tangxifan
|
732e24767f
|
developing module manager
|
2019-08-22 23:49:35 -06:00 |
|
tangxifan
|
d8eb9866a0
|
refactored gate verilog generation
|
2019-08-21 18:49:48 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
5ece7ab6d0
|
start refactoring the bitstream part using spice_models
|
2019-08-16 15:58:14 -06:00 |
|
tangxifan
|
4eb046760b
|
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
|
2019-08-15 21:57:59 -06:00 |
|
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
|
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
|
2019-07-14 13:49:20 -06:00 |
|
tangxifan
|
4c6e245885
|
speed-up the unique routing process
|
2019-07-14 12:22:00 -06:00 |
|
tangxifan
|
b690e702f6
|
adding more info to show the progress bar in backannotating GSBs
|
2019-07-13 19:53:44 -06:00 |
|
tangxifan
|
aa4cd850ae
|
try to optimize the runtime of routing uniqueness detection
|
2019-07-13 18:10:34 -06:00 |