26b1e48723
[Engine] Merge BL/WLs in the Grid/CB/SB modules
2021-09-15 11:27:55 -07:00
4af6413c97
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
2021-09-10 17:03:44 -07:00
ba1e277dc9
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
2021-09-10 15:05:46 -07:00
b787c4e100
[Engine] Register QL memory bank as a legal protocol
2021-09-09 15:06:51 -07:00
6f09f5f7ad
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
2021-09-05 21:25:58 -07:00
1085e468e2
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
2021-09-05 20:45:56 -07:00
fed975c52a
[Tool] Add postfix removal support in write_io_mapping command
2021-06-18 16:13:50 -06:00
366dcff75d
[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
2021-06-07 21:49:31 -06:00
ba75c18378
[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
2021-06-07 17:40:07 -06:00
1a5902ca74
[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
2021-06-07 14:32:56 -06:00
af298de121
[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
2021-06-07 13:53:32 -06:00
d644b8f22d
[Tool] Support external bitstream file when generating full testbench for frame-based decoder
2021-06-07 11:55:11 -06:00
618b04568f
[Tool] Remove unnecessary new line in bitstream file
2021-06-04 20:07:42 -06:00
cf7addb1a6
[Tool] Add heads to bitstream plain text file
2021-06-04 19:48:48 -06:00
70fb3a85dc
[Tool] Patch fast configuration in bitstream writing
2021-06-04 17:23:10 -06:00
061f832429
[Tool] Enable fast configuration when writing fabric bitstream
2021-06-04 16:23:40 -06:00
8728fd9561
[Tool] Typo fix to resolve clang errors
2021-04-27 15:06:07 -06:00
c5d36757c6
[Tool] Fix typo in io mapping writing
2021-04-27 14:39:57 -06:00
43c1e052ef
[Tool] Add a writer to output I/O mapping information to XML files
2021-04-27 14:30:16 -06:00
0aec30bac6
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
2021-04-19 15:53:33 -06:00
7c6e000be8
[Tool] bug fix
2021-04-10 15:36:02 -06:00
03b68a1fdd
[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
2021-04-10 15:25:39 -06:00
934918d9c0
[Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions
2021-04-10 15:06:53 -06:00
d877a02534
[Tool] Patch the extended bitstream setting support on mode-select bits
2021-03-10 21:28:09 -07:00
85640a7403
[Tool] Extend bitstream setting to support mode bits overload from eblif file
2021-03-10 20:45:48 -07:00
6a0f4f354f
[Tool] Support superLUT circuit model in core engine
2021-02-09 20:23:05 -07:00
0c409b5bcc
[Tool] Add bitstream annotation support
2021-02-01 20:49:36 -07:00
9a441fa5cc
[Tool] Upgrade openfpga to support extended global tile port definition
2021-01-09 18:47:12 -07:00
5be9e9b736
[Tool] Adapted tools to support I/O in center grid
2020-12-04 18:50:13 -07:00
ba0120bd76
[Tool] Remove the limitation on requiring Qb ports for CCFF
2020-11-06 11:10:04 -07:00
4a2874b2bc
[Tool] Refactor the codes for walking through io blocks
2020-11-03 13:21:50 -07:00
6b25cf720d
[Tool] Comment on the memory efficiency on fabric bitstream address storage
2020-10-30 22:09:48 -06:00
b78f8bec16
[Tool] Bug fixed for multi-region configuration frame
2020-10-30 21:19:20 -06:00
5bcd559851
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
2020-10-30 17:29:04 -06:00
0d77916041
[Tool] Support multi-region frame-based configuration protocol
2020-10-30 10:43:11 -06:00
8ef6ae32fb
[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
2020-10-29 17:35:55 -06:00
987eccf586
[Tool] Bug fix in multi-region memory bank; Basic test passed
2020-10-29 16:26:45 -06:00
448e88645a
[Tool] Support multiple memory banks in top-level module
2020-10-29 12:42:03 -06:00
e0d7bcfa11
[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
2020-09-29 12:49:32 -06:00
e988e35f81
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
2020-09-29 12:22:10 -06:00
180d72f3e5
[Tool] Add regions to fabric bitstream
2020-09-28 21:04:08 -06:00
9a7364c6e6
bug fix in fabric bitstream XML syntax
2020-07-27 19:22:36 -06:00
35af0dd676
streamline fabric bitstream file format
2020-07-27 16:34:43 -06:00
8dd26094b8
add root node to fabric bitstream XML file format
2020-07-27 15:31:08 -06:00
d68e77f322
Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
2020-07-27 14:16:33 -06:00
e09eddab43
add width syntex to the fabric bitstream file format
2020-07-27 13:54:23 -06:00
80e982fb39
minor file format fix in fabric bitstream XML
2020-07-26 21:35:48 -06:00
b3ad04fd1e
minor file format fix in fabric bitstream XML
2020-07-26 21:33:47 -06:00
861e346830
minor bug fix in fabric bitstream XML writer
2020-07-26 21:31:08 -06:00
92d2d2d849
add fabric bitstream XML writer
2020-07-26 21:00:57 -06:00
62fd0947f5
using a unified string to replace multi net names to save memory of bitstream database
2020-07-08 16:28:20 -06:00
033c92c365
precisely reserve memory for child blocks in bitstream manager
2020-07-03 22:47:21 -06:00
46f038c829
bug fix in grid config block allocation
2020-07-03 20:46:04 -06:00
f040fc78a9
now reserve blocks in bitstream manager can accurately capture the size
2020-07-03 20:06:12 -06:00
8067a13346
bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
2020-07-03 15:56:20 -06:00
2a9377b3f4
use encoded address in storage of fabric bitstream to save memory
2020-07-03 15:12:29 -06:00
70d9678578
reserve child block in bistream manager
2020-07-03 14:04:10 -06:00
2783fda344
use index range instead of vector for block bitstream
2020-07-03 11:42:38 -06:00
6ea857ae6c
use fast method to inquire number of bits and blocks in bitstream databases
2020-07-03 10:55:25 -06:00
7ca1a5bdc1
Fabric bitstream now allocates vectors in conditions for memory efficiency
2020-07-03 10:17:03 -06:00
8a45e48a1c
minor fix
2020-07-02 22:27:48 -06:00
246b4d5ac6
reserve block bits to save memory
2020-07-02 21:52:32 -06:00
dee4be96af
reserve all the input/output net storage in bitstream manager
2020-07-02 19:17:34 -06:00
81c9fcb7c0
bug fix when optimizing the fabric bitstream data structure
2020-07-02 16:41:32 -06:00
9608cefa86
remove id vector in fabric bitstream database and replace with more memory efficient implementation
2020-07-02 16:08:50 -06:00
9f19c36a89
use char in fabric bitstream to save memory footprint
2020-07-02 15:56:50 -06:00
405824081b
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
2020-07-02 15:28:52 -06:00
b85af57971
optimizing fabric bitsteream memory footprint
2020-07-02 12:39:18 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
4f7e8020a8
minor fix on the format of arch bitstream writer
2020-06-17 00:08:28 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
3c10af7f2b
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
2020-06-11 19:31:14 -06:00
5368485bd6
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
2020-06-11 19:31:14 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
51e1559352
add fabric bitstream support for memory bank configuration protocol
2020-06-11 19:31:13 -06:00
8298bbff78
bug fixed in the fabric bitstream for frame-based configurable memories.
2020-06-11 19:31:10 -06:00
65df309419
bug fixing for frame-based configuration protocol and rename some naming function to be generic
2020-06-11 19:31:10 -06:00
cff5b5cfc1
break the configuration testbench. This commit is to spot which modification leads to the problem
2020-06-11 19:31:10 -06:00
85921dcc05
add fabric bitstream builder for frame-based configuration protocol
2020-06-11 19:31:10 -06:00
4a0e1cd908
add fabric bitstream data structure and deploy it to Verilog testbench generation
2020-06-11 19:31:10 -06:00
8c14cced84
start improve fabric bitstream database to support frame-based configuration protocol
2020-06-11 19:31:09 -06:00
d325bede68
add fabric bitstream writer
2020-04-21 12:02:10 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
b80e26e711
update bitstream generator to use sorted edges
2020-03-08 15:36:47 -06:00
3807a940f4
fixed critical bugs in bitstream generation and now we pass microbenchmarks
2020-02-28 16:45:50 -07:00
410dcf6ab6
debugged LUT bitstream
2020-02-26 11:42:18 -07:00
a26d31b87f
make write bitstream online
2020-02-26 11:09:23 -07:00
759758421d
found the bug in physical pb mode bits and fixed
2020-02-25 23:45:49 -07:00
075264e3e3
debugging LUT bitstream generation
2020-02-25 23:29:16 -07:00
2c44c70557
bring pb interconnection bitstream generation online
2020-02-25 00:28:06 -07:00
04c69d30c2
start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
2020-02-24 19:38:02 -07:00
712eeb1340
bring bitstream generator for routing modules online
2020-02-23 22:09:46 -07:00
86c7c24701
add fabric bitstream generation online
2020-02-23 20:58:17 -07:00
8723007f68
Bring mux bitstream generation online
2020-02-23 20:53:24 -07:00
51439ba3b4
add bitstream writer to be integrated
2020-02-23 20:40:18 -07:00
2d17395e13
start integrating fpga_bitstream. Bring data structures online
2020-02-22 23:04:42 -07:00
tangxifan