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OpenFPGA
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6,506 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

150 Commits

Author SHA1 Message Date
tangxifan c2066cc63c [core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules 2023-07-27 13:33:23 -07:00
tangxifan 6ecbbb3a94 [core] fixed a bug in fabric bitgen due to tile modules 2023-07-25 14:49:12 -07:00
tangxifan 95a32628ab [core] fixed the bug in arch bitgen due to the tile modules 2023-07-25 14:15:15 -07:00
tangxifan b2d1d1b6bd [core] fixed a bug on fpga bitstream when supporting fpga_core 2023-06-19 14:40:38 -07:00
tangxifan 63ee0c980e [core] fixed some bugs 2023-06-18 22:12:54 -07:00
tangxifan d9499f2b40 [core] now fpga bitstream supports the wrapper module 2023-06-18 21:58:36 -07:00
tangxifan ee59bdb675 [core] code format 2023-06-07 18:55:34 -07:00
tangxifan 327f7f4dab [core] now adapt to latest API of DeviceGrid 2023-06-07 18:54:48 -07:00
tangxifan 550e68c68b [core] fixed a bug: node_fan_in seems buggy 2023-03-06 22:26:27 -08:00
tangxifan 45107bf14f [core] debugging 2023-03-06 21:48:19 -08:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan e19ca1c6d1 [engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb 2022-09-19 18:49:54 -07:00
tangxifan 90ddd2ce32 [engine] now get incoming edges for IPINs only from GSB 2022-09-19 14:02:13 -07:00
tangxifan 9e1abf5898
Merge branch 'master' into vtr_upgrade 2022-09-01 21:39:14 -07:00
tangxifan 001367ea41 [engine] syntax 2022-09-01 16:40:17 -07:00
tangxifan 1f5e4d4215 [engine] update fabric bitstream implementation 2022-09-01 16:29:42 -07:00
tangxifan ea6f609181 [engine] fixing a bug in fabric bitstream encoding 2022-09-01 16:28:17 -07:00
tangxifan 10cefebca8 [engine] fixing bugs on using subtile index 2022-08-23 11:00:23 -07:00
tangxifan e0ae851e28 [engine] correcting compilation errors due to vpr upgrade 2022-08-17 16:25:12 -07:00
tangxifan 3c12810ad9 [engine] debugging 2022-08-17 14:37:13 -07:00
tangxifan 8f1aac885e [engine] fixing mismatches in APIs 2022-08-17 14:19:02 -07:00
tangxifan 0c329866da [engine] Use RRGraphView in openfpga source codes 2022-08-16 16:48:32 -07:00
tangxifan a7e87b9432 [FPGA-Bitstream] note limitations 2022-05-25 18:38:01 +08:00
tangxifan ffac5a66e1 [FPGA-Bitstream] Now encode address bits to save memory in bitstream database 2022-05-25 17:45:08 +08:00
tangxifan bf1a81fbb5 [FPGA-bitstream] add timer to computing intensive functions 2022-05-25 14:52:32 +08:00
tangxifan 6171abdf95 [FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats 2022-03-29 19:41:15 +08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
nadeemyaseen-rs dbe8616837 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-12-23 00:00:22 +05:00
Tarachand Pagarani 02e4ae9740 allow bitstream setting on hard blocks 2021-12-07 03:42:22 -08:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan ad54c8547e [FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files 2021-10-05 18:54:02 -07:00
tangxifan fdd75c4ec8 [FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks 2021-10-05 17:54:07 -07:00
tangxifan 9e5debabe1 [FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks 2021-10-01 16:23:38 -07:00
tangxifan 4f7ab01bf5 [FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately 2021-10-01 15:47:13 -07:00
tangxifan 96828e456a [FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong 2021-09-30 22:07:46 -07:00
tangxifan 33972fc0ec [FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers 2021-09-30 21:05:41 -07:00
tangxifan 4526133089 [FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers 2021-09-30 17:01:02 -07:00
tangxifan 43c569b612 [FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object 2021-09-30 14:47:21 -07:00
tangxifan 4d8019b7c1 [FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank 2021-09-29 22:32:45 -07:00
tangxifan 33e9b27cb8 [Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs 2021-09-25 20:22:27 -07:00
tangxifan 3cf31f1565 [Engine] Fixed bugs 2021-09-25 18:22:55 -07:00
tangxifan 386812777c [FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs 2021-09-25 12:49:32 -07:00
tangxifan 1a2a2a6e63 [FPGA-Bitstream] Relax fabric bitstream address check 2021-09-25 12:03:33 -07:00
tangxifan 8b72447dad [FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs 2021-09-24 18:07:07 -07:00
tangxifan a49e3fe57a [FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank 2021-09-24 16:30:18 -07:00
tangxifan 2de4a460a8 [Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator 2021-09-24 15:15:32 -07:00
tangxifan 962acda810 [Engine] Bug fix in fabric key generation when computing configurable children 2021-09-22 11:09:46 -07:00
tangxifan f2aa31ddb1 [FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank 2021-09-15 13:45:30 -07:00