Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
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Ganesh Gore
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1e243650b9
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Added option to copy example projects
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2022-05-03 14:06:16 -06:00 |
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Ganesh Gore
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21c3dbf611
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Added regression for template project
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2022-05-02 23:23:45 -06:00 |
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Ganesh Gore
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9891e42f7a
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Added template task
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2022-05-02 11:49:16 -06:00 |
tangxifan
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9bd66d531e
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[Test] Deploy the new test case to basic regression tests
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2022-04-13 16:06:27 +08:00 |
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tangxifan
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efc25aa66e
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[Script] Fixed a bug in wrong paths
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2022-04-13 16:04:33 +08:00 |
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tangxifan
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5beefda3bd
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[Test] Add a new test case to validate the fix_pins option
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2022-04-13 15:55:21 +08:00 |
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tangxifan
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576b9c2d8f
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[Script] Disable SDC writer in multiclock examples
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2022-03-20 11:05:29 +08:00 |
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tangxifan
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3e3a65223c
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[Test] Deploy new test case to basic regression tests
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2022-03-20 11:04:07 +08:00 |
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tangxifan
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f8845f7d3a
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[Test] Add a test case to validate separated clock pins in global port
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2022-03-20 11:02:07 +08:00 |
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tangxifan
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c8da85cc24
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[Doc] Update naming convention for OpenFPGA architecture files
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2022-03-20 10:51:55 +08:00 |
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tangxifan
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a1e2d9c864
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[Arch] Add a new example openfpga arch where clock ports are independent
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2022-03-20 10:50:31 +08:00 |
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tangxifan
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9f7a182433
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[Arch] Typo
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2022-02-24 09:51:26 -08:00 |
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tangxifan
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fdaf97e60d
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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tangxifan
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fcaff28e24
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[HDL] Add a new IO cell with config_done support
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2022-02-24 09:46:55 -08:00 |
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tangxifan
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a615c9d4e3
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[Test] Rename test cases
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2022-02-24 09:43:41 -08:00 |
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tangxifan
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e443a4567d
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[Arch] Typo
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2022-02-23 22:09:26 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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cf31879b20
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[Test] Deploy new test to basic regression tests
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2022-02-23 16:03:56 -08:00 |
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tangxifan
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245c7b1e45
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[Test] Add a new test case to validate config enable signal in preconfigured testbenches
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2022-02-23 16:02:00 -08:00 |
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tangxifan
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e33ba667e4
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[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
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f30de1085c
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[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
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b4202f52b4
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[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
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785bb1633d
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[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
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7645d5332d
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[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
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68644ea0f6
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[Test] Add the new test to basic regression tests
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2022-02-18 15:44:07 -08:00 |
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tangxifan
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f0ce1e79a3
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[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
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fe9e0ff977
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[Test] Add the new test to basic regression tests
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2022-02-18 15:38:53 -08:00 |
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tangxifan
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c897a64ad5
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[Script] Add a new example script to test full testbenches using bus group features
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2022-02-18 15:37:42 -08:00 |
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tangxifan
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223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
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85c893c94c
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[Test] Add new test to basic regression tests
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2022-02-18 15:30:08 -08:00 |
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tangxifan
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5ab84e1861
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[Test] Add a new test for bus group
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2022-02-18 15:29:33 -08:00 |
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tangxifan
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b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
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2022-02-18 15:02:08 -08:00 |
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tangxifan
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36543f7f2f
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[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
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tangxifan
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8ba3d06392
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[Test] Fixed bugs in simulation settings
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2022-02-18 12:36:22 -08:00 |
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tangxifan
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a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |
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tangxifan
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43d852d8a1
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[Test] Add the bus group test case to basic regression tests
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2022-02-18 12:27:25 -08:00 |
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tangxifan
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7176037bc4
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[Test] Added a new test about bus group
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2022-02-18 12:26:00 -08:00 |
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tangxifan
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73e6ee964d
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[Script] Add a new example script showing how to use bus group features
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2022-02-18 12:25:34 -08:00 |
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tangxifan
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f02f3c10d4
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[Test] Fix bugs on the remaining implicit verilog test cases
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2022-02-15 16:49:15 -08:00 |
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tangxifan
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074811a612
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[Script] Now counter benchmarks should pass on the implicit verilog test case
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2022-02-15 16:47:14 -08:00 |
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tangxifan
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1370be0817
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[Script] Fixing bugs
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2022-02-15 16:44:51 -08:00 |
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tangxifan
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8be0868a3b
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[Test] Update test case which uses counter benchmarks: adding pin constraints
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2022-02-15 16:29:06 -08:00 |
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tangxifan
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430580f138
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[HDL] Fix a typo
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2022-02-15 16:09:14 -08:00 |
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tangxifan
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a7786efde1
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[HDL] Now dual-clock counter has only 1 reset pin
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2022-02-15 16:07:50 -08:00 |
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tangxifan
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f002c79a61
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[Test] Adapt pin constraints due to changes in pin names
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2022-02-15 16:06:46 -08:00 |
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tangxifan
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b533fd17d5
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[Test] Rework pin constraints that cause problems
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2022-02-15 15:41:16 -08:00 |
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tangxifan
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9ef7ad64d8
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[Test] Simplify paths
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2022-02-15 15:35:21 -08:00 |
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tangxifan
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7121513396
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[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
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2022-02-15 15:21:08 -08:00 |
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tangxifan
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74045fc7a1
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[Script] Fix a bug
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2022-02-14 23:11:42 -08:00 |
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tangxifan
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2990eb7406
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[Script] Fixed a bug in task run when removing previous runs
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2022-02-14 22:54:16 -08:00 |
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tangxifan
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d0fe8d96fa
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[Test] Update template scripts and assoicated test cases by offering more options
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2022-02-14 16:03:48 -08:00 |
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tangxifan
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d667102a43
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[Test] Add new test case to regression tests
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2022-02-14 15:58:53 -08:00 |
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tangxifan
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70363effa4
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[Test] Add a new test to validate 8-bit counters using full testbenches
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2022-02-14 15:57:55 -08:00 |
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tangxifan
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2fb1df11bb
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[Script] Add a new example script
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2022-02-14 15:54:07 -08:00 |
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tangxifan
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7ef808cbe4
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[Test] Update pin constraints for different counter benchmarks
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2022-02-14 15:28:03 -08:00 |
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tangxifan
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570c1b10dc
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[Test] Add dedicated pin constraints for counter designs
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2022-02-14 13:54:48 -08:00 |
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tangxifan
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85011824e2
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[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
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2022-02-14 13:15:55 -08:00 |
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tangxifan
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6630c17c23
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[Test] Use preconfigured testbench template to run counter8 tests
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2022-02-14 13:07:31 -08:00 |
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tangxifan
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da3f9ccb80
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[Test] Truncating counter designs in each task
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2022-02-14 12:22:19 -08:00 |
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tangxifan
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0268814fc6
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[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |
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tangxifan
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1d3c9ff192
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[Script] Adapt python scripts to support include directory
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2022-02-01 13:55:25 -08:00 |
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tangxifan
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27ac2fafe5
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[Test] Add the new test case to regression tests
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2022-02-01 13:45:46 -08:00 |
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tangxifan
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532af96243
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[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
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2022-02-01 13:44:47 -08:00 |
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tangxifan
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35c7968c98
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[Script] Add a new example openfpga shell script
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2022-02-01 13:40:22 -08:00 |
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tangxifan
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09ef516de8
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[Script] Tune OpenFPGA shell script to enable testing on relative paths
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2022-01-31 14:23:13 -08:00 |
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tangxifan
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9871fe88fb
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[Test] Typo fix
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2022-01-31 13:03:45 -08:00 |
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tangxifan
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da8fc0f5d4
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[Test] Add a new test case to validate ``--use_relative_path``
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2022-01-31 13:02:19 -08:00 |
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tangxifan
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e59ea91ad6
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[Script] Fixed a bug which causes errors
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2022-01-26 11:49:32 -08:00 |
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tangxifan
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f8ef3df560
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[Test] Now use 4x4 fabric in testing write_rr_gsb commands
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2022-01-26 11:41:48 -08:00 |
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tangxifan
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a9042318cf
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[Test] Deploy the test case to regression tests
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2022-01-26 11:26:17 -08:00 |
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tangxifan
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3b7588cd48
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[Test] Rename test case to be consistent with the name of options
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2022-01-26 11:25:54 -08:00 |
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tangxifan
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6b26ed0819
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[Test] Add test cases on writing gsb files
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2022-01-26 11:22:39 -08:00 |
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tangxifan
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5db049522d
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[Script] Add an example script about write GSB
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2022-01-26 11:22:23 -08:00 |
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tangxifan
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11e045992d
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[Test] Now only compare on the golden netlist changes to branch
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2022-01-25 21:24:10 -08:00 |
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tangxifan
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23795d6474
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[Test] Update golden netlists
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2022-01-25 20:37:08 -08:00 |
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tangxifan
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a9e6b7c12e
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[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
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2022-01-25 20:33:49 -08:00 |
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tangxifan
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c2c827ee10
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[Script] Fix a bug in git-diff for regression tests
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2022-01-25 20:27:41 -08:00 |
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tangxifan
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fedb1bd2e3
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[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
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2022-01-25 16:41:36 -08:00 |
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tangxifan
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5c0f63ddd9
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[Test] Update regression tests for the new test about ``--no_time_stamp``
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2022-01-25 16:30:48 -08:00 |
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tangxifan
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6e778a74ee
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[Test] Add golden reference for files outputted without time stamp
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2022-01-25 16:24:25 -08:00 |
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tangxifan
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2bee59c6ca
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[Test] Add the testcase to validate ``--no_time_stamp``
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2022-01-25 16:21:15 -08:00 |
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tangxifan
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dd803dd1de
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[Test] Remove unused tests
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2022-01-25 16:16:58 -08:00 |
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tangxifan
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e4cfa2222f
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[Script] Add an example script to test option ``--no_time_stamp``
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2022-01-25 16:16:39 -08:00 |
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tangxifan
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dd40057992
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[Script] Fixed a bug which causes errors when removing run-directory
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2022-01-25 13:56:42 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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397f2e71f1
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Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
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2022-01-19 20:43:26 +05:00 |
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Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
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Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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469b3a960c
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basic reg test updated
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2022-01-14 15:44:26 +05:00 |
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Awais Abbas
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793e40cb95
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basic_reg test for yosys-only flow added in OpenFPGA regression test scripts
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2022-01-14 15:39:26 +05:00 |
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Awais Abbas
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598c5e6b75
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Test case for yosys-only flow added
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2022-01-14 15:37:47 +05:00 |
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Awais Abbas
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fc52a4696c
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Yosys only support added in OpenFPGA
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2022-01-06 14:44:11 +05:00 |
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tangxifan
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27caeb1d1f
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[Arch] Patched VPR arch
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2022-01-02 20:47:22 -08:00 |
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tangxifan
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384a1e58d6
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[Arch] Patch architecture using DSP with registers
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2022-01-02 20:44:43 -08:00 |
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tangxifan
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e3baec63f8
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[Arch] Bug fix on architecture with registerable DSP
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2022-01-02 20:35:48 -08:00 |
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tangxifan
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f667065f75
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[Arch] Bug fix in DSP with registers architecture
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2022-01-02 20:34:26 -08:00 |
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tangxifan
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9c476ed5db
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[Arch] Syntax error fix
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2022-01-02 20:27:00 -08:00 |