Commit Graph

664 Commits

Author SHA1 Message Date
Lalit Sharma 3c9e4919b4 Updating variable name in ys to call BLIF output file. 2020-12-18 03:18:46 -08:00
Lalit Sharma 1f994319fd Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF 2020-12-16 04:19:56 -08:00
Lalit Sharma 891e2f8aa3 Adding arch xml from SOFA repo. Also updating the script with its file location 2020-12-16 04:14:18 -08:00
Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow 2020-12-10 02:41:43 -08:00
tangxifan 6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
tangxifan 6001da3a40 [Arch] Bug fix in tileable I/O arch example 2020-12-04 17:56:54 -07:00
tangxifan 1d0bdcfeca [Arch] Simplify the grid layout modeling 2020-12-04 17:38:44 -07:00
tangxifan 1c3f625e41 [Arch] Force empty tiles at corners for tileable I/O arch example 2020-12-04 17:11:06 -07:00
tangxifan 0cb8457e21 [Test] Add test case for tileable I/O 2020-12-04 16:02:47 -07:00
tangxifan 186eb0f0a4 [Arch] Add tileable I/O architecture example 2020-12-04 15:59:39 -07:00
ganeshgore 289d9d2169 [Bugfix] Honors yosys_tmpl parameter in flow script 2020-12-03 12:24:24 -07:00
tangxifan 412fb5bb31 [Arch] Bug fix due to valid default value parser 2020-12-02 17:51:50 -07:00
tangxifan 179b0ce304 [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile 2020-11-30 18:11:47 -07:00
tangxifan c7604ab94f [Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA 2020-11-30 18:02:00 -07:00
tangxifan ff53d2c375 [HDL] Add new Scan-chain DFF cell 2020-11-30 17:54:10 -07:00
tangxifan ad703ad85b [HDL] Add new gpio cell with protection circuitry 2020-11-30 17:52:39 -07:00
tangxifan 27a480b5f8 [Test] arch name fix in the test case 2020-11-30 17:45:54 -07:00
tangxifan 7a0a3398d4 [Arch] Add new architecture to test global reset ports defined thru tile ports 2020-11-30 17:43:41 -07:00
tangxifan a1d3b439d3 [Test] Add a new test case to define a global reset port from a global tile port 2020-11-30 17:19:12 -07:00
tangxifan a60bd4d14a [Arch] Bug fix in nature fracturable architecture 2020-11-25 22:48:26 -07:00
ganeshgore 7db030018c [Bug] Fixed variable file location 2020-11-25 22:44:40 -07:00
tangxifan b8559249dc [Test] Bug fix in task configuration file 2020-11-25 22:23:27 -07:00
tangxifan 26e4db56ad [Test] Add new test case for the native fracturable LUT4 2020-11-25 22:21:23 -07:00
tangxifan 17070c6405 [Doc] Update README in openfpga arch directory for native fracturable LUT design 2020-11-25 22:19:20 -07:00
tangxifan f6a667de58 [Arch] Add openfpga architecture using native fracturable LUT 2020-11-25 22:18:03 -07:00
tangxifan eda671592e [Doc] Update README about new keyword about fracturable LUT 2020-11-25 22:12:56 -07:00
tangxifan 0f841aa6d1 [Arch] Add an example architecture using native fracturable LUT 2020-11-25 22:11:14 -07:00
ganeshgore 59bd7d0f18 [Flow] Changed substitute to safe_sustitute option 2020-11-25 22:09:36 -07:00
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
ganeshgore 1d993296d8 [Flow] Example of using test variable in task conf 2020-11-25 17:25:12 -07:00
ganeshgore 1554f583b7 [Flow] Now support explicit variable file for task 2020-11-25 17:22:41 -07:00
tangxifan fd80cacaa3 [Flow] Add example script for behaviorial verilog generation 2020-11-22 21:14:10 -07:00
tangxifan 617f7e3062 [Flow] disable signal initialization for behavioral verilog generation 2020-11-22 21:13:22 -07:00
tangxifan 5eb04e6fff [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals 2020-11-22 20:53:32 -07:00
tangxifan 655da9f3d0 [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
tangxifan 348872f8a4 [Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes 2020-11-22 16:12:28 -07:00
tangxifan 845436fa71 [Test] Add sequential benchmark for global tile clock test case 2020-11-17 14:34:54 -07:00
tangxifan 91b0dbbaa2 [Script] Add example openfpga shell run script when using global tile clocks 2020-11-17 14:33:12 -07:00
tangxifan 485258a9ea [Test] Add test case for global clock from tiles 2020-11-10 19:24:25 -07:00
tangxifan f29916921a [Arch] Add openfpga arch for using global clocks from tiles 2020-11-10 19:20:08 -07:00
tangxifan a6531d9e8d [Arch] Add k4 arch using global clock from tile port (with zero fc) 2020-11-10 19:17:34 -07:00
tangxifan 75ce4b5e25 [Arch] Fine tune example arch 2020-11-10 14:38:47 -07:00
tangxifan d127304760 [Arch] Update sample arch using local clock from physical tile ports 2020-11-10 14:31:58 -07:00
tangxifan 4ca2a129c2 [Arch] Add an sample architecture where global clock port is defined from tile ports 2020-11-10 11:47:03 -07:00
tangxifan 70734abc35 [Arch] Remove QN from stdcell arch 2020-11-06 11:20:13 -07:00
tangxifan 1a79a55646 [HDL] Add DFF cell with reset but only 1 output 2020-11-06 11:19:19 -07:00
tangxifan 2aab8bf910 [Arch] Use single-output DFF for a standard cell FPGA 2020-11-06 10:26:39 -07:00
tangxifan 7d46b35296 [HDL] Add single-output DFF HDL 2020-11-06 10:18:37 -07:00
Laboratory for Nano Integrated Systems (LNIS) 55f7a2c187
Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
2020-11-04 21:55:37 -07:00
tangxifan bce8233019 [Arch] Bug fix in caravel arch 2020-11-04 20:58:58 -07:00
tangxifan 6b48ee7f0b [Test] Add new test for caravel io support 2020-11-04 20:58:40 -07:00
tangxifan c85edb4738 [Arch] Bug fix for embedded io arch 2020-11-04 20:52:47 -07:00
tangxifan a6c7bb2c48 [Arch] Update OpenFPGA arch for new syntax on I/O 2020-11-04 20:24:02 -07:00
tangxifan dd86f7f464 [Arch] Path architecture for caravel i/o interface 2020-11-04 17:16:21 -07:00
tangxifan c074e88dcd [HDL] Add embedded I/O HDL for Caravel SoC interface 2020-11-04 17:09:59 -07:00
tangxifan aebf7453d0 [Arch] Add architecture files with compatible I/O capacity with caravel SoC 2020-11-04 16:57:00 -07:00
tangxifan 61376a2979 [Test] Add test cases for various tile organization 2020-11-04 16:32:52 -07:00
tangxifan cf455df555 [Arch] Add architecture for bottom-right and top-left tile organization 2020-11-04 16:24:36 -07:00
tangxifan 46ca406f10 [Arch] Add a new vpr architecture with new tile organization 2020-11-04 16:20:01 -07:00
tangxifan 049ca14461 [Doc] Add new naming rules for vpr architecture files 2020-11-04 16:17:56 -07:00
Laboratory for Nano Integrated Systems (LNIS) 5d41cc6d23
Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
2020-11-02 21:10:52 -07:00
tangxifan c036c87d6d [HDL] Bug fix in the GP output pad 2020-11-02 18:37:53 -07:00
tangxifan 3b49e6d090 [Arch] Patch embedded IO architecture by forcing only 1 pad per block 2020-11-02 15:39:31 -07:00
tangxifan c512644a09 [Arch] Patch embedded I/O example architecture 2020-11-02 15:16:19 -07:00
tangxifan 7e9e0ec9d4 [HDL] Bug fix in I/O HDL code 2020-11-02 15:15:45 -07:00
tangxifan 2f237a6240 [HDL] Add HDL codes for embedded I/Os 2020-11-02 14:01:27 -07:00
tangxifan 55b77ac6cb [Arch] Bug fixed in embedded FPGA architecture 2020-11-02 13:57:15 -07:00
tangxifan a7e7fa2005 [Arch] Update arch with true embedded I/O definition 2020-11-02 13:29:40 -07:00
tangxifan 65ca53ac98 [Test] Update test case with the new arch name 2020-11-02 13:16:42 -07:00
tangxifan 8c8190047f [Arch] Rename architecture files for embedded I/Os 2020-11-02 13:15:19 -07:00
tangxifan bc00dee858 [Test] Add test case for embedded I/O 2020-11-02 12:28:25 -07:00
tangxifan f86f43d287 [Arch] Add openfpga architecture file for constrained pin equivalence 2020-11-02 12:27:40 -07:00
tangxifan 795b30f76b [Arch] Add VPR architecture with partial pin equivalence 2020-11-02 11:54:25 -07:00
tangxifan 032cbfb8b2
Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
2020-10-31 10:37:38 -06:00
tangxifan 4c14428400 [Test] Add test case for fast configuration support on multi-region frame-based configuration protocol 2020-10-30 10:50:00 -06:00
tangxifan ca7d43275d [Test] Add test case for multi_region configuration frame 2020-10-30 10:48:29 -06:00
tangxifan 29da368742 [Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories 2020-10-30 10:46:47 -06:00
tangxifan b701bd2640 [Arch] Add multi-region architecture example for frame-based protocol 2020-10-30 10:45:14 -06:00
Laboratory for Nano Integrated Systems (LNIS) cd0d3dd798
Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
2020-10-29 18:39:44 -06:00
tangxifan 1d930d1b5d [Architecture] Add missing arch files and bug fix 2020-10-29 18:08:26 -06:00
tangxifan 153b265a6d [Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set 2020-10-29 16:32:05 -06:00
tangxifan 241ebf054a [Test] Add a test case for validating fast configuration techniques on multi-region memory banks 2020-10-29 16:29:46 -06:00
tangxifan ff386001c4 [Test] Add openfpga task for multi-region memory banks 2020-10-29 13:56:32 -06:00
tangxifan 7534474423 [Arch] Add architecture for multiple-region memory banks 2020-10-29 13:54:51 -06:00
Laboratory for Nano Integrated Systems (LNIS) d984547258
Merge pull request #108 from LNIS-Projects/dev
Add test cases for constant inputs of routing multiplexers
2020-10-14 22:33:14 -06:00
tangxifan 179ae355d0 [Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops 2020-10-13 12:02:26 -06:00
tangxifan 97c3bf7ea0 [Test] Add a test case for non-constant input multiplexers 2020-10-13 11:58:17 -06:00
tangxifan c5bcd93408 [Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input 2020-10-13 11:57:21 -06:00
tangxifan 99b1e68d92 [Architecture] Add architecture using GND as constant inputs for multiplexers 2020-10-13 11:39:27 -06:00
tangxifan 570b494df7 [Test] Add test case for using GND signal as constant input for routing multiplexers 2020-10-13 11:38:54 -06:00
Laboratory for Nano Integrated Systems (LNIS) 16128f0905
Merge pull request #107 from LNIS-Projects/dev
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
2020-10-12 13:47:40 -06:00
tangxifan dc68c52d0a [Test] Now use a light architecture to speed up the test case runtime 2020-10-12 12:53:34 -06:00
tangxifan e59377a3ec [Flow] bug fix in the sample script for fabric netlist customization 2020-10-12 12:52:01 -06:00
tangxifan 8941e38613 [Test] Enable verification in the new test case 2020-10-12 12:50:08 -06:00
tangxifan 9e1fd300dc [Test] Add test case for customized location of fabric netlists 2020-10-12 12:47:58 -06:00
tangxifan e510e79c12 [Flow] Add openfpga shell example script to use fabric netlist option 2020-10-12 12:42:43 -06:00
Laboratory for Nano Integrated Systems (LNIS) 8493345b52
Merge pull request #105 from LNIS-Projects/dev
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
2020-10-10 21:43:02 -06:00
tangxifan 82e7b159ce [Regression test] Add test case for fracturable LUT using AND gate to switch modes 2020-10-10 20:26:41 -06:00
tangxifan d0014878d5 [Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes 2020-10-10 20:24:57 -06:00
tangxifan 521accdc88
Merge pull request #104 from lukefahr/disp_fix
FLOW:  fixed display flag
2020-10-07 09:54:06 -06:00
tangxifan 7b12c28e4f
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
2020-10-06 20:05:02 -06:00
Andrew Lukefahr 33bbe0ec48 FLOW: fixed display flag 2020-10-06 20:52:28 -04:00
Andrew Lukefahr d68427e47b Fixed blif formatting bug 2020-10-06 20:46:50 -04:00
Andrew Lukefahr 2d92a1f1af Edits to enable basic run_fpga_flow.py 2020-10-02 10:18:10 -04:00
tangxifan d4d02ab16a [Regression Test] Move fabric key tests to basic tests 2020-09-29 14:22:23 -06:00
tangxifan ff6570df9d [Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI 2020-09-29 14:19:40 -06:00
tangxifan 4f00d310d3 [Architecture] Add example fabric key using multiple regions 2020-09-29 14:14:50 -06:00
tangxifan 02ea639959 [Regression Test] Add test for fabric key based on multiple region 2020-09-29 14:13:38 -06:00
tangxifan a0d1d68402 [Regression Test] Add regression tests for smart fast configuration chain using multiple regions 2020-09-29 13:53:41 -06:00
tangxifan d5c7411399 [Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain 2020-09-29 13:50:31 -06:00
tangxifan 5be5835b71 [Regression Test] Add multiple region configuration chain test case 2020-09-29 13:48:39 -06:00
tangxifan 23449dc5c3 [Architecture] Add multiple region configuration chain architecture 2020-09-29 13:46:40 -06:00
tangxifan e09e5fa6c6 [Architecture] Update fabric key for region syntax 2020-09-27 20:40:37 -06:00
tangxifan ffd926d686 [Architecture] Update external bitstream 2020-09-25 21:30:59 -06:00
tangxifan dcbd6a0614 [Architecture] Add lib name to TGATE to test compatibility 2020-09-25 21:08:12 -06:00
tangxifan 019208ec0f [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
tangxifan 20d6b2bf84 [Architecture] Remove out-of-date Verilog testbench 2020-09-24 21:14:13 -06:00
tangxifan 00bf775971 [Architecture] Bug fix for adder renaming 2020-09-24 20:54:18 -06:00
tangxifan 0a53a719bd [Architecture] Bug fix due to adder renaming 2020-09-24 20:42:24 -06:00
tangxifan e4bfa2ef51 [Architecture] Update external bitstream file 2020-09-24 20:16:50 -06:00
tangxifan bd0f0144a0 [Architecture] Rename AIB architecture for the new cell naming 2020-09-24 20:14:16 -06:00
tangxifan 8edfc79f53 [Architecture] Rename AIB cell 2020-09-24 20:11:21 -06:00
tangxifan 4ada793c84 [Architecture] Adapt openfpga architecture to follow the renamed adder cell 2020-09-24 20:09:29 -06:00
tangxifan 53187044e6 [Architecture] Rename adder cell 2020-09-24 20:07:57 -06:00
tangxifan 4a0a448171 [Architecture] Rename openfpga architecture for the I/O cell 2020-09-24 19:56:01 -06:00
tangxifan e0f9547f5b [Architecture] Rework the i/o cell Verilog HDL 2020-09-24 19:53:54 -06:00
tangxifan eb5fd1f44e [Architecture] Bug fix for architectures using scan-chain DFF cell 2020-09-24 18:37:25 -06:00
tangxifan 60a14ccbd2 [Architecture] Bug fix in architectures that use BRAM 2020-09-24 18:20:55 -06:00
tangxifan d51efd397f [Architecture] Bug fix for architectures using DFF cells 2020-09-24 18:02:42 -06:00
tangxifan 3ade6d6ff5 [Architecture] Bug fix for dff that are used in data path 2020-09-24 17:53:30 -06:00
tangxifan 3e7c88eac8 [Architecture] Bug fix in Verilog netlist for scan-chain DFF 2020-09-24 17:41:03 -06:00
tangxifan 7494556316 [Architecture] Bug fix for scan-chain FF cell 2020-09-24 17:38:16 -06:00
tangxifan 54b3f244d3 [Architecture] Remove obsolete Verilog netlists 2020-09-24 17:35:02 -06:00
tangxifan 49d6863641 [Architecture] Bug fix for scan-chain FF cell renaming 2020-09-24 17:33:14 -06:00
tangxifan 0a5369f919 [Architecture] Adapt all the architecture files to use standard DFF cell 2020-09-24 17:26:48 -06:00
tangxifan 19dd3778d9 [Architecture] Add test case for memory bank to use both reset and set 2020-09-24 17:04:24 -06:00
tangxifan 335f5b78c1 [Regression Test] Add test case to use both set and reset for configuration frame 2020-09-24 17:02:28 -06:00
tangxifan 2d81ff9012 [Regression test] Add configuration chain test case where both set and reset are used 2020-09-24 16:59:52 -06:00
tangxifan fc154b8560 [Architecture] Bug fix due to switching CCFF cell 2020-09-24 16:45:56 -06:00
tangxifan 79875d5a91 [Architecture] Bug fix in the configuration chain arch using both reset and set 2020-09-24 15:27:26 -06:00
tangxifan 9cb67e6097 [Architecture] Now all the configuration chain architecture use the DFFR cell by default 2020-09-24 15:19:37 -06:00
tangxifan 81965e75f6 [Architecture] Bug fix in DFF Verilog HDL 2020-09-24 14:53:21 -06:00
tangxifan 3b42fe94d6 [Architecture] Update external bitstream file 2020-09-24 14:41:44 -06:00
tangxifan 7fbccdd102 [Regression Tests] Add test cases for configuration chain using different DFF cells 2020-09-24 14:34:12 -06:00
tangxifan 178afb3c7f [Architecture] Add configuration chain architectures using different DFF cells 2020-09-24 14:23:27 -06:00
tangxifan 98d88dc686 [Architecture] Bug fix for vanilla memory organization 2020-09-24 14:13:48 -06:00
tangxifan efad0402c2 [Regression Test] Bug fix for CI errors 2020-09-24 13:55:41 -06:00
tangxifan e7906899dd [Regression test] Bug fix for fast configuration frame. Now should use a latch with reset 2020-09-24 13:53:12 -06:00
tangxifan e832d806c7 [Architecture] Add DFF Verilog netlist using standard naming convention 2020-09-24 13:50:59 -06:00
tangxifan 1b13e8ecb1 [Architecture] Bug fix in the SRAM Verilog 2020-09-24 12:26:13 -06:00