AurelienUoU
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fe218fc207
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Tutorial update
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2019-07-16 11:52:24 -06:00 |
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AurelienUoU
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a04555419a
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Typo fix
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2019-07-16 07:30:25 -06:00 |
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AurelienUoU
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3d079c9421
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Add folder creation in tuto_fpga_flow.sh to ease the use
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2019-07-16 07:20:21 -06:00 |
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AurelienUoU
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b810b5cab9
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fpga_flow bug fix + upload k8 architecture
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2019-07-16 07:04:45 -06:00 |
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AurelienUoU
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35e1962732
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Merge branch 'dev' into documentation
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2019-07-15 21:19:26 -06:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
tangxifan
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bcc6346533
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speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
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tangxifan
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4c6e245885
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speed-up the unique routing process
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2019-07-14 12:22:00 -06:00 |
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tangxifan
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b690e702f6
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adding more info to show the progress bar in backannotating GSBs
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2019-07-13 19:53:44 -06:00 |
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tangxifan
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aa4cd850ae
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try to optimize the runtime of routing uniqueness detection
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2019-07-13 18:10:34 -06:00 |
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tangxifan
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78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
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AurelienUoU
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1a5c5ff4a6
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Update demo simulation result path
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2019-07-12 16:52:54 -06:00 |
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AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
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AurelienUoU
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ef600bc63f
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Save workspace
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2019-07-12 15:57:41 -06:00 |
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AurelienUoU
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d10cc34c9e
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Update Readme and tutorial
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2019-07-12 14:56:08 -06:00 |
Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
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Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
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tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
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AurelienUoU
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e65cf9f5fd
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Update ERI-demo
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2019-07-12 08:55:19 -06:00 |
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Baudouin Chauviere
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40d3460bac
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
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29ffa1cdcb
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:09 -06:00 |
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Baudouin Chauviere
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e461cd0b99
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 22:09:49 -06:00 |
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Baudouin Chauviere
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1431ee2f82
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Fix Explicit verilog
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2019-07-11 22:09:34 -06:00 |
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tangxifan
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cffdebd912
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bug fixed for the tileable RR graph generator for heterogeneous blocks
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2019-07-11 21:02:09 -06:00 |
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tangxifan
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75ff2e904e
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 19:41:24 -06:00 |
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tangxifan
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e633e3d17b
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update fpga_flow scripts to support vpr_only flow
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2019-07-11 19:40:58 -06:00 |
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Baudouin Chauviere
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c9b84f61c9
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Hot fix
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2019-07-11 17:39:02 -06:00 |
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Baudouin Chauviere
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d0cd5a2bc1
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Hot fix
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2019-07-11 17:27:31 -06:00 |
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tangxifan
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9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
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AurelienUoU
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1848771e54
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Add explicit mapping option into fpga_flow
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2019-07-11 14:44:30 -06:00 |
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Baudouin Chauviere
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f4be375637
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Latest version explicit
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2019-07-11 14:33:56 -06:00 |
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AurelienUoU
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ad0b4b3acd
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Merge remote-tracking branch 'origin/dev' into documentation
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2019-07-11 10:15:26 -06:00 |
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AurelienUoU
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346b6f3e8e
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Update docker part in building.md
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2019-07-11 10:13:55 -06:00 |
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AurelienUoU
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c556b85d66
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Update docker instruction
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2019-07-11 10:10:30 -06:00 |
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tangxifan
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31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
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AurelienUoU
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3cd214ada2
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tuto flow v2.1
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2019-07-10 16:14:38 -06:00 |
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AurelienUoU
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db9c4be963
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Tuto flow v2
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2019-07-10 16:00:22 -06:00 |
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AurelienUoU
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9d7ae2f6ec
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Update tutorial flow demo draft 6
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2019-07-10 15:42:31 -06:00 |
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tangxifan
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a90316e9f4
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 15:13:46 -06:00 |
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tangxifan
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acee0161c7
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Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
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tangxifan
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206fc84a0e
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minor fix in fpga_flow
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2019-07-10 15:12:51 -06:00 |
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AurelienUoU
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a47711203c
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Tuto update draft 5
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2019-07-10 14:59:03 -06:00 |
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Baudouin Chauviere
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6441f2ebe7
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 14:16:55 -06:00 |
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Baudouin Chauviere
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0a978db866
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Fix regression test
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2019-07-10 14:16:34 -06:00 |
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tangxifan
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b7f9831bd2
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add statistics for unique GSBs
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2019-07-10 13:08:03 -06:00 |
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AurelienUoU
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422ede7610
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Update tutorial draft 4
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2019-07-10 12:17:07 -06:00 |
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tangxifan
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c6a4d29ed8
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Merge branch 'tileable_routing' into dev
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2019-07-10 12:05:43 -06:00 |
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AurelienUoU
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cb782a0e9f
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Draft 3
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2019-07-10 11:00:36 -06:00 |
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AurelienUoU
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905293820f
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Draft2
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2019-07-10 10:37:05 -06:00 |
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AurelienUoU
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20ce020eb6
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Tutorial rewrite draft 1
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2019-07-10 10:03:30 -06:00 |