AurelienUoU
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21dc8a006f
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Change simulator script generation (waves)
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2018-12-14 14:40:04 -07:00 |
LNIS-Projects
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c0e49b7d4d
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Update .travis.yml
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2018-12-14 14:16:04 -07:00 |
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LNIS-Projects
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c7915511f7
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Update .travis.yml
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2018-12-14 14:12:26 -07:00 |
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LNIS-Projects
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74c1067220
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Update .travis.yml
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2018-12-14 14:09:09 -07:00 |
tangxifan
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1d426986e5
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add travis
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2018-12-14 14:05:31 -07:00 |
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tangxifan
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ee6b1d6cd6
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adapt arch xml and act for demo
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2018-12-13 22:46:40 -07:00 |
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tangxifan
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3d9e913e4e
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add a benchmark fifo
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2018-12-12 16:45:33 -07:00 |
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AurelienUoU
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cc5a01d476
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Fix waveform generation + add benchmark and update go.sh
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2018-12-11 22:21:39 -07:00 |
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AurelienUoU
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a70b0ac9ac
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Correct go.sh
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2018-12-11 15:51:21 -07:00 |
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AurelienUoU
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317c3b59c9
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Update go.sh and upload pip_add.v
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2018-12-11 15:47:05 -07:00 |
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AurelienUoU
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fb0992bd85
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Update go.sh and Makefile
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2018-12-11 15:31:32 -07:00 |
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AurelienUoU
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c2c4e78639
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Add pip_add benchmark
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2018-12-11 15:29:48 -07:00 |
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AurelienUoU
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f5ea3ff233
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Add an autochecked configuration free testbench
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2018-12-11 14:44:13 -07:00 |
Baudouin Chauviere
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79f3db9880
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removed the now useless tutorial part
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2018-12-10 13:57:01 -07:00 |
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Baudouin Chauviere
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ba6ace343b
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-12-10 13:48:09 -07:00 |
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LNIS-Projects
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55459f7906
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Update index.rst
Reorganization
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2018-12-10 13:46:38 -07:00 |
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LNIS-Projects
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56555fc8a0
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Update index.rst
Removed abc from the project because included in Yosys
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2018-12-10 13:46:02 -07:00 |
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tangxifan
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8891904e10
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-12-10 13:30:12 -07:00 |
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tangxifan
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72fbd8d6a8
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update blif reader to identify clock signals
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2018-12-10 13:28:44 -07:00 |
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LNIS-Projects
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7bcc61b0f2
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Update .gitmodules
Unused submodule blocking the compilation of the documentation
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2018-12-10 12:07:05 -07:00 |
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Baudouin Chauviere
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1472e7aa62
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-12-10 10:25:25 -07:00 |
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AurelienUoU
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a69c2e1882
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Add security in checking to avoid simulation glitch error
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2018-12-10 09:46:16 -07:00 |
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AurelienUoU
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7020d9b4b6
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Edit waveform generator + fix clock mapping in autochecked testbench
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2018-12-09 15:48:59 -07:00 |
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Baudouin Chauviere
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afbe5bd3ff
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need abc_with_bb_support for ace compilation
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2018-12-09 15:45:09 -07:00 |
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AurelienUoU
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5e94b7093d
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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Aur??Lien ALACCHI
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10866d1852
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Correct verilog syntax error in autocheck testbench
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2018-12-08 17:40:23 -07:00 |
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Aur??Lien ALACCHI
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d716b67e23
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Correct syntax error in autocheck testbench
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2018-12-08 17:29:56 -07:00 |
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Aur??Lien ALACCHI
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0580d8243f
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Add Autochek testbench option
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2018-12-08 17:19:12 -07:00 |
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Baudouin Chauviere
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b0fcbc0960
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remove abc with bb support
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2018-12-08 16:40:57 -07:00 |
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Baudouin Chauviere
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79930982cf
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Changed for the naming
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2018-12-08 16:19:38 -07:00 |
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Baudouin Chauviere
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4440066565
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added the script to launch vpr with picorv
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2018-12-08 16:01:58 -07:00 |
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Baudouin Chauviere
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c130404158
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add a section for picorv generation through the flow
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2018-12-08 11:33:14 -07:00 |
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Aur??Lien ALACCHI
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4cc875a5a5
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fix a bug in wired LUT
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2018-12-06 18:00:17 -07:00 |
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tangxifan
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b3c1018e28
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fixed a bug in wired LUT
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2018-12-06 16:50:30 -07:00 |
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Aur??Lien ALACCHI
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7795d4e7fd
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
unknown merge
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2018-12-06 15:35:22 -07:00 |
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Aur??Lien ALACCHI
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eebdf7cb10
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Add possibility to choose default value for initialization
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2018-12-06 15:34:14 -07:00 |
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Baudouin Chauviere
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0b6fcc8875
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Added the aliases for Yosys-ABC
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2018-12-06 15:06:01 -07:00 |
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Baudouin Chauviere
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0b1ccf7722
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and in the config path as well
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2018-12-06 14:57:32 -07:00 |
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Baudouin Chauviere
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6a54592a7b
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removed abc and added yosys in the flow
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2018-12-06 14:55:36 -07:00 |
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Baudouin Chauviere
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b6bb419e1d
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add a ModelSim option
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2018-12-06 14:13:37 -07:00 |
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Baudouin Chauviere
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fe47b3d21f
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Changing arch from memory dec to scff. Get the bitstream from go.sh
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2018-12-06 14:03:17 -07:00 |
BaudouinChauviere
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88af64c606
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Update eda_flow.rst
Distributions compilable added
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2018-12-05 16:29:07 -07:00 |
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BaudouinChauviere
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d0ac931daa
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Update README.md
Small correction
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2018-12-05 16:27:37 -07:00 |
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BaudouinChauviere
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576feb600f
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Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
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2018-12-05 16:24:03 -07:00 |
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Aur??Lien ALACCHI
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8281b7346b
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Edit auto-generated modelsim script
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2018-12-05 16:15:29 -07:00 |
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Aur??Lien ALACCHI
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44b7f7f3d4
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Correct sub_modules.v generation to include decoders.v when necessary
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2018-12-05 13:52:25 -07:00 |
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Aur??Lien ALACCHI
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dc4accedd9
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Add forgottent files + add parameter transmission from verilog_api.c
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2018-12-05 11:33:14 -07:00 |
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Aur??Lien ALACCHI
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9a8c7b391a
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Add process for modelsim script autogeneration
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2018-12-05 09:20:47 -07:00 |
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Aur??Lien ALACCHI
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75d64db0f9
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Add verilog header sub_module.v file generation
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2018-12-04 18:42:47 -07:00 |
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Aur??Lien ALACCHI
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8ac566ecc0
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |