Commit Graph

994 Commits

Author SHA1 Message Date
Xifan Tang d7e2a78d86 creating documentation 2018-09-13 11:52:12 -06:00
Xifan Tang bdffcbd559 creating documentations 2018-09-13 11:51:32 -06:00
Xifan Tang 1cf066d3ad Fixing minor bugs 2018-09-06 14:25:23 -06:00
Xifan Tang c009a37580 fix minor bugs 2018-09-04 17:56:37 -06:00
Xifan Tang 42da9160f0 Clean codes and update 2018-09-04 17:49:20 -06:00
Xifan Tang 9f3cb45b85 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-09-04 17:33:38 -06:00
Xifan Tang 00ecd0bb1d Cleanup codes and organization 2018-09-04 17:31:30 -06:00
tangxifan d3d95ee842
Update getting_started.md 2018-08-10 14:17:12 -06:00
Xifan Tang cb15bb5082 Clean code and fix minor bugs 2018-08-10 13:46:00 -06:00
Xifan Tang b0ef554b35 Add power property XML 2018-08-09 11:27:36 -06:00
Xifan Tang 90669d19c5 Update FPGA-SPICE and flow configurations 2018-08-09 11:27:16 -06:00
Xifan Tang 4d7f4350de get FPGA-SPICE updated for release - Clear printf and fix assert bugs 2018-08-01 14:04:28 -06:00
Steve Corey 91f073cdc4 added build files to .gitignore 2018-07-30 10:36:34 -06:00
Xifan Tang fe13168f8f Add ABC and ACE2, fix bugs for fpga_flow and VPR 2018-07-27 22:54:52 -06:00
Steve Corey b9d583519b Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-07-26 13:59:26 -06:00
Steve Corey be6c296c22 initial commit of black-box doc 2018-07-26 13:58:58 -06:00
Xifan Tang 158dec405e Reorganize the code directory 2018-07-26 11:28:21 -06:00
Steve Corey 3abce69f7c multimode clb simple documentation complete 2018-07-18 10:54:05 -06:00
Steve Corey c61d11baa6 changed some names to make more sense 2018-07-18 10:53:21 -06:00
Steve Corey 9c4e5ca95f ignored vpr output files 2018-07-18 10:50:37 -06:00
Steve Corey 1b36d491c8 ignored vpr output files 2018-07-18 10:48:55 -06:00
Steve Corey 51efa38751 continuing simple documentation 2018-07-17 13:55:10 -06:00
Steve Corey 84fd0348af initial commit of simple architecture documentation 2018-07-16 13:22:18 -06:00
Steve Corey 6f73b7a874 moved architecture documentation to new file 2018-07-16 13:21:41 -06:00
Steve Corey 17988e2ade changed switch names to make more sense 2018-07-16 13:21:07 -06:00
Steve Corey fa50eef093 added simple architecture for vpr version 8 2018-07-11 13:19:40 -06:00
Steve Corey 2208916a95 updated to line numbers of vpr8 example architecture 2018-07-10 13:02:21 -06:00
Steve Corey 8040328841 added notes about CLB 2018-07-09 13:06:22 -06:00
Steve Corey 8c7a7af458 started documenting architecture 2018-07-06 13:36:55 -06:00
Steve Corey 5b6ce1349e edited to match vtr_release7 version 2018-07-05 11:54:37 -06:00
Steve Corey 3f00ce365e tutorial additions 2018-07-03 15:04:09 -06:00
Steve Corey 2cc4027ab0 added tutorial files 2018-07-03 14:46:50 -06:00
Steve Corey 122c1b19f7 removed cloning 2018-07-02 11:12:28 -06:00
stevecorey 569bdbfb95 added submodule instructions 2018-06-29 13:30:44 -06:00
stevecorey cfcc177e4b added submodule instructions 2018-06-29 13:29:56 -06:00
stevecorey d5c0c7659b removed cloning 2018-06-29 13:24:18 -06:00
stevecorey f8e1e06a6c added git cloning and tool building 2018-06-29 11:16:13 -06:00
stevecorey 6f4b7f5cb9 added tangxifan-eda-tools as a submodule 2018-06-28 12:59:12 -06:00
stevecorey 099e180557 initial commit 2018-06-28 12:47:59 -06:00
stevecorey 8c341d8f51 initial commit 2018-06-28 11:50:25 -06:00
stevecorey 7b1e82e9c8 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-06-27 11:54:17 -06:00
stevecorey 6430fc5139 initial commit 2018-06-27 11:54:00 -06:00
Pierre-Emmanuel Gaillardon 508346c196
Create LICENSE 2018-06-26 21:52:08 -07:00
LNIS-Projects 520e9ae64b initial commit 2018-06-26 17:41:36 -06:00