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OpenFPGA
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removed cloning

This commit is contained in:
stevecorey 2018-06-29 13:24:18 -06:00
parent f8e1e06a6c
commit d5c0c7659b
1 changed files with 41 additions and 64 deletions
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105
jupyter_example.ipynb
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@ -16,46 +16,14 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"Clone the [FPGA-SPICE git repository:](https://github.com/LNIS-Projects/OpenFPGA)\n",
"\n"
]
},
{
"cell_type": "code",
"execution_count": 1,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
"Wait for the clone to finish with a return code of 0.\n"
]
},
{
"data": {
"text/plain": [
"0"
]
},
"execution_count": 1,
"metadata": {},
"output_type": "execute_result"
}
],
"source": [
"import os\n",
"# change to the user's HOME directory\n",
"os.chdir(os.environ['HOME']) \n",
"print (\"Wait for the clone to finish with a return code of 0.\")\n",
"os.system(\"git clone https://github.com/LNIS-Projects/OpenFPGA.git\")"
"The repository contains a submodule, so you need to get it as well:"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"The repository contains a submodule, so you need to get it as well:"
"Build the VPR tool with the FPGA-SPICE functionality:"
]
},
{
@ -67,7 +35,7 @@
"name": "stdout",
"output_type": "stream",
"text": [
"Wait for the submodule update to finish with a return code of 0.\n"
"Wait for make to finish with a return code of 0.\n"
]
},
{
@ -82,27 +50,7 @@
}
],
"source": [
"# move into the master repository \n",
"os.chdir(\"./OpenFPGA\")\n",
"# get the submodule\n",
"os.system(\"git submodule init\")\n",
"print (\"Wait for the submodule update to finish with a return code of 0.\")\n",
"os.system(\"git submodule update\")"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"Build the VPR tool with the FPGA-SPICE functionality:"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": [
"import os\n",
"# move to the directory with the Makefile\n",
"os.chdir(\"./tangxifan-eda-tools/branches/vpr7_rram/vpr/\")\n",
"# run make\n",
@ -119,7 +67,7 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 3,
"metadata": {},
"outputs": [],
"source": [
@ -136,12 +84,12 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 20,
"metadata": {},
"outputs": [],
"source": [
"arch = \"~/OpenFPGA/tangxifan-eda-tools/branches/vpr7_rram/libarchfpga/arch/sample_arch.xml\"\n",
"circuit = \"~/OpenFPGA/tangxifan-eda-tools/branches/vpr7_rram/vpr/Circuits/s298_K6_N10_ace.blif\""
"circuit = \"~/OpenFPGA/tangxifan-eda-tools/trunk/MPACK1.5_FLOW/BENCHMARKS/test_case1/add16_new.blif\""
]
},
{
@ -153,9 +101,20 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 21,
"metadata": {},
"outputs": [],
"outputs": [
{
"data": {
"text/plain": [
"0"
]
},
"execution_count": 21,
"metadata": {},
"output_type": "execute_result"
}
],
"source": [
"\n",
"command_line = fpga_spice + \" \" + arch + \" \" + circuit\n",
@ -173,7 +132,7 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 22,
"metadata": {},
"outputs": [],
"source": [
@ -182,12 +141,30 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 23,
"metadata": {},
"outputs": [],
"outputs": [
{
"data": {
"text/plain": [
"0"
]
},
"execution_count": 23,
"metadata": {},
"output_type": "execute_result"
}
],
"source": [
"os.system(command_line_nodisp)"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
}
],
"metadata": {