added notes about CLB

jupyter_example.ipynb

@@ -230,6 +230,8 @@
     "\n",
     "Line 18 has the `<models>` tag which would describe `BLIF` circuit model names that the FPGA accepts. This architecture is simple enough to not need any additional models beyond the default `.names .latch .input .output`.\n",
     "\n",
+    "## Layout and Routing\n",
+    "\n",
     "Line 23 has the `<layout>` tag which specifies how the FPGA grid will be laid out. For this example: `<layout auto=\"1.000000\"/>` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout.\n",
     "\n",
     "Line 24 begins the `<device>` tag which characterizes the components of the FPGA. `<sizing>` specifies the resistance of the minimum-width nmos and pmos transistors. `<area grid_logic_tile_area>` is used as an estimate of the size of one grid tile.\n",
@@ -240,7 +242,31 @@
     "\n",
     "Line 35 is the `<switchlist>` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n",
     "\n",
-    "Line 38 is the `<segmentlist>` section that specifies kinds of wire segments and their properties such as resistance and capacitance. `<sb type=\"pattern\">1 1</sb>` describes a pattern on a 1-length wire where there is a switch box between each grid element. `<cb type=\"pattern\">1</cb>` describes a pattern on a 1-length wire where there is a connection box at each grid element.\n"
+    "Line 38 begins the `<segmentlist>` section that specifies kinds of wire segments and their properties such as resistance and capacitance. `<sb type=\"pattern\">1 1</sb>` describes a pattern on a 1-length wire where there is a switch box between each grid element. `<cb type=\"pattern\">1</cb>` describes a pattern on a 1-length wire where there is a connection box at each grid element.\n"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "Line 46 begins the `<complexblocklist>` section which is where the I/O and logic blocks are defined.\n",
+    "\n",
+    "# Skip I/O for now...\n",
+    "\n",
+    "\n",
+    "## Logic Blocks\n",
+    "\n",
+    "Line 106 is where the general purpuse *complex logic block* or *clb* definition begins. `<pb_type>` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n",
+    "\n",
+    "Line 112 defines the *basic logic element* or *BLE* that makes up the clb. The `<pb_type name=\"fle\" num_pb=\"4\">` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n",
+    "\n",
+    "Skipping down to line 125, the core lookup-table of the BLE is defined: `<pb_type name=\"lut4\" blif_model=\".names\" num_pb=\"1\" class=\"lut\">`.  This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `<delay_matrix>` attribute specifies the propogation delay through the LUT's inputs to output.\n",
+    "\n",
+    "Line 138 defines the flip-flop in the BLE: `<pb_type name=\"ff\" blif_model=\".latch\" num_pb=\"1\" class=\"flipflop\">`: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n",
+    "\n",
+    "Skipping back up to line 117, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 199 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n",
+    "\n",
+    "Moving back down to line 146, `<interconnect>` indicates how the blocks are connected. The `<direct>` element means to simply wire the nets together. Line 147 wires the input of `ble4` to the input of `lut4`, line 148 wires the output of `lut4` to the D-input of `ff`. Line 152 wires the clk inputs together. Line 153 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`."
    ]
   },
   {

tutorial/example_arch.xml

@@ -113,9 +113,9 @@
         <input name="in" num_pins="4"/>
         <output name="out" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
-        <!-- 6-LUT mode definition begin -->
+        <!-- 4-LUT mode definition begin -->
         <mode name="n1_lut4">
-          <!-- Define 6-LUT mode -->
+          <!-- Define 4-LUT mode -->
           <pb_type name="ble4" num_pb="1">
             <input name="in" num_pins="4"/>
             <output name="out" num_pins="1"/>