tangxifan
|
b9a0b1cdf8
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[core] code format
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2024-10-07 14:21:19 -07:00 |
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tangxifan
|
4f96680e1f
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[core] adapt to side var changes
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2024-10-07 14:20:48 -07:00 |
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tangxifan
|
1225679aac
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[core] code format
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2024-08-06 17:35:44 -07:00 |
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tangxifan
|
0dba4082d1
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[core] syntax
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2024-08-06 17:20:34 -07:00 |
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tangxifan
|
ac2337d24b
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[core] rework the option 'constant_undriven_inputs'
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2024-08-06 16:50:49 -07:00 |
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tangxifan
|
215de8eb93
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[core] code format
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2024-07-10 14:17:22 -07:00 |
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tangxifan
|
f5ba43e392
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[core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench
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2024-07-10 14:16:24 -07:00 |
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tangxifan
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213914e4ac
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[core] code format
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2024-07-10 12:23:57 -07:00 |
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tangxifan
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48e159dd8d
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[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
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2024-07-10 12:23:15 -07:00 |
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tangxifan
|
703cbddc9e
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[core] code format
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2024-07-06 12:14:57 -07:00 |
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tangxifan
|
1f8c2436ef
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[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
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2024-07-04 20:46:38 -07:00 |
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tangxifan
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4e21bbb3f1
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[core] now support constant undriven local wires in verilog writer
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2024-07-04 20:32:56 -07:00 |
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tangxifan
|
1dd03d0fdd
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[core] on a new feature to connect undriven pins to ground
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2024-07-04 18:34:39 -07:00 |
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tangxifan
|
0a7915aa77
|
[core] typo
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2024-03-29 12:03:23 -07:00 |
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tangxifan
|
6a5d3c7cdc
|
[code] syntax
|
2024-03-29 11:03:48 -07:00 |
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tangxifan
|
00de794967
|
[core] code format
|
2024-03-29 10:58:48 -07:00 |
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tangxifan
|
981828c39c
|
[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
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2024-03-29 10:57:45 -07:00 |
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tangxifan
|
bacd845139
|
[core] code format
|
2023-12-08 13:41:41 -08:00 |
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tangxifan
|
5e181cbe72
|
[core] add a new option for simulator type to verilog full testbench generator
|
2023-12-08 13:07:25 -08:00 |
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tangxifan
|
0e945d6e71
|
[core] fix a bug in ql memory bank tb where VCS failed
|
2023-12-08 11:36:54 -08:00 |
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tangxifan
|
b780f0a552
|
[core] code format
|
2023-11-03 14:39:49 -07:00 |
|
tangxifan
|
e48de682ed
|
[core] fixed som ebugs
|
2023-11-03 14:39:28 -07:00 |
|
tangxifan
|
b2e1eb30c7
|
[core] code format
|
2023-11-03 13:50:04 -07:00 |
|
tangxifan
|
21813eb59f
|
[core] now full testbench uses bitstream in different sizes
|
2023-11-03 13:48:21 -07:00 |
|
tangxifan
|
2cd3453629
|
[core] fixed the bug in ccff v2 on config enable signal drivers
|
2023-11-03 10:25:12 -07:00 |
|
tangxifan
|
8bee65853c
|
[core] add missing files
|
2023-11-02 19:01:25 -07:00 |
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tangxifan
|
649d44b2d8
|
[core] code format
|
2023-11-02 16:33:55 -07:00 |
|
tangxifan
|
36fa020c15
|
[core] syntax
|
2023-11-02 16:33:19 -07:00 |
|
tangxifan
|
75e9e98e5d
|
[core] add two new commands to output testbench parts
|
2023-11-02 16:06:48 -07:00 |
|
tangxifan
|
5bae2bf54d
|
[core] code format
|
2023-10-19 23:05:49 -07:00 |
|
tangxifan
|
4b00651a46
|
[core] now name indexing is applied to netlist names
|
2023-10-19 23:03:48 -07:00 |
|
tangxifan
|
4d11f73471
|
[core] fixed a bug
|
2023-09-18 20:43:15 -07:00 |
|
tangxifan
|
a1e609c901
|
[core] fixed some bugs
|
2023-09-18 16:39:07 -07:00 |
|
tangxifan
|
c6175aa514
|
[core] code format
|
2023-09-17 22:37:48 -07:00 |
|
tangxifan
|
ef97127c63
|
[core] fixed some bugs in testbenches when renaming top modules
|
2023-09-17 22:34:00 -07:00 |
|
tangxifan
|
4ccb4737be
|
[core] code format
|
2023-09-17 17:33:10 -07:00 |
|
tangxifan
|
f79da76656
|
[core] supporting renaming on all the verilog modules
|
2023-09-17 17:29:11 -07:00 |
|
tangxifan
|
058bb1ef51
|
[core] code format
|
2023-09-16 18:24:38 -07:00 |
|
tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
|
tangxifan
|
d61d88f12e
|
[core] fixed some bugs in verilog writer due to renaming
|
2023-09-16 18:13:22 -07:00 |
|
tangxifan
|
eaadff3448
|
[core] fixed some bugs
|
2023-09-06 22:49:56 -07:00 |
|
tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
|
tangxifan
|
2fee56548b
|
[core] fixed some bugs
|
2023-09-06 22:39:59 -07:00 |
|
tangxifan
|
f544953085
|
[core] code format
|
2023-09-06 22:29:30 -07:00 |
|
tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
|
2023-09-06 22:27:51 -07:00 |
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tangxifan
|
539bcba851
|
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
|
2023-09-06 17:23:41 -07:00 |
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tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
|
tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
|
2023-08-25 15:13:00 -07:00 |
|
tangxifan
|
a6d43beaca
|
[core] now tile verilog writer supports relative paths
|
2023-08-21 22:25:52 -07:00 |
|
tangxifan
|
bb945b2816
|
Merge branch 'master' into openfpga-issue-1256
|
2023-08-07 13:49:19 -07:00 |