tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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4bf0a63ae6
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bug fixed for multiple io types defined in FPGA architectures
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2020-03-27 16:32:15 -06:00 |
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tangxifan
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0c7aa2581d
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update vpr8 version with hotfix on undriven pins in GSB
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2020-03-08 14:58:56 -06:00 |
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tangxifan
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7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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2020-03-03 12:29:58 -07:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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b010fc1983
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add warning to force formal_verification_top_netlist enabled
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2020-02-27 13:28:21 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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77529f4957
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adapt top Verilog testbench generation
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2020-02-26 21:30:21 -07:00 |
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tangxifan
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bb671acac3
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add formal random Verilog testbench generation
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2020-02-26 20:58:16 -07:00 |
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tangxifan
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e9adb4fdbc
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add preconfig top module Verilog generation
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2020-02-26 20:38:01 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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60f40a9657
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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tangxifan
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11775c370b
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bring FPGA top module verilog writer online. Fabric Verilog generator done
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2020-02-16 16:18:14 -07:00 |
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tangxifan
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e37ac8a098
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
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c20caa1fa3
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routing module Verilog writer is online
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2020-02-16 14:47:54 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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99c3712b6f
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adapt Verilog wire module writer
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2020-02-16 12:59:37 -07:00 |
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tangxifan
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5cc68b0730
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adapt LUT Verilog writer
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2020-02-16 12:45:58 -07:00 |
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tangxifan
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105ccabecc
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adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |
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tangxifan
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c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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tangxifan
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a88c4bc954
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add decode utils to libopenfpga and adapt local decoder writer in Verilog
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2020-02-16 12:21:59 -07:00 |
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tangxifan
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3efd1a2a6d
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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tangxifan
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cf34339e96
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adapt essential gates for submodule generation
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2020-02-16 11:57:19 -07:00 |
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tangxifan
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2eba882332
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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tangxifan
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4cb61e2138
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bring preprocessing flag Verilog netlists online
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2020-02-16 00:03:24 -07:00 |
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tangxifan
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0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |
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tangxifan
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bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |