riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,898 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

999 Commits

Author SHA1 Message Date
tangxifan 0f2b8da7f0 [engine] code format 2022-10-17 14:55:34 -07:00
tangxifan 63d8b00630 [engine] syntax 2022-10-17 14:54:18 -07:00
tangxifan 11624cd0c6 [engine] enabling new feature: pin_table_direction_convention 2022-10-17 14:08:21 -07:00
tangxifan 0af6c76239 [engine] code format 2022-10-13 16:27:57 -07:00
tangxifan d1f3338837 [engine] now repacker find only routable pins when given a net to search routing traces 2022-10-13 16:26:45 -07:00
tangxifan 31da9bf6ea [engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node 2022-10-13 15:10:25 -07:00
tangxifan afdc071c4c [engine] apply code format 2022-10-06 18:13:33 -07:00
tangxifan e2debd2dde [engine] add missing header files after coding formatter sorts the include files 2022-10-06 18:08:57 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan 0d8d8446ee [test] fixed a bug where OPIN for direct connection is included in GSB 2022-09-30 15:24:51 -07:00
tangxifan fb2693171b [engine] fixed a bug which causes errors in repacker 2022-09-28 16:30:11 -07:00
tangxifan 36b3e64b35 [engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results 2022-09-28 12:17:16 -07:00
tangxifan 3285af4107 [engine] syntax 2022-09-28 11:39:37 -07:00
tangxifan 51f54bbf20 [engine] developing the steps to annotate clustering results 2022-09-27 16:54:48 -07:00
tangxifan 8272d2dcbc [engine] enrich verbose output for repacker, easier to debug 2022-09-27 10:46:57 -07:00
tangxifan e19ca1c6d1 [engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb 2022-09-19 18:49:54 -07:00
tangxifan c922259c23 [engine] remove warnings and update vtr 2022-09-19 14:53:30 -07:00
tangxifan 90ddd2ce32 [engine] now get incoming edges for IPINs only from GSB 2022-09-19 14:02:13 -07:00
tangxifan 3c6ef1925c [engine] now sort ipin incoming edges 2022-09-19 11:00:08 -07:00
tangxifan 373566416c Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-16 16:47:21 -07:00
tangxifan f0fe781dbc [engine] fixed a bug 2022-09-16 10:45:27 -07:00
tangxifan bba5b7b070 [engine] syntax 2022-09-15 23:04:37 -07:00
tangxifan cbc71c75c4 [engine] now io indexing follows a natural way 2022-09-15 23:01:35 -07:00
tangxifan 8378ad4bf3 [engine] fixed a bug on mistakenly adding I/O child modules for direct connections 2022-09-14 17:13:23 -07:00
tangxifan 036933dc14 [engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols 2022-09-14 16:46:10 -07:00
tangxifan 0425b00af5 [engine] fixed a bug for frame-based protocols 2022-09-14 16:41:30 -07:00
tangxifan cb89488f76 [engine] now support a custom list for indexing I/O children in each module 2022-09-14 15:54:55 -07:00
tangxifan eb8b7e6901 [engine] fixed a bug in i/o indexing 2022-09-14 11:30:34 -07:00
tangxifan 1c2192a87d [engine] fixed a few bugs 2022-09-12 16:50:32 -07:00
tangxifan 2fc124e109 [engine] now repack has a new option "--ignore_global_nets_on_pins" 2022-09-12 16:18:26 -07:00
tangxifan e5c7a3df9f [engine] syntax 2022-09-07 15:51:54 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
tangxifan 8d09773e65 [engine] remove unnecessary checks from sb mirror checker 2022-09-07 11:55:08 +08:00
tangxifan e748c7697d [engine] update code comments 2022-09-06 13:51:29 -07:00
tangxifan eab3580f79 [engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity 2022-09-06 13:40:29 -07:00
tangxifan 59440082ed [engine] fixed some syntax errors 2022-09-06 11:55:40 -07:00
tangxifan 2f84ce5955 [engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used 2022-09-06 11:48:21 -07:00
tangxifan b26b2d0ed0
Merge branch 'master' into vtr_upgrade 2022-09-02 10:05:23 -07:00
coolbreeze413 04abd1a36f add <array> declaration to fix gcc error 2022-09-02 19:26:28 +05:30
tangxifan 9e1abf5898
Merge branch 'master' into vtr_upgrade 2022-09-01 21:39:14 -07:00
tangxifan d3f08a893c [engine] now frame view will not build nets for configuration bus 2022-09-01 20:02:00 -07:00
tangxifan 001367ea41 [engine] syntax 2022-09-01 16:40:17 -07:00
tangxifan 1f5e4d4215 [engine] update fabric bitstream implementation 2022-09-01 16:29:42 -07:00
tangxifan ea6f609181 [engine] fixing a bug in fabric bitstream encoding 2022-09-01 16:28:17 -07:00
tangxifan e4aa6e0ee5 [engine] syntax 2022-09-01 15:17:39 -07:00
tangxifan ee87b5c348 [engine] fixed all the remaining syntax errors due to API mismatches 2022-09-01 09:57:12 -07:00
tangxifan 7c5046cf4e [engine] include the correct header file 2022-09-01 09:23:05 -07:00
tangxifan 71ad0721a1
Merge branch 'master' into vtr_upgrade 2022-08-31 13:56:17 -07:00
tangxifan 26388dfb2f [engine] fixed a bug which causes errors when writing unique GSB to files 2022-08-30 15:45:00 -07:00
tangxifan 3656154913 [engine] fixed syntax errors 2022-08-29 21:17:48 -07:00
tangxifan 2321ea6274 [engine] complete the code required to output rr_gsb with options 2022-08-29 20:44:16 -07:00
tangxifan 12a30196e0 [engine] updating gsb writer; Unfinished!!! 2022-08-29 16:58:48 -07:00
tangxifan b9abdbc5d4 [engine] enable verbose output 2022-08-27 19:59:57 -07:00
tangxifan e9d6e7e38a [engine] update vtr and enable more debugging info 2022-08-27 19:12:43 -07:00
tangxifan 0c2b49ddb9 [engine] remove debugging log output 2022-08-27 13:06:05 -07:00
tangxifan 25f6c529e0 [engine] fixed syntax errors when using clang 2022-08-25 09:58:43 -07:00
tangxifan b432ac05b4 [script] fixed typo on IPO options 2022-08-24 21:51:29 -07:00
tangxifan f853040875 [script] enable IPO in cmakefile 2022-08-24 14:34:33 -07:00
tangxifan ba6ae05091 [engine] update vtr and add in_edge checks to link_arch 2022-08-24 12:22:20 -07:00
tangxifan d1edc51165 [engine] clean up header files that include rr_graph_obj 2022-08-23 18:38:21 -07:00
tangxifan b3e4a06969 [engine] adapt vpr wrapper to the latest main.cpp from vtr 2022-08-23 14:28:05 -07:00
tangxifan 892770a8fb [engine] debugging subtile index failures 2022-08-23 14:13:10 -07:00
tangxifan 0a6b794ef0 [engine] fixed bugs in subtiles. Revisited the usage of client functions 2022-08-23 12:35:04 -07:00
tangxifan 019e663e12 [engine] fixing the bugs on building global nets to sub tile pins 2022-08-23 11:58:44 -07:00
tangxifan 10cefebca8 [engine] fixing bugs on using subtile index 2022-08-23 11:00:23 -07:00
tangxifan ba0ddd01d3 [engine] fixing the bugs on subtiles 2022-08-23 10:52:05 -07:00
tangxifan c17e5d46ab [engine] fixed a bug due to the API of subtile data structure 2022-08-22 21:44:05 -07:00
tangxifan 5d6a90d983 [engine] remove compile warnings 2022-08-22 20:59:50 -07:00
tangxifan 800ce6a290 [engine] avoid function naming conflicts 2022-08-18 19:33:56 -07:00
tangxifan 903dd6cef6 [engine] remove warnings 2022-08-18 15:56:18 -07:00
tangxifan a52597361b [script] remove duplicated libraries in dependency list for some libopenfpga 2022-08-18 11:34:01 -07:00
tangxifan e9c4d102c1 [engine] rename files to avoid conflicts with VPR files 2022-08-17 20:01:50 -07:00
tangxifan 40100c1ba3 [engine] remove warnings 2022-08-17 19:07:49 -07:00
tangxifan cb4b106d4e [engine] correcting syntax errors 2022-08-17 16:36:14 -07:00
tangxifan dfe30df462 [engine] resolve compilation warnings 2022-08-17 16:32:21 -07:00
tangxifan e0ae851e28 [engine] correcting compilation errors due to vpr upgrade 2022-08-17 16:25:12 -07:00
tangxifan ce32c3b30b [engine] fixing api errors 2022-08-17 14:47:14 -07:00
tangxifan 3c2bf5159b [engine] use new API to get node side 2022-08-17 14:38:40 -07:00
tangxifan 3c12810ad9 [engine] debugging 2022-08-17 14:37:13 -07:00
tangxifan 8f1aac885e [engine] fixing mismatches in APIs 2022-08-17 14:19:02 -07:00
tangxifan 4e871be357 [engine] adapt the use of API in RRGraph for annotation functions 2022-08-17 10:50:16 -07:00
tangxifan 01d53db484 [script] Adapt timing analysis APIs 2022-08-17 10:28:58 -07:00
tangxifan ade8f43a36 [engine] Updating RRGraph Annotation and VTr 2022-08-17 10:16:55 -07:00
tangxifan 716929536d [engine] adapting source files for new APIs in VTR 2022-08-17 09:54:31 -07:00
tangxifan d3d81f0b18 [engine] keep adapting to latest VTR 2022-08-16 21:05:50 -07:00
tangxifan 0c329866da [engine] Use RRGraphView in openfpga source codes 2022-08-16 16:48:32 -07:00
tangxifan ce7204daec [engine] debugging 2022-08-16 16:35:08 -07:00
tangxifan c1256ae818 [engine] added command 'pcf2place' to openfpga 2022-07-28 11:30:36 -07:00
tangxifan 2a5bffa6b9 [engine] developing pcf2place integration to openfpga 2022-07-28 10:30:43 -07:00
tangxifan 1c9da96f59 [lib] move io_location_map to libpcf 2022-07-26 16:00:28 -07:00
tangxifan 27fea8bbbe [lib] Merge librepackdc into libpcf 2022-07-26 15:54:32 -07:00
tangxifan 23f98d6a3b [engine] fixed a few bugs 2022-07-26 13:55:29 -07:00
tangxifan 85bcb36f34 [engine] fix compiler errors 2022-07-26 12:25:40 -07:00
tangxifan 0862eceed0 [engine] add an XML write to io location map: In the long run, we should decouple the writer function from the data structure!!! 2022-07-26 12:17:45 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan a7e87b9432 [FPGA-Bitstream] note limitations 2022-05-25 18:38:01 +08:00
tangxifan ffac5a66e1 [FPGA-Bitstream] Now encode address bits to save memory in bitstream database 2022-05-25 17:45:08 +08:00
tangxifan bf1a81fbb5 [FPGA-bitstream] add timer to computing intensive functions 2022-05-25 14:52:32 +08:00
tangxifan a20f6eaf06 [Engine] Fixed a few bugs 2022-04-10 21:29:38 +08:00