tangxifan
|
dd86f7f464
|
[Arch] Path architecture for caravel i/o interface
|
2020-11-04 17:16:21 -07:00 |
|
tangxifan
|
c074e88dcd
|
[HDL] Add embedded I/O HDL for Caravel SoC interface
|
2020-11-04 17:09:59 -07:00 |
|
tangxifan
|
aebf7453d0
|
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
|
2020-11-04 16:57:00 -07:00 |
|
tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
|
2020-11-04 16:32:52 -07:00 |
|
tangxifan
|
cf455df555
|
[Arch] Add architecture for bottom-right and top-left tile organization
|
2020-11-04 16:24:36 -07:00 |
|
tangxifan
|
46ca406f10
|
[Arch] Add a new vpr architecture with new tile organization
|
2020-11-04 16:20:01 -07:00 |
|
tangxifan
|
049ca14461
|
[Doc] Add new naming rules for vpr architecture files
|
2020-11-04 16:17:56 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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5d41cc6d23
|
Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
|
2020-11-02 21:10:52 -07:00 |
|
tangxifan
|
c036c87d6d
|
[HDL] Bug fix in the GP output pad
|
2020-11-02 18:37:53 -07:00 |
|
tangxifan
|
3b49e6d090
|
[Arch] Patch embedded IO architecture by forcing only 1 pad per block
|
2020-11-02 15:39:31 -07:00 |
|
tangxifan
|
c512644a09
|
[Arch] Patch embedded I/O example architecture
|
2020-11-02 15:16:19 -07:00 |
|
tangxifan
|
7e9e0ec9d4
|
[HDL] Bug fix in I/O HDL code
|
2020-11-02 15:15:45 -07:00 |
|
tangxifan
|
2f237a6240
|
[HDL] Add HDL codes for embedded I/Os
|
2020-11-02 14:01:27 -07:00 |
|
tangxifan
|
55b77ac6cb
|
[Arch] Bug fixed in embedded FPGA architecture
|
2020-11-02 13:57:15 -07:00 |
|
tangxifan
|
a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
|
2020-11-02 13:29:40 -07:00 |
|
tangxifan
|
65ca53ac98
|
[Test] Update test case with the new arch name
|
2020-11-02 13:16:42 -07:00 |
|
tangxifan
|
8c8190047f
|
[Arch] Rename architecture files for embedded I/Os
|
2020-11-02 13:15:19 -07:00 |
|
tangxifan
|
bc00dee858
|
[Test] Add test case for embedded I/O
|
2020-11-02 12:28:25 -07:00 |
|
tangxifan
|
f86f43d287
|
[Arch] Add openfpga architecture file for constrained pin equivalence
|
2020-11-02 12:27:40 -07:00 |
|
tangxifan
|
795b30f76b
|
[Arch] Add VPR architecture with partial pin equivalence
|
2020-11-02 11:54:25 -07:00 |
|
tangxifan
|
032cbfb8b2
|
Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
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2020-10-31 10:37:38 -06:00 |
|
tangxifan
|
4c14428400
|
[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
|
2020-10-30 10:50:00 -06:00 |
|
tangxifan
|
ca7d43275d
|
[Test] Add test case for multi_region configuration frame
|
2020-10-30 10:48:29 -06:00 |
|
tangxifan
|
29da368742
|
[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
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2020-10-30 10:46:47 -06:00 |
|
tangxifan
|
b701bd2640
|
[Arch] Add multi-region architecture example for frame-based protocol
|
2020-10-30 10:45:14 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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cd0d3dd798
|
Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
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2020-10-29 18:39:44 -06:00 |
|
tangxifan
|
1d930d1b5d
|
[Architecture] Add missing arch files and bug fix
|
2020-10-29 18:08:26 -06:00 |
|
tangxifan
|
153b265a6d
|
[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
|
2020-10-29 16:32:05 -06:00 |
|
tangxifan
|
241ebf054a
|
[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
|
2020-10-29 16:29:46 -06:00 |
|
tangxifan
|
ff386001c4
|
[Test] Add openfpga task for multi-region memory banks
|
2020-10-29 13:56:32 -06:00 |
|
tangxifan
|
7534474423
|
[Arch] Add architecture for multiple-region memory banks
|
2020-10-29 13:54:51 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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d984547258
|
Merge pull request #108 from LNIS-Projects/dev
Add test cases for constant inputs of routing multiplexers
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2020-10-14 22:33:14 -06:00 |
|
tangxifan
|
179ae355d0
|
[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
|
2020-10-13 12:02:26 -06:00 |
|
tangxifan
|
97c3bf7ea0
|
[Test] Add a test case for non-constant input multiplexers
|
2020-10-13 11:58:17 -06:00 |
|
tangxifan
|
c5bcd93408
|
[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
|
2020-10-13 11:57:21 -06:00 |
|
tangxifan
|
99b1e68d92
|
[Architecture] Add architecture using GND as constant inputs for multiplexers
|
2020-10-13 11:39:27 -06:00 |
|
tangxifan
|
570b494df7
|
[Test] Add test case for using GND signal as constant input for routing multiplexers
|
2020-10-13 11:38:54 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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16128f0905
|
Merge pull request #107 from LNIS-Projects/dev
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
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2020-10-12 13:47:40 -06:00 |
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tangxifan
|
dc68c52d0a
|
[Test] Now use a light architecture to speed up the test case runtime
|
2020-10-12 12:53:34 -06:00 |
|
tangxifan
|
e59377a3ec
|
[Flow] bug fix in the sample script for fabric netlist customization
|
2020-10-12 12:52:01 -06:00 |
|
tangxifan
|
8941e38613
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[Test] Enable verification in the new test case
|
2020-10-12 12:50:08 -06:00 |
|
tangxifan
|
9e1fd300dc
|
[Test] Add test case for customized location of fabric netlists
|
2020-10-12 12:47:58 -06:00 |
|
tangxifan
|
e510e79c12
|
[Flow] Add openfpga shell example script to use fabric netlist option
|
2020-10-12 12:42:43 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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8493345b52
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Merge pull request #105 from LNIS-Projects/dev
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
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2020-10-10 21:43:02 -06:00 |
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tangxifan
|
82e7b159ce
|
[Regression test] Add test case for fracturable LUT using AND gate to switch modes
|
2020-10-10 20:26:41 -06:00 |
|
tangxifan
|
d0014878d5
|
[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
|
tangxifan
|
521accdc88
|
Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
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tangxifan
|
7b12c28e4f
|
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
|
Andrew Lukefahr
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d68427e47b
|
Fixed blif formatting bug
|
2020-10-06 20:46:50 -04:00 |
|
Andrew Lukefahr
|
2d92a1f1af
|
Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
|
tangxifan
|
d4d02ab16a
|
[Regression Test] Move fabric key tests to basic tests
|
2020-09-29 14:22:23 -06:00 |
|
tangxifan
|
ff6570df9d
|
[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
|
2020-09-29 14:19:40 -06:00 |
|
tangxifan
|
4f00d310d3
|
[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
|
tangxifan
|
02ea639959
|
[Regression Test] Add test for fabric key based on multiple region
|
2020-09-29 14:13:38 -06:00 |
|
tangxifan
|
a0d1d68402
|
[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
|
2020-09-29 13:53:41 -06:00 |
|
tangxifan
|
d5c7411399
|
[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
|
2020-09-29 13:50:31 -06:00 |
|
tangxifan
|
5be5835b71
|
[Regression Test] Add multiple region configuration chain test case
|
2020-09-29 13:48:39 -06:00 |
|
tangxifan
|
23449dc5c3
|
[Architecture] Add multiple region configuration chain architecture
|
2020-09-29 13:46:40 -06:00 |
|
tangxifan
|
e09e5fa6c6
|
[Architecture] Update fabric key for region syntax
|
2020-09-27 20:40:37 -06:00 |
|
tangxifan
|
ffd926d686
|
[Architecture] Update external bitstream
|
2020-09-25 21:30:59 -06:00 |
|
tangxifan
|
dcbd6a0614
|
[Architecture] Add lib name to TGATE to test compatibility
|
2020-09-25 21:08:12 -06:00 |
|
tangxifan
|
019208ec0f
|
[Architecture] Reorganize the cell netlists and update architecture files accordingly
|
2020-09-25 11:55:28 -06:00 |
|
tangxifan
|
20d6b2bf84
|
[Architecture] Remove out-of-date Verilog testbench
|
2020-09-24 21:14:13 -06:00 |
|
tangxifan
|
00bf775971
|
[Architecture] Bug fix for adder renaming
|
2020-09-24 20:54:18 -06:00 |
|
tangxifan
|
0a53a719bd
|
[Architecture] Bug fix due to adder renaming
|
2020-09-24 20:42:24 -06:00 |
|
tangxifan
|
e4bfa2ef51
|
[Architecture] Update external bitstream file
|
2020-09-24 20:16:50 -06:00 |
|
tangxifan
|
bd0f0144a0
|
[Architecture] Rename AIB architecture for the new cell naming
|
2020-09-24 20:14:16 -06:00 |
|
tangxifan
|
8edfc79f53
|
[Architecture] Rename AIB cell
|
2020-09-24 20:11:21 -06:00 |
|
tangxifan
|
4ada793c84
|
[Architecture] Adapt openfpga architecture to follow the renamed adder cell
|
2020-09-24 20:09:29 -06:00 |
|
tangxifan
|
53187044e6
|
[Architecture] Rename adder cell
|
2020-09-24 20:07:57 -06:00 |
|
tangxifan
|
4a0a448171
|
[Architecture] Rename openfpga architecture for the I/O cell
|
2020-09-24 19:56:01 -06:00 |
|
tangxifan
|
e0f9547f5b
|
[Architecture] Rework the i/o cell Verilog HDL
|
2020-09-24 19:53:54 -06:00 |
|
tangxifan
|
eb5fd1f44e
|
[Architecture] Bug fix for architectures using scan-chain DFF cell
|
2020-09-24 18:37:25 -06:00 |
|
tangxifan
|
60a14ccbd2
|
[Architecture] Bug fix in architectures that use BRAM
|
2020-09-24 18:20:55 -06:00 |
|
tangxifan
|
d51efd397f
|
[Architecture] Bug fix for architectures using DFF cells
|
2020-09-24 18:02:42 -06:00 |
|
tangxifan
|
3ade6d6ff5
|
[Architecture] Bug fix for dff that are used in data path
|
2020-09-24 17:53:30 -06:00 |
|
tangxifan
|
3e7c88eac8
|
[Architecture] Bug fix in Verilog netlist for scan-chain DFF
|
2020-09-24 17:41:03 -06:00 |
|
tangxifan
|
7494556316
|
[Architecture] Bug fix for scan-chain FF cell
|
2020-09-24 17:38:16 -06:00 |
|
tangxifan
|
54b3f244d3
|
[Architecture] Remove obsolete Verilog netlists
|
2020-09-24 17:35:02 -06:00 |
|
tangxifan
|
49d6863641
|
[Architecture] Bug fix for scan-chain FF cell renaming
|
2020-09-24 17:33:14 -06:00 |
|
tangxifan
|
0a5369f919
|
[Architecture] Adapt all the architecture files to use standard DFF cell
|
2020-09-24 17:26:48 -06:00 |
|
tangxifan
|
19dd3778d9
|
[Architecture] Add test case for memory bank to use both reset and set
|
2020-09-24 17:04:24 -06:00 |
|
tangxifan
|
335f5b78c1
|
[Regression Test] Add test case to use both set and reset for configuration frame
|
2020-09-24 17:02:28 -06:00 |
|
tangxifan
|
2d81ff9012
|
[Regression test] Add configuration chain test case where both set and reset are used
|
2020-09-24 16:59:52 -06:00 |
|
tangxifan
|
fc154b8560
|
[Architecture] Bug fix due to switching CCFF cell
|
2020-09-24 16:45:56 -06:00 |
|
tangxifan
|
79875d5a91
|
[Architecture] Bug fix in the configuration chain arch using both reset and set
|
2020-09-24 15:27:26 -06:00 |
|
tangxifan
|
9cb67e6097
|
[Architecture] Now all the configuration chain architecture use the DFFR cell by default
|
2020-09-24 15:19:37 -06:00 |
|
tangxifan
|
81965e75f6
|
[Architecture] Bug fix in DFF Verilog HDL
|
2020-09-24 14:53:21 -06:00 |
|
tangxifan
|
3b42fe94d6
|
[Architecture] Update external bitstream file
|
2020-09-24 14:41:44 -06:00 |
|
tangxifan
|
7fbccdd102
|
[Regression Tests] Add test cases for configuration chain using different DFF cells
|
2020-09-24 14:34:12 -06:00 |
|
tangxifan
|
178afb3c7f
|
[Architecture] Add configuration chain architectures using different DFF cells
|
2020-09-24 14:23:27 -06:00 |
|
tangxifan
|
98d88dc686
|
[Architecture] Bug fix for vanilla memory organization
|
2020-09-24 14:13:48 -06:00 |
|
tangxifan
|
efad0402c2
|
[Regression Test] Bug fix for CI errors
|
2020-09-24 13:55:41 -06:00 |
|
tangxifan
|
e7906899dd
|
[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
|
2020-09-24 13:53:12 -06:00 |
|
tangxifan
|
e832d806c7
|
[Architecture] Add DFF Verilog netlist using standard naming convention
|
2020-09-24 13:50:59 -06:00 |
|
tangxifan
|
1b13e8ecb1
|
[Architecture] Bug fix in the SRAM Verilog
|
2020-09-24 12:26:13 -06:00 |
|
tangxifan
|
ffd1a72d22
|
[Architecture] Add regression tests for the frame-based configuration using reset and set signals
|
2020-09-24 12:18:26 -06:00 |
|
tangxifan
|
539bb617f9
|
[Architecture] Add reset test case for frame based configuration
|
2020-09-24 12:17:18 -06:00 |
|
tangxifan
|
2add0406a7
|
[Architecture] Update architecture files for new latch naming
|
2020-09-24 12:14:03 -06:00 |
|
tangxifan
|
fde15c4f88
|
[Regression Test] Add test for fast memory bank configuration using set signals
|
2020-09-24 12:13:35 -06:00 |
|
tangxifan
|
7238a2be03
|
[Architecture] Merge latch Verilog HDL to a unique file
|
2020-09-24 11:02:01 -06:00 |
|
tangxifan
|
48083d2276
|
[Regression Test] Adapt fast memory bank test case
|
2020-09-24 10:32:03 -06:00 |
|
tangxifan
|
83971bba41
|
[Architecture] Update cell ports for native SRAM cell
|
2020-09-24 10:31:31 -06:00 |
|
tangxifan
|
186f00edfc
|
[Regression Test] Add test cases for memory bank using different SRAM cells
|
2020-09-24 10:25:03 -06:00 |
|
tangxifan
|
56c9aab190
|
[Architecture] Add architecture to use different SRAM cells for memory bank
|
2020-09-24 10:15:08 -06:00 |
|
tangxifan
|
6bb30ab33c
|
[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support
|
2020-09-24 10:02:51 -06:00 |
|
tangxifan
|
10b6e1dc0d
|
[Architecture] bug fix for active-low
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2020-09-23 23:06:46 -06:00 |
|
tangxifan
|
5b0d451f0f
|
[Regression Test] Add test case for configurable latch with active-low set
|
2020-09-23 23:04:10 -06:00 |
|
tangxifan
|
5d60b4ef8c
|
[Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set
|
2020-09-23 23:02:49 -06:00 |
|
tangxifan
|
8e780635df
|
[Regression Test] Rename test case in CI
|
2020-09-23 22:59:46 -06:00 |
|
tangxifan
|
d0cef68242
|
[Regression test] Add test case for using resetb
|
2020-09-23 22:58:59 -06:00 |
|
tangxifan
|
c7fc0178b0
|
[Architecture] Rename to be consist with other architectures
|
2020-09-23 22:57:06 -06:00 |
|
tangxifan
|
707300a6e4
|
[Architecture] Bug fix for using both reset and set architecture
|
2020-09-23 22:07:40 -06:00 |
|
tangxifan
|
77a1f99564
|
[Architecture] Bug fix for architecture using set only
|
2020-09-23 22:04:24 -06:00 |
|
tangxifan
|
fcf1ff418f
|
[Architecture] Add Verilog for SRAM using set/reset
|
2020-09-23 21:53:38 -06:00 |
|
tangxifan
|
73e59d67af
|
[Architecture] Add test case for fast configuration using set signals
|
2020-09-23 21:50:23 -06:00 |
|
tangxifan
|
349aa79069
|
[Regression test] Add test case for smart fast configuration
|
2020-09-23 21:49:38 -06:00 |
|
tangxifan
|
9331ef941d
|
[Architecture] Add architecture that use both set and reset signals
|
2020-09-23 21:46:04 -06:00 |
|
tangxifan
|
7591060fbd
|
[Architecture] Add configurable latch Verilog designs and assoicated architectures
|
2020-09-23 21:45:06 -06:00 |
|
tangxifan
|
8fa4fa1125
|
[Architecture] Add openfpga architecture using set signals for configurable latch
|
2020-09-23 21:39:31 -06:00 |
|
tangxifan
|
05c2e652a4
|
[Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol
|
2020-09-23 20:44:06 -06:00 |
|
tangxifan
|
2869eae8a9
|
[Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol
|
2020-09-23 20:43:15 -06:00 |
|
tangxifan
|
fc60b18191
|
[Architecture] Now a regular flip-flop can be used in frame-based configuration
|
2020-09-23 20:41:49 -06:00 |
|
tangxifan
|
8e4e66038a
|
[Architecture] Bug fix for standalone memory
|
2020-09-23 19:32:48 -06:00 |
|
tangxifan
|
129caea38c
|
[Architecture] Patch configurable latch Verilog HDL with resetb
|
2020-09-23 18:30:48 -06:00 |
|
tangxifan
|
1864b080a2
|
[Architecture] Bug fix in configurable latch Verilog HDL
|
2020-09-23 18:28:45 -06:00 |
|
tangxifan
|
ebb866d04a
|
[Architecture] Patch frame based using ccff
|
2020-09-23 18:04:14 -06:00 |
|
tangxifan
|
906191e931
|
[Architecture] Use strict latch Verilog HDL in frame-based procotol
|
2020-09-23 17:58:13 -06:00 |
|
tangxifan
|
645db17168
|
[Architecture] Patch DFF Verilog HDL
|
2020-09-23 17:52:59 -06:00 |
|
tangxifan
|
092ada39f4
|
[Architecture] Add Verilog HDL for DFF with write enable
|
2020-09-23 17:49:30 -06:00 |
|
tangxifan
|
ad385c6d69
|
[Regression Test] Add test case for using SRAM cell in frame-based configuration
|
2020-09-23 17:39:36 -06:00 |
|
tangxifan
|
1a2c66f07d
|
[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
|
2020-09-23 17:34:49 -06:00 |
|
tangxifan
|
a3c982a83f
|
[Architecture] Patch the openfpga architecture using active-low configurable latch
|
2020-09-23 17:27:16 -06:00 |
|
tangxifan
|
f23c25e123
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[Regression Test] Add test case for configurable latch with active-low reset
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2020-09-23 17:25:17 -06:00 |
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tangxifan
|
a94c2655c2
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[Architecture] Patch Verilog HDL for configurable latch
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2020-09-23 17:21:30 -06:00 |
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tangxifan
|
893859be37
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[Architecture] Add openfpga architecture using active-low configurable latch
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2020-09-23 17:21:00 -06:00 |
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tangxifan
|
b242ab79bd
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[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset
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2020-09-23 17:19:02 -06:00 |
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tangxifan
|
149d5b20bd
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[Regression Test] Add test case for fixed device support
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2020-09-23 16:47:11 -06:00 |
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tangxifan
|
c92cf71891
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[Regression Test] Add a new template script for fixed device support
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2020-09-23 16:46:41 -06:00 |
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tangxifan
|
3350695806
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[Regression test] Add test case for pattern based local routing architecture
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2020-09-23 16:06:47 -06:00 |
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tangxifan
|
1aab691e9d
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[Architecture] Add openfpga architecture using pattern based local routing
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2020-09-23 16:06:16 -06:00 |
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tangxifan
|
951a47b19c
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[Architecture] Add k4 series architecture using pattern-based local routing
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2020-09-23 16:05:39 -06:00 |
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tangxifan
|
7729f671ab
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[Regression Tests] Remove deadlink
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2020-09-22 18:35:41 -06:00 |
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tangxifan
|
51c0319657
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[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:54 -06:00 |
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tangxifan
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70b8b02f74
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[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:11 -06:00 |
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tangxifan
|
72749be4bd
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[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:31:34 -06:00 |
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tangxifan
|
61bcbaafd8
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[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
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2020-09-22 15:15:19 -06:00 |
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tangxifan
|
3d1f49fb2f
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[Regression Test] Add testcase for k4n4 with multiple segments
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2020-09-22 12:47:41 -06:00 |
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tangxifan
|
13df6c1c21
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[Architecture] Add openfpga architecture for k4n4 using multiple segments
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2020-09-22 12:36:11 -06:00 |