Ganesh Gore
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acf983a110
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Forced unused bits to default 0
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2023-10-16 21:01:29 -07:00 |
tangxifan
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7ba6795fe2
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[core] fixed a bug
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2023-10-06 18:50:26 -07:00 |
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tangxifan
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83ef35b2da
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[core] fixed a bug
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2023-10-06 18:47:20 -07:00 |
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tangxifan
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3440768840
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[core] code format
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2023-10-06 18:37:54 -07:00 |
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tangxifan
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e102c9bddc
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[core] fixed a bug
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2023-10-06 18:37:28 -07:00 |
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tangxifan
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93cbbf2045
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[core] code format
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2023-10-06 18:20:55 -07:00 |
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tangxifan
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b07111497c
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[core] enable options in xml writers
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2023-10-06 18:20:17 -07:00 |
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tangxifan
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ae63c9d441
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[core] code format
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2023-10-06 17:28:25 -07:00 |
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tangxifan
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1e8bf1cece
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[core] deploy options
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2023-10-06 17:28:02 -07:00 |
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tangxifan
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f30663f708
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[core] code format
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2023-10-06 14:08:09 -07:00 |
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tangxifan
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108bbad8d4
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[core] syntax
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2023-10-06 14:07:44 -07:00 |
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tangxifan
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80856f1b70
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[core] adding new options and rewrite options for bitfile writer
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2023-10-06 13:54:29 -07:00 |
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tangxifan
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a15db83267
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[core] code format
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2023-09-26 11:41:11 -07:00 |
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tangxifan
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ea91182216
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[core] check option conflicts
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2023-09-26 11:40:42 -07:00 |
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tangxifan
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c4bce834e4
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[core] code format
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2023-09-25 22:34:39 -07:00 |
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tangxifan
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5aa206e616
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[core] fixed some bugs
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2023-09-25 22:27:24 -07:00 |
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tangxifan
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1624dc9764
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[core] code format
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2023-09-25 21:13:50 -07:00 |
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tangxifan
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76f446caec
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[core] fixed a bug
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2023-09-25 21:13:11 -07:00 |
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tangxifan
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dbd466cdec
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[core] now support tile port merge
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2023-09-25 18:16:24 -07:00 |
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tangxifan
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3adf81046a
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[core] code format
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2023-09-25 17:22:26 -07:00 |
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tangxifan
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5e269e8bc4
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[core] support port merging at grid modules
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2023-09-25 17:21:58 -07:00 |
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tangxifan
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edb0e687f1
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[core] code format
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2023-09-23 12:15:53 -07:00 |
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tangxifan
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11de8965a8
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[core] fixed some bugs
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2023-09-23 12:15:31 -07:00 |
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tangxifan
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860cfd53c6
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[core] fixed critical bugs in renaming modules
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2023-09-23 11:51:31 -07:00 |
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tangxifan
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ca3617a029
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[core] code format
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2023-09-20 20:37:27 -07:00 |
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tangxifan
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1ef38b6a64
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[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
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2023-09-20 20:34:21 -07:00 |
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tangxifan
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c105b56bf0
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[core] code format
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2023-09-18 23:31:27 -07:00 |
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tangxifan
|
43fd08a3fe
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[core] fixed a bug
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2023-09-18 23:31:09 -07:00 |
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tangxifan
|
4d11f73471
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[core] fixed a bug
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2023-09-18 20:43:15 -07:00 |
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tangxifan
|
a1e609c901
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[core] fixed some bugs
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2023-09-18 16:39:07 -07:00 |
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tangxifan
|
1daabb990e
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[core] code format
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2023-09-18 15:35:13 -07:00 |
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tangxifan
|
110301a2e4
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[core] now tile port naming can follow index
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2023-09-18 15:34:40 -07:00 |
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tangxifan
|
e46e58527a
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[core] code format
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2023-09-17 23:16:38 -07:00 |
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tangxifan
|
eeb1bd6662
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[core] fixed some bugs
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2023-09-17 23:16:15 -07:00 |
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tangxifan
|
c6175aa514
|
[core] code format
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2023-09-17 22:37:48 -07:00 |
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tangxifan
|
ef97127c63
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
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c14277a674
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[core] fixing bugs
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2023-09-17 17:57:57 -07:00 |
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tangxifan
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d5152dc16d
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[core] fixed a bug on the hierarchy writer
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2023-09-17 17:42:25 -07:00 |
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tangxifan
|
4ccb4737be
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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tangxifan
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f79da76656
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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tangxifan
|
72a3c05747
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[core] code format
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2023-09-17 13:29:30 -07:00 |
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tangxifan
|
ccd4c1861b
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[core] developing new command to write module naming rules
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2023-09-16 19:37:06 -07:00 |
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tangxifan
|
32df673d72
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[core] code format
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2023-09-16 18:35:33 -07:00 |
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tangxifan
|
200ecad74a
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[core] fixed bugs in bitgen
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2023-09-16 18:34:55 -07:00 |
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tangxifan
|
058bb1ef51
|
[core] code format
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2023-09-16 18:24:38 -07:00 |
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tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
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tangxifan
|
d61d88f12e
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[core] fixed some bugs in verilog writer due to renaming
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2023-09-16 18:13:22 -07:00 |
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tangxifan
|
37573abc22
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[core] code format
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2023-09-15 23:32:40 -07:00 |
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tangxifan
|
c85c64eb5a
|
[core] syntax
|
2023-09-15 23:30:34 -07:00 |
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tangxifan
|
bc407e5d69
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[core] code complete for rename modules
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2023-09-15 23:22:31 -07:00 |