Commit Graph

1001 Commits

Author SHA1 Message Date
Tim Newsome 6112814f45 Fix build.
Change-Id: I12f90bed9a1fe470ef3d49f9219227ee0de928b6
2021-10-05 17:47:17 -07:00
Tim Newsome 1775341ef8 Merge branch 'master' into from_upstream
Conflicts:
	src/jtag/drivers/remote_bitbang.c
	src/rtos/rtos_standard_stackings.c
	src/rtos/rtos_standard_stackings.h
	src/target/breakpoints.c
	src/target/riscv/riscv.c
	src/target/target.c

Change-Id: Ia6fcba3d43be8ea31728f3bcc2be6cb7e3ccc5c5
2021-10-05 17:46:02 -07:00
Tim Newsome 5215fc52ab
Fix flashing on HiFive1. (#649)
Broken by #645. It probably broke some other uses as well, but it was
reported (and easy to reproduce) as an issue with flashing.

Change-Id: Ic1b579c1361442479ced14156102ce68ab232396
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-05 11:17:24 -07:00
Tim Newsome f139080376
Clear type 6 triggers on connecting. (#648)
I missed this when I first add mcontrol6 support.

Change-Id: I1a2706c7ea3a6757ed5083091cd2c764a8b0267c
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-05 10:03:19 -07:00
Yasushi SHOJI 05752557dd helper: Remove src/helper from include dirs
The header files under src/helper/ can currently be included with
either

    #include <bits.h>
    or
    #include <helper/bits.h>

This is because we specify both "src/" and "src/helper/" directories
as include directories.  Some files name under "src/helper/", such as
types.h, log.h, and util.h are too generic and could be ambiguous
depending on the search path.

This commit remove "src/helper/" from our include dir and make C files
include explicitly.

Change-Id: I38fc9b96ba01a513d4a72757d40007e21b502f25
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6507
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-10-02 13:18:15 +00:00
Tim Newsome 3858878d38
Properly cache s0/s1 (#645)
* WIP on register caching.

So we don't have to save/restore S0 all the time.

Change-Id: I9d83a24dbd92a325213f2b25eebc9ede9dca2868

* Seems to work for RV32.

Change-Id: Ide620faa5dfef4f39c3146e094787ea28d041327

* Use caching everywhere.

Change-Id: I0de249437589e1f49811f34c12726528c045c74f

* Getting closer...

Change-Id: I532455f1e416723b79eecc7d33ec6407ccb8e33c

* All spike tests pass again.

Running all tests now takes 2m54s compared to 3m0s. That's probably not
the thing to measure, since the goal is to improve interactive
performance, while the tests do all kinds of other stuff (like sleep,
and start spike, etc.).

Change-Id: Ic7d944454a64b2baf6e6028debb4a1ba896834d8

* Save s0/s1 during examine.

Change-Id: I4795180e3b04d01433a11d4a0ccb38c35074cc44
Signed-off-by: Tim Newsome <tim@sifive.com>

* Check flush registers result.

Change-Id: I8350c4198cb41881e1143816698aed677a312111
Signed-off-by: Tim Newsome <tim@sifive.com>

* Fix upstream style regression.

Change-Id: I4cc7034151ba62fa51aea77e44b0cad9b9b97876
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-09-23 15:07:38 -07:00
Tim Newsome a1146731a8 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/fespi.c
	src/jtag/drivers/ftdi.c
	src/rtos/FreeRTOS.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/rtos/rtos_ecos_stackings.c
	src/rtos/rtos_embkernel_stackings.c
	src/rtos/rtos_standard_stackings.c
	src/rtos/rtos_standard_stackings.h
	src/rtos/rtos_ucos_iii_stackings.c
	src/server/gdb_server.c
	src/server/server.c
	src/target/riscv/riscv-013.c
	src/target/target.c
	src/target/target.h

Change-Id: If0924a3e799260c33fae5feb85975b1273b45a0f
2021-08-30 15:03:59 -07:00
Antonio Borneo 3917823187 openocd: remove NULL comparisons with checkpatch [1/2]
Patch generated automatically through the new checkpatch with
flags "--types COMPARISON_TO_NULL --fix-inplace".
This only fixes the comparisons
	if (symbol == NULL)
	if (symbol != NULL)
The case of NULL on the left side of the comparison is not tested.

Some automatic fix is incorrect and has been massaged by hands:
	-	if (*psig == NULL)
	+	if (*!psig)
changed as
	+	if (!*psig)

Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6351
Tested-by: jenkins
2021-07-24 10:38:00 +01:00
Antonio Borneo 08ee7bb982 openocd: fix simple cases of NULL comparison
There are more than 1000 NULL comparisons to be aligned to the
coding style.
For recurrent NULL comparison it's preferable using trivial
scripts in order to minimize the review effort.

Patch generated automatically with the command:
	sed -i PATTERN $(find src/ -type f)
where PATTERN is in the list:
	's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
	's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
	's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g'

	's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g'
	's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g'
	's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g'

	's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g'
	's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g'
	's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g'

	's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g'
	's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g'
	's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g'

Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6350
Tested-by: jenkins
2021-07-24 10:37:49 +01:00
Tim Newsome 90d1d490c1
Add support for hypervisor bits. (#631)
Expose them in the virtual priv register, and set them on mcontrol6
hardware triggers. I have no good way to test this right now, so it's
all untested. But this change doesn't break anything, at least.

Change-Id: I0343a6169a0b2b1f0cc0abf687c6bdc560d99b1b
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-07-23 14:42:05 -07:00
Tim Newsome 2ae1e88178
Fix clobbering s2 in read_memory_progbuf(increment=0) (#634)
Fixes #632.

Change-Id: Ic884823faf67749f1ac8fbd91fe67ff9ebdd8fd0
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-07-23 12:01:41 -07:00
Antonio Borneo 20b29b7767 openocd: manually fix Yoda conditions
Fix the remaining Yoda conditions, detected by checkpatch but not
fixed automatically.

While there, apply minor style changes.

Change-Id: I6e1978b89c4d56a20aceaeb2b52968eb6384432a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6356
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:55:43 +01:00
Tim Newsome 5edbbb4827 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/nrf5.c
	src/flash/nor/xcf.c
	src/jtag/drivers/remote_bitbang.c
	src/rtos/FreeRTOS.c
	src/rtos/zephyr.c
	src/target/cortex_a.c
	src/target/cortex_a.h
	src/target/cortex_m.c
	src/target/riscv/riscv.c

Change-Id: I80b0a33b40c06c229d20fe34e04d6322da83326d
2021-06-30 14:56:44 -07:00
Jesse Sheridan 0ef5144c32 target/riscv: Implement get_gdb_arch()
Change-Id: I5f4ab5243104df41031950682f688f2448a09b17
Signed-off-by: Jesse Sheridan <jesse.sheridan@gmail.com>
Reviewed-on: http://openocd.zylin.com/6322
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26 14:38:59 +01:00
Marc Schink da770c4fbb Use boolean argument for register_get_by_name()
Change-Id: Ie913630c6ab3b600532d8e375e2fc11ca202cf5e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6295
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18 23:14:27 +01:00
Tim Newsome f4950b7c5d
From upstream (#620)
* cortex_m: use unsigned int for FPB and DWT quantifiers

related quantifiers are:
 - fp_num_lit
 - fp_num_code
 - dwt_num_comp
 - dwt_comp_available

Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6185
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* telnet: allow hiding selected commands during auto-completion

We have TCL procedure and commands that we do not want to show in
the list of auto-completion. E.g. TCL wrappers for deprecated
commands, internal procedures that are not supposed to be exposed
to user, or even commands that the user decides to hide.

Create a TCL procedure to be called by telnet auto-complete code
in place of the hard-coded TCL command. The procedure will run the
same command and will filter-out the unwanted command names.

Initialize the list of commands to be filtered-out with the name
of the TCL procedure above, as it is considered as internal.

Change-Id: I2d83bbf8194502368c589c85cccb617e69128c69
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6194
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* telnet/auto-complete: hide deprecated and internal commands

For both:
- TCL proc that redirect deprecated commands to the new commands,
- TCL proc used internally and not supposed to be exposed to user,
add their name to the list of commands that should be hide by the
telnet auto-complete.

Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6195
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* startup.tcl: prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Modify the script startup.tcl compiled-in OpenOCD binary to comply
with the new jimtcl.

Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6158
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Enclose within double quote the argument of 'expr' when there is
the need to concatenate strings.

Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6160
Tested-by: jenkins

* tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/stm8: Make 'stm8_command_handlers' static

Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6200
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/riscv: Change 'authdata_read' output

Use a constant output length and remove the line break to make the
authentication data easier to parse.

Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6199
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* Enable adapter "Bus Pirate" by default.

The Bus Pirate is now listed in the "OpenOCD configuration summary" too.

Change-Id: Ieb7bf9134af456ebe9803f3108a243204fb2a62d
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/5637
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* coding-style: additional style for C code

To improve readability and to push more uniform code style.

Prefer 'if (false) {...}' for unused code so it get checked by the
compiler.
Define preferred indentation for 'switch' statement.
Require balanced brackets in 'if/else'.
Report the max line length.
Report the formatting strings for stdint/inttypes types.
Report the type 'target_addr_t'.
Prefer 'unsigned int' to 'unsigned'.

Change-Id: I0192a4ed298f6c6c432764fdd156cffd4b13fc89
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6203
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Marc Schink <dev@zapb.de>

* Add IPDBG JtagHost functionality to OpenOCD

IPDBG are utilities to debug IP-cores. It uses JTAG for
transport to/from the FPGA. The different UIs use TCP/IP
as transport. The JtagHost makes the bridge between these
two.

Comparable to the bridge between GDB and the in-circuit-
debugging-unit of a micro controller.

Change-Id: Ib1bc10dcbd4ea426e492bb7b2d85c1ed1b7a8d5a
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: http://openocd.zylin.com/5938
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* flash/nor/xcf: Do not use 'Yoda conditions'

Change-Id: I17308f5237338ce468e5b86289a0634429deaaa9
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6201
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cortex_m: add armv8m special registers

Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* rtos: Add support for Zephyr RTOS

With this patch, the Zephyr[1] RTOS is supported by OpenOCD.

As usual with support for other RTOSes, Zephyr must be compiled with
the DEBUG_THREAD_INFO option. This will generate some symbols
with information needed in order to build the list of threads.

The current implementation is limited to Zephyr running on ARM
Cortex-M processors. This is the only ARM variant supported by Zephyr
at the moment and is used on most of the officially supported boards.

[1] https://www.zephyrproject.org/

Change-Id: I22afdbec91562f3a22cf5b88cd4ea3a7a59ba0b4
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Signed-off-by: Daniel Glöckner <dg@emlix.com>
Reviewed-on: http://openocd.zylin.com/4988
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/armv7m.h: [style] replace tab with space between variable type and name

Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6230
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* server: gdb_server: Add colon for target extended-remote

Both GDB commands "target remote" and "target extended-remote" require
to have ":" right before port number.

e.g.
    (gdb) target extended-remote :3333

Add ":" to the warning message so that users can copy & past it.

Change-Id: Id6d8ec1e4dfd3c12cb7f3b314064f2c35fa7ab55
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6237
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* jimtcl: restrict memory leak workaround on Linux only

The workaround for jimtcl 0.80 in commit 36ae487ed0 ("jimtcl:
add temporary workaround for memory leak in jimtcl 0.80") issues a
compile time error on macOS:
	../src/helper/command.c:157:22: error: aliases are not
	supported on darwin
	__attribute__((weak, alias("workaround_createcommand")));
The OS is x86_64-apple-darwin19.6.0 and the compiler used is
x86_64-apple-darwin13.4.0-clang.

Restrict the workaround on Linux host only. The fix for 'expr'
syntax change is already merged and the workaround will be dropped
soon.

Change-Id: I925109a9c57c05f8c95b70bc7d6604eb1172cd79
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Adam Jeliński <ajelinski@users.sourceforge.net>
Fixes: 36ae487ed0 ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80")
Fixes: https://sourceforge.net/p/openocd/tickets/304/
Reviewed-on: http://openocd.zylin.com/6241
Tested-by: jenkins

* target/armv7m: fix static analyzer warning

Despite of assert(is_packed) clang static analyser complains on use
of the uninitialized offset variable.

Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings
	src/target/armv7m.c: In function ‘armv7m_read_core_reg’:
	src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used
	    uninitialized in this function [-Werror=maybe-uninitialized]

It happens because mingw32 defines assert() without the attribute
"noreturn", whatever NDEBUG is defined or not.

Replace assert(is_packed) by if (is_packed) conditional and call
assert(false) in the else branch.

Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6256
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>

* cmsis_dap: fix build on macOS

Compile fails with error:
	src/jtag/drivers/cmsis_dap.c:683:28: error: format specifies type
	    'unsigned char' but the argument has type 'int' [-Werror,-Wformat]
	                         " received 0x%" PRIx8, CMD_DAP_TFER, resp[0]);
	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~

Fix the format specifier.

Change-Id: I0a5a1a35452d634019989d14d849501fb8a7e93a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6255
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* cortex_m: do not perform soft_reset_halt on targets without VECTRESET

Change-Id: Ib3df457e0afe4e342c82ad1af25e03aad6979d87
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* cortex_m: fix VECTRESET detection for ARMv6-M cores

VECTRESET check should be done after verifying if the core is an ARMv6-M core,
and not before that.

Fixes: 2dc9c1df81 ("cortex_m: [FIX] ARMv8-M does not support VECTRESET")
Change-Id: I8306affd332b3a35cea69bba39ef24ca71244273
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6232
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/arm_dpm: rename 'wp_pc' as 'wp_addr'

The field 'wp_pc' was originally introduced in commit 55eeea7fce
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.

Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.

Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>

* target/aarch64: fix watchpoint management

The early documentation for armv8a report the debug register WFAR
as containing the address of the instruction that triggered the
watchpoint. More recent documentation report the register EDWAR as
containing the data memory address that triggered the watchpoint.

The name of macros CPUV8_DBG_WFAR0 and CPUV8_DBG_WFAR1 is not
correct as they point to the debug register EDWAR, so reading such
register returns directly the data memory address that triggered
the watchpoint. The code incorrectly passes this address value to
the function armv8_dpm_report_wfar(); this function is supposed to
adjust the PC value, decrementing it to remove the effects of the
CPU pipeline. This pipeline offset, that has no meaning on the
value in EDWAR, caused commit 651b861d5d ("target/aarch64: Add
watchpoint support") to add back the offset while comparing the
address with the watchpoint enabled.

The upper 32 bits of EDWAR are not valid in aarch32 mode and have
to be ignored.

Rename CPUV8_DBG_WFAR0/1 as CPUV8_DBG_EDWAR0/1.
Remove the function armv8_dpm_report_wfar().
Remove the offset while searching the matching watchpoint.
Ignore the upper 32 bits of EDWAR in aarch32 mode.
Fix a comment and the LOG text.

Change-Id: I7cbdbeb766fa18e31cc72be098ca2bc501877ed1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6205
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>

* flash/stm32l4x: add missing break statement

this is not a bug fix, this for loop will issue only one match
adding the break will save unnecessary more loops.

Change-Id: Ic1484ea8cdea1b284eb570f9e3e7818e07daf5cd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6248
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins

* github/action: create a permanent 'latest' release

this commit extends the existing snapshot action to create a release named
'latest' with the built binaries for windows.

this 'latest' release will be updated after every push to github.

Change-Id: I75a64c598169241743add3ac9aa7a0337fbab7f2
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6127
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* tcl/rp2040: remove empty line at end of file

Change-Id: I212a96b77282b151a8ecbd46a6436e2bbbda4161
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6221
Tested-by: jenkins

* tcl: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.
While there, fix one indentation.

Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6214
Tested-by: jenkins

* flash: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: Ia5f134c91beb483fd865df9e4877e0ec3e789478
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6215
Tested-by: jenkins

* jtag: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I101c76a638805d77c1ff356cf0f027552389e5d3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6216
Tested-by: jenkins

* target: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I548581247db72e683249749d1b8725035530b06e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6217
Tested-by: jenkins

* openocd: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I7b4cae1798ff5ea048fcbc671a397af763fdc605
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6218
Tested-by: jenkins

* Document the buspirate interface driver.

Change-Id: Iaff13fc5187041a840f4f00eb6b4ee52880cf47e
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6231
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Warn on undefined preprocessor symbols

Preprocessor directives like "#if SYMBOL" silently replace undefined or
misspelt symbols with 0, which makes configuration bugs hard to spot.
Compiler flag "-Wundef" prevents such errors.

Change-Id: I91b7ba2db02ef0c3c452d334601c53aebda4660e
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6238
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Remove compatibility macros m4_ifblank and m4_ifnblank

They are at least since Autoconf 2.67 present,
and we are requiring version 2.69.

Change-Id: I41b33d4ebe02198f03cdddcc4a3c1beedd993d78
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* configure.ac: use a separate folder for Autoconf-generated files

Autoconf generates several files in root folder of the project.
Keep the root folder cleaner by specifying subfolder 'build-aux'.
Align .gitignore accordingly.

Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Change-Id: Ied87faba495d9eeb8f98e78c2e2b7e7e596febfb
Reviewed-on: http://openocd.zylin.com/6236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* helper/command: silent debug msg on command register/unregister

Commit e216186fab ("helper/command: register full-name commands
in jim") and commit a7d68878e4 ("helper/command: unregister
commands through their full-name") introduce a LOG_DEBUG() message
each for command registration and unregistration.
The messages above are quite noisy and pollute the log when
debug_level is 3 or higher.
They can be useful to debug the command registration logic, but
for the other debug activities on OpenOCD are just noisy.
Already commit a03ac1ba30 ("helper/command: disable logging of
registered commands [RFC]") was merged to silent the first case
that is now back with additional logs.

Silent both log messages.
Use 'if (false)' to silent them, making easy to re-enable it when
or if someone needs it.

Change-Id: Id8a067e60e822d4ecbddcb036d081298f7e6181f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6220
Tested-by: jenkins

* mem_ap: fix target arch_info type

The target mem_ap appears as an ARM target, thus it allows the
execution of ARM specific commands causing the crash of OpenOCD.
E.g. 'arm mrc ...' can be executed and segfaults.

Replace the incorrect ARM magic number with a dedicated one.
While there, remove the 'struct arm', that is now holding only the
mem_ap's dap, and replace it with a pointer to the dap.

Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6213
Tested-by: jenkins

* riscv: drop unused variable

The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6257
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* riscv: replace macro DIM() with ARRAY_SIZE()

OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6258
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* target/zynqmp : Add AXI AP access port

The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.

Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* drivers/versaloon: use ARRAY_SIZE()

Replace the custom macro dimof() with the OpenOCD macro
ARRAY_SIZE().

Change-Id: I2fe638444f6c16f2a78c1fd558b21550f76282d6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6259
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>

* openocd: use macro ARRAY_SIZE()

There are still few cases where the macro ARRAY_SIZE() should be
used in place of custom code.

Use ARRAY_SIZE() whenever possible.

Change-Id: Iba0127a02357bc704fe639e08562a4f9aa7011df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6260
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins

* rtos: use ARRAY_SIZE() and simplify rtos_type.create()

Use the existing macro ARRAY_SIZE().
Rewrite the functions rtos_type.create() to simplify the logic.

Change-Id: I8833354767045d1642801d26944c9087a77add00
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6261
Tested-by: jenkins

* tcl: remove remaining deprecated commands

There are still few adapter_khz, ftdi_location, jtag_nsrst_delay
and xds110_serial strolling around ...

Change-Id: I3e8503dcc3875e3c92e6536f3d455a5e448d51ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6270
Tested-by: jenkins

* help text: remove trailing space

Some help text end with a useless space character.
Remove it.

Change-Id: I397e1194fac8042f0fab694222f925f906716de3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6222
Tested-by: jenkins

* help: fix line size in 'usage' output

The implementation of command 'usage' is broken while checking the
line limit of 76 chars per line (e.g. 'usage load_image') and the
line wrapping is not correct. The same broken code is used for the
first output line of command 'help' too.

When call command_help_show_wrap(), include the command's name in
the string so the whole text would be wrapped.

Change-Id: Idece01ce54994db7e851d8522435ff764b11f3ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6223
Tested-by: jenkins

* LICENSES: Add the MIT license

Add the full text of the MIT license to the kernel tree.  It was copied
directly from:

  https://spdx.org/licenses/MIT.html#licenseText

Add the required tags for reference and tooling.

Change-Id: I94a5dea5ced6421809ea2a3448f8dda19a93f5c9
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6219
Tested-by: jenkins

* stlink: add comment of firmware version for each flag bit

Change-Id: I7f7c7b9c9cfd88125f82662ed864a2c0715140b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6211
Tested-by: jenkins

* stlink: reorder the flag macro by firmware release

The corresponding bit for each macro is changed, but this is not
relevant in the code.

Change-Id: I7039464f5a3d55d008208f44952aadeb815bd5a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6212
Tested-by: jenkins

* tcl/board: Add ST NUCLEO-8S208RB

Change-Id: I384c6ad9b4cbabbc004160677f600d8c4bd3eb71
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6268
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/arm_adi_v5: Fix clear sticky overrun flag during replay of commands

When a WAIT occurs the commands after the WAIT are replayed and the
STICKYORUN is cleared. However if another WAIT occurs during the
command replay, the command itself is resent but the STICKYORUN bit
shall also be cleared. If this is not done, the MEM-AP hangs.

Change-Id: I14e8340cd5d8f58f4de31509da96cfa2ecb630d1
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6278
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: add support for watchpoints

The current implementation of OpenOCD does not support watchpoints for
cortex_a architecture. So, I replaced the add_watchpoint and
remove_watchpoint with the specific implementation for the
cortex a and using the breakpoint implementation and the arm
documentation [1] as reference. In particular, I have made the
following changes:

* added the following functions

- cortex_a_add_watchpoint
  This wrapper function check whether there are any watchpoint
  available on the target device by calling cortex_a_set_watchpoint.

- cortex_a_set_watchpoint
  This function is responsible for settings the watchpoint register
  pair. In particular, it sets the WVR and the WCR registers with
  the cortex_a_dap command.

- cortex_a_remove_watchpoint
  This wrapper function the selected watchpoint on the target device
  by calling cortex_a_unset_watchpoint.

- cortex_a_unset_watchpoint
  This function sets both the WVR and the WCR registers to zero, thus
  unsetting the watchpoint.

[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html

Change-Id: I86611dab474cb84836662af572b17636dc68e282
Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-on: http://openocd.zylin.com/3913
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins

* target/cortex_a: fix number of watchpoints

Decrement the available watchpoints only when succeed setting it.
Initialize the available watchpoint with the correct value.

Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6196
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytes

Use byte address select for 1 and 2 bytes length.
Use normal mode for 4 bytes length.

Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6197
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: fix memory leak on watchpoints

The memory allocated to hold the watchpoints is not freed at
OpenOCD exit.

Free the watchpoint memory at OpenOCD exit.

Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6210
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* helper/jim-nvp: comply with coding style [1/2]

The helper jim-nvp does not comply with OpenOCD coding style due
to typedef of struct and CamelCase symbol names.
While it's trivial fixing the helper and all its current use in
the code, changing these APIs will potentially break a number of
patches pending in gerrit. Gerrit will not trigger any alert, but
the code will generate compile error after the merge.

Add the compile flag "-Wno-error=deprecated-declarations" to keep
as warning (not as error) the use of "deprecated" functions and
types.
Rename all the CamelCase symbols is lowercase and provide struct
prototypes in place of the typedef.
Add a DEPRECATED section to 'jim-nvp.h' where the old CamelCase
symbols and the old typedef are re-declared with compile attribute
'deprecated'.

With this change OpenOCD compiles, but generates warnings.
The remaining changes allover OpenOCD code will be fixed in a
separate patch for easier review.

The patches merged later that still use the old deprecated API
will compile with warnings. This will permit to identify and fix
these cases.

Change-Id: I786385d0f662dbb1be5be313ae42623156d68ce5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6183
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* helper/jim-nvp: comply with coding style [2/2]

With the API fixed to comply with OpenOCD coding style, fix all
the references in the code.

Patch generated automatically with the script below.
The list is in reverse order to replace a common prefix after the
replacement of the symbols with the same prefix.

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
(cat << EOF
Jim_SetResult_NvpUnknown         jim_set_result_nvp_unknown
Jim_Nvp_value2name_simple        jim_nvp_value2name_simple
Jim_Nvp_value2name_obj           jim_nvp_value2name_obj
Jim_Nvp_value2name               jim_nvp_value2name
Jim_Nvp_name2value_simple        jim_nvp_name2value_simple
Jim_Nvp_name2value_obj_nocase    jim_nvp_name2value_obj_nocase
Jim_Nvp_name2value_obj           jim_nvp_name2value_obj
Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple
Jim_Nvp_name2value_nocase        jim_nvp_name2value_nocase
Jim_Nvp_name2value               jim_nvp_name2value
Jim_Nvp                        struct jim_nvp
Jim_GetOpt_Wide                  jim_getopt_wide
Jim_GetOpt_String                jim_getopt_string
Jim_GetOpt_Setup                 jim_getopt_setup
Jim_GetOpt_Obj                   jim_getopt_obj
Jim_GetOpt_NvpUnknown            jim_getopt_nvp_unknown
Jim_GetOpt_Nvp                   jim_getopt_nvp
Jim_GetOpt_Enum                  jim_getopt_enum
Jim_GetOpt_Double                jim_getopt_double
Jim_GetOpt_Debug                 jim_getopt_debug
Jim_GetOptInfo                 struct jim_getopt_info
Jim_GetNvp                       jim_get_nvp
Jim_Debug_ArgvString             jim_debug_argv_string
EOF
) | while read a b; do
    sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? )
done
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6184
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins

* server/telnet: fix autocomplete for jimtcl commands

Current autocomplete filters-out some command reported by "info
commands". One of the filter rule concerns the command's private
data.
Every command registered by OpenOCD has its 'struct command' as
private data.

By ignoring commands without private data, we loose several TCL
commands registered by jimtcl, e.g. 'foreach', 'llength'.

By assuming that every command with non-NULL private data has
'struct command' as private data, we risk at best to access
inconsistent data, at worst to trigger a segmentation fault.

Export the already available functions:
- to check if a command has been registered by OpenOCD and
- to get the private data.
While there, rename jimcmd_is_ocd_command() as
jimcmd_is_oocd_command().
Don't filter-out jimtcl commands with no private data.
Check the private data only on OpenOCD commands.

Change-Id: Ib5bf8d2bc5c12440c0cfae438f637c38724a79b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6282
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* helper/list.h: align file to Linux v5.12

Main improvement is in the doxygen comments.
Minimize the delta with kernel file.
Skip the functions hlist_unhashed_lockless() and
__list_del_clearprev() that are relevant only in kernel.
Remove gcc extension "omitted conditional operand".

Change-Id: I2e9ddb54cfe2fa5f7cf18f44726acd144e1f98b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6276
Reviewed-by: <rdiezmail-openocd@yahoo.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

* contrib: add an example of using list.h

Change-Id: Ic3d399d7ad2e4d10677cf78d64968040941b74e5
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6280
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* helper/list.h: add mention to the example in contrib

Without such reference, it could be difficult to find the example.

Change-Id: Ia9ffb06bc1a45446c2c7b53197ab3400e1d8a9e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6281
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* tcl/target/stm32f4x: fix hardcoded chip name

Fixes: c945d6e616 ("tcl/target: start using the new TPIU/SWO support")
Change-Id: I4543c9a204f7b4b3b14e6eabc5042653106aff0e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6277
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

* Makefile: add special target .DELETE_ON_ERROR

The special .DELETE_ON_ERROR deletes the target file on recipe error.
Otherwise, an incomplete output file may be considered up to date
the next time around. .DELETE_ON_ERROR provides reasonable
protection at virtually no cost.

Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Change-Id: I67dca47ae5ddf3786993c87b9991b3046a85f00b
Reviewed-on: http://openocd.zylin.com/6235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: Log both incoming and outgoing GDB packets

- Made sure that also outgoing GDB packets are logged,
  not only the incoming ones.

- Improved the treatment of non-printable characters
  in the packets to make it more robust.

Prior to this change:

- Outgoing packets were not printed unless OpenOCD was
  re-compiled with _DEBUG_GDB_IO_.
- Non-prinable characters were only treated in incoming
  'X' packets.

After this change:

- Both incoming and outgoing GDB packets are logged
  on debug_level >= 3, so that both directions of the
  GDB channel are visible.
- Non-printable characters are checked for in every packet
  so that hey do not interfere with the terminal.

Change-Id: I0613e57ae5059b3279b0abcb71276cf5719a8699
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6269
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/renesas_rz_g2: Introduce tcl config file for RZ/G2 devices

Initial support for Renesas RZ/G2 MPU family

Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6250
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* drivers/jlink: Remove trailing dots

This makes the messages consistent with most of the rest of
the OpenOCD output.

Change-Id: I915a01187e7fc317e02483ac0bbd39ec077d6321
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6274
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: Use 'bool' for 'reset_halt'

Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6262
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cmsis_dap: add support for swo commands

Replaced mixed snake_case_CamelCase with snake_case.
Define variables at first-use location.

CMSIS-DAP SWO specification:

    https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__swo__gr.html

Change-Id: Ieba79b16efd445143f964b614673d041aae74f92
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/5820
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Add target_data_bits().

This is used to compute memory block read alignment, and specifically
allows 64-bit targets to ensure that memory block reads are only
requested on 64-bit boundaries.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817
Reviewed-on: http://openocd.zylin.com/6249
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Avoid non-standard conditionals with omitted operands.

Fixes bug #257.

Change-Id: I05fc6468306d46399e769098e031e7e588798afc
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6271
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/startup.tcl: Do not use 'Yoda conditions'

Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6284
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix build.

Change-Id: I4f2667db91f84f07af354691aac5d4c9e3aea3fa
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Marc Schink <dev@zapb.de>
Co-authored-by: R. Diez <rdiezmail-openocd@yahoo.de>
Co-authored-by: Daniel Anselmi <danselmi@gmx.ch>
Co-authored-by: Evgeniy Didin <didin@synopsys.com>
Co-authored-by: Yasushi SHOJI <yashi@spacecubics.com>
Co-authored-by: Tomas Vanek <vanekt@fbl.cz>
Co-authored-by: Olivier DANET <odanet@caramail.com>
Co-authored-by: Thomas Gleixner <tglx@linutronix.de>
Co-authored-by: micbis <michele.bisogno.ct@renesas.com>
Co-authored-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Co-authored-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Co-authored-by: Jan Matyas <matyas@codasip.com>
Co-authored-by: Adrian Negreanu <adrian.negreanu@nxp.com>
2021-06-11 13:01:55 -07:00
Tim Newsome ab0a2a38a3
Call keep_alive() more often. (#616)
When it doesn't do anything (most of the time) it has negligible
performance impact. With slower remote bitbang, and multiple spike
instances being tested in a single chain, things are sufficiently slow
that if a computer is busy then this is required to pass
riscv-tests/debug.

Change-Id: I8816efedaa0cc3b25734ba8fdc979ee4502284a1
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-06-08 10:54:26 -07:00
Jan Matyas 0211e6bf4c
Print dcsr.cause always (#617)
Minor change/debug print: Made sure that dcsr.cause is printed
into the log always.
2021-06-07 12:40:58 -07:00
Tim Newsome 358ab3483d Add target_data_bits().
This is used to compute memory block read alignment, and specifically
allows 64-bit targets to ensure that memory block reads are only
requested on 64-bit boundaries.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817
Reviewed-on: http://openocd.zylin.com/6249
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04 17:45:58 +01:00
Xiang W 3249d41559
Refactor opcodes.h (#613)
Simplify the code and prevent some field of the instruction from overflowing

Change-Id: I0acade05ad351d0e1918be4b75702b1637aa02c9
Signed-off-by: Xiang W <wxjstz@126.com>
2021-05-28 13:27:22 -07:00
Antonio Borneo 036de3b482 riscv: replace macro DIM() with ARRAY_SIZE()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6258
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-22 10:11:41 +01:00
Antonio Borneo 8d207b5d2e riscv: drop unused variable
The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6257
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-22 10:11:36 +01:00
wxjstz b36d176721
remove needless function declaration from src/target/riscv/program.h (#608)
Signed-off-by: Xiang W <wxjstz@126.com>
2021-05-20 11:55:47 -07:00
Tim Newsome 19f7b5c43c
Add keepalive for vector register access. (#611)
(And whatever else does a lot of register writes.)

Change-Id: I86a1a784fb7b9430aa470dbb39a495b89f56d8c9
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-20 11:50:34 -07:00
Antonio Borneo 9bdd1daec3 riscv: replace macro DIM() with ARRAY_SIZE()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:57:11 +02:00
Antonio Borneo 6f5259db05 riscv: prefer ARRAY_SIZE() to DIM()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code not upstreamed.

Change-Id: Ie3e411280f76bc798f1d51c2574cfec148ee0d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:53:10 +02:00
Antonio Borneo 0944e12232 riscv: drop unused variable
The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:40:55 +02:00
Tim Newsome 8fcc19d70b Keep alive when accessing registers.
With the bitbang performance decrease and talking to slower targets
(daisy chain spike) we more often don't meet the expected keepalive time
for gdb. This addresses the cases I ran into.

Change-Id: Ie69c2c602c3be9c156e508fdfa6d0178f104e1d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-12 11:44:32 -07:00
Marc Schink 40dd1e5284 target/riscv: Change 'authdata_read' output
Use a constant output length and remove the line break to make the
authentication data easier to parse.

Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6199
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-08 09:49:52 +01:00
Tim Newsome 38eea2367c Add keep_alive() to system bus read loop.
Without it the repeat read test wasn't passing any longer. This is
because 7dd323b26d reduced the remote
bitbang performance. I've notified the mailing list about this.

Change-Id: Ie71592792202423aec89fa889b9e3d2a60a3c25f
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-03 14:56:34 -07:00
Tim Newsome 7420382a4d Merge branch 'master' into from_upstream
Conflicts:
	.github/workflows/snapshot.yml
	NEWS
	configure.ac
	contrib/loaders/checksum/riscv_crc.c
	jimtcl
	src/helper/time_support.h
	src/jtag/drivers/arm-jtag-ew.c
	src/rtos/FreeRTOS.c
	src/target/image.c
	src/target/riscv/riscv.c

Change-Id: I043624ba540d4672fc123dddb2066bcb9c6b5a05
2021-04-13 11:26:25 -07:00
Ernie Edgar 28724d996a
Update version check error message from 0.14 to 1.0. (#588) 2021-04-02 11:51:01 -07:00
Tim Newsome 41147e6fcd Implement CRC32 algorithm for RISC-V.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01
Reviewed-on: http://openocd.zylin.com/6076
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2021-03-19 21:58:17 +00:00
Tim Newsome d57ab0b632
From upstream (#580)
* configure: do not make Capstone dependency automagic

This adds regular ./configure options to control dependency on the
Capstone disassembly engine. See [0] for the rationale.

[0] https://wiki.gentoo.org/wiki/Project:Quality_Assurance/Automagic_dependencies

Change-Id: I3e16dc5255d650aa1949ccf896b26dc96e522a75
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5985
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* configure.ac: fix build with libusb0 and without libusb1

Driver 'openjtag' requires both libftdi and libusb1.
The current check is incorrect and the driver is built when
libftdi is present with libusb0 and without libusb1, which causes
the linker to fail resolving the required libusb1 symbols.

Remove the check for libusb0 on driver 'openjtag'.
Create a new adapters group LIBFTDI_USB1_ADAPTERS to hold the
driver 'openjtag'.

Change-Id: I1f5e554b519e51c829d116ede894639cb55a26aa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5989
Tested-by: jenkins

* doc: fix over/underfull hboxes in PDF

This adds some cosmetic changes to make the PDF User Manual look
proper.

Building it now requires Texinfo 5.0 which shouldn't be problematic
according to [0]. Commit 79fdeb37f4 is
effectively reverted.

[0] https://repology.org/project/texinfo/versions

Change-Id: I990bc23bdb53d24c302b26d74fd770ea738e4096
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5995
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* contrib: rpc_examples: haskell: fix ftbs with current libraries

And get rid of some warnings along the way.

Change-Id: I8fdbe1fa304276be6b0f25249b902b3576aa3793
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5987
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Makefile.am: fix override of target 'check-recursive'

To prevent executing the Jim Tcl tests, the makefile's target
'check-recursive' has been overridden in commit 56d163ce79
("jimtcl: update to 0.77, the current version, enable only
specific modules").
This causes a runtime warning during build:
	Makefile:6332: warning: overriding recipe for target 'check-recursive'
	Makefile:5098: warning: ignoring old recipe for target 'check-recursive'

Instead of override the makefile's target 'check-recursive',
prevent the recursion by re-assigning as empty the variable
SUBDIRS for this specific target only.

Change-Id: I03d1c467eba42316a59aeed4612d6bdbe6211282
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 56d163ce79 ("jimtcl: update to 0.77, the current version, enable only specific modules")
Reviewed-on: http://openocd.zylin.com/5986
Tested-by: jenkins

* contrib: udev file for Cypress SuperSpeed Explorer kit

lsusb output:

Bus 003 Device 011: ID 04b4:0007 Cypress Semiconductor Corp.
Couldn't open device, some information will be missing
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass            0 (Defined at Interface level)
  bDeviceSubClass         0
  bDeviceProtocol         0
  bMaxPacketSize0         8
  idVendor           0x04b4 Cypress Semiconductor Corp.
  idProduct          0x0007
  bcdDevice            0.00
  iManufacturer           1
  iProduct                2
  iSerial                 0
  bNumConfigurations      1
  Configuration Descriptor:
    bLength                 9
    bDescriptorType         2
    wTotalLength          114
    bNumInterfaces          4
    bConfigurationValue     1
    iConfiguration          0
    bmAttributes         0xa0
      (Bus Powered)
      Remote Wakeup
    MaxPower              100mA
    Interface Association:
      bLength                 8
      bDescriptorType        11
      bFirstInterface         0
      bInterfaceCount         2
      bFunctionClass          2 Communications
      bFunctionSubClass       2 Abstract (modem)
      bFunctionProtocol       1 AT-commands (v.25ter)
      iFunction               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass         2 Communications
      bInterfaceSubClass      2 Abstract (modem)
      bInterfaceProtocol      1 AT-commands (v.25ter)
      iInterface              0
      CDC Header:
        bcdCDC               1.10
      CDC ACM:
        bmCapabilities       0x02
          line coding and serial state
      CDC Union:
        bMasterInterface        0
        bSlaveInterface         1
      CDC Call Management:
        bmCapabilities       0x00
        bDataInterface          1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x83  EP 3 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval              10
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       0
      bNumEndpoints           2
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0
      iInterface              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x01  EP 1 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x82  EP 2 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        2
      bAlternateSetting       0
      bNumEndpoints           3
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass      4
      bInterfaceProtocol      0
      iInterface              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x04  EP 4 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x85  EP 5 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval              10
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        3
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass      5
      bInterfaceProtocol      0
      iInterface              0

Change-Id: I62f0300199da3551c8774a4a5a4cd106a3ab2904
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/3611
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: fix memory leak on multiple '-gdb-port' flag

In the odd case of multiple flags '-gdb-port' during 'target
create' or following 'configure', the new strdup()'ed value will
replace the old one without freeing it.

Free the old value (if it exists) before replacing it.

Change-Id: I1673346613ce7023880046e3a9ba473e75f18b8a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6005
Tested-by: jenkins

* udev: fix permission for Ambiq Micro EVK's

Commit 68e204f1e9 ("udev: Add rules for Ambiq Micro EVK's.") was
initially proposed as http://openocd.zylin.com/3429/ then replaced
by http://openocd.zylin.com/3980/
The initial proposal was for file '99-openocd.rules', in which
MODE="664" was the norm.
After merge of http://openocd.zylin.com/2804/ the new udev rules
in '60-openocd.rules' switched to MODE="660", but the evolution of
the above patch missed this change.

Switch udev rules of Ambiq Micro EVK's to MODE="660" and uniform
them to the rest of the file.

Change-Id: I4b4eea535184ee8569da3264bff4f1fafb5bce4d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 68e204f1e9 ("udev: Add rules for Ambiq Micro EVK's.")
Reviewed-on: http://openocd.zylin.com/6004
Tested-by: jenkins

* doc/style: fix doxygen error

Doxygen complains about non-closed nested comments:
	doc/manual/style.txt:423: warning: Reached end of file
	while still inside a (nested) comment. Nesting level 1
	(probable line reference: 149)

This is caused by the string '/**' that is interpreted as the
beginning of a comment.

Escape the string to not let doxygen consider it as a comment

While there, replace @code/@endcode with @verbatim/@endverbatim to
properly render the line.

Change-Id: If2a27c4cf659326e317cc4ac8c0b313e97e40432
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5996
Tested-by: jenkins

* flash/nor/max32xxx: fix path of include file

The relative path should have three times '..'.

Issue identified by doxygen:
	src/flash/nor/max32xxx.c:85: warning: include file
	../../contrib/loaders/flash/max32xxx/max32xxx.inc not
	found, perhaps you forgot to add its directory to
	INCLUDE_PATH?

Change-Id: Ie7b4948c6770b8acb9eff26e08eea32945ebb219
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5997
Tested-by: jenkins

* Doxyfile.in: fix build out-of-tree

When doxygen is built out-of-tree, it fails to find the generated
file startup_tcl.inc:
	src/openocd.c:59: warning: include file startup_tcl.inc
	not found, perhaps you forgot to add its directory to
	INCLUDE_PATH?

Add '@builddir@/src' to INCLUDE_PATH.

Change-Id: I51f2f6fe7224bba0f8b3db7219f9831de4e67139
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5998
Tested-by: jenkins

* doc/manual/primer/jtag.txt: remove duplicated section name

The section name 'primerjtag' is used twice, causing doxygen to
complain:
	warning: multiple use of section label 'primerjtag',
	(first occurrence: doc/manual/primer/jtag.txt, line 107)

Rename one of them.

Change-Id: Id307915dbc51a7f647fab4fb28ab431e65344d61
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5999
Tested-by: jenkins

* Doxyfile.in: exclude libjaylink from doxygen

When build using libjaylink as git submodule, doxygen includes the
libjaylink files and complains for multiple 'mainpage' comment
block, one in OpenOCD and the other in libjaylink:
	src/jtag/drivers/libjaylink/libjaylink/core.c:37: warning:
	found more than one \mainpage comment block! (first
	occurrence: doc/manual/main.txt, line 1), Skipping current
	block!

Exclude libjaylink submodule from doxygen.

Change-Id: I5e856817344c9f21f8c26f077a23c00b83cfbcb5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6000
Tested-by: jenkins

* openocd: fix incorrect doxygen comments

Use '@param' in front of function's parameters and '@a' when the
parameter is recalled in the description.

This fixes doxygen complains:
	warning: Found unknown command '@buff16'

While there, fix a minor typo s/occured/occurred/ in a comment and
the typo s/@apram/@param/ in a doxygen comment.

Change-Id: I5cd86a80adef552331310a21c55ec5d11354be21
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6001
Tested-by: jenkins

* openocd: fix doxygen parameters of functions

Add to doxygen comment the missing parameters.
Remove from doxygen comment any non-existing parameter.
Fix the parameter names in doxygen comment to match the one in the
function prototype.
Where the parameter name in the doxygen description seems better
than the one in the code, change the code.
Escape the character '<' to prevent doxygen to interpret it as an
xml tag.

Change-Id: I22da723339ac7d7a7a64ac4c1cc4336e2416c2cc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6002
Tested-by: jenkins

* doc/manual/primer/autotools.txt: fix doxygen warning

Commit ab90b87778 ("configure: remove AM_MAINTAINER_MODE,
effectively always enabling all the rules") removes the configure
flag '--enable-maintainer-mode' and its documentation, but have
left a reference to the removed subsection 'primermaintainermode'
and this triggers a warning in doxygen:
	doc/manual/primer/autotools.txt:21: warning: unable to
	resolve reference to 'primermaintainermode' for \ref
	command

Remove the obsoleted paragraph.

Change-Id: I56e69ef033d546d159745bed1b47c6105827e7ae
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ab90b87778 ("configure: remove AM_MAINTAINER_MODE, effectively always enabling all the rules")
Reviewed-on: http://openocd.zylin.com/6003
Tested-by: jenkins

* flash/stmqspi: fix build error with -Werror=maybe-uninitialized

using gcc 9.3 on ubuntu focal fossa with -Werror=maybe-uninitialized
we get this error:
  /src/flash/nor/stmqspi.c: In function ‘read_flash_id’:
  /src/flash/nor/stmqspi.c:1948:6: error: ‘retval’ may be used uninitialized

Change-Id: Ifd8ae60df847fc61e22ca100c008e3914c9af79b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6012
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/riscv: fix build error with -Werror=maybe-uninitialized

using gcc 9.3 on ubuntu focal fossa with -Werror=maybe-uninitialized
we get this error:
  /src/target/riscv/riscv.c: In function ‘riscv_address_translate’:
  /src/target/riscv/riscv.c:1536:13: error: ‘pte’ may be used uninitialized

Change-Id: I51e180b43f9b6996e4e4058db49c179b9f81bcdc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6013
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cortex_m: [FIX] ARMv8-M does not support VECTRESET

ref: Arm®v8-M Architecture Reference Manual (DDI0553B.m)
     D1.2.3: AIRCR, Application Interrupt and Reset Control Register
             Bit [0] is RES0

Change-Id: I6ef451b2c114487e2732852a60e86c292ffa6a50
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6014
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* driver/ftdi: skip trst in swd mode

When using the adapter olimex arm-jtag-swd (to convert to SWD a
JTAG-only FTDI adapter), the pin trst on JTAG side is re-used to
control the direction of pin SWDIO on SWD side.
There is a single reset API at adapter driver to assert/deassert
either srst and/or trst. A request to assert/deassert srst can
cause also trst to change value, hanging the SWD communication.

In SWD mode, ignore the value passed to trst.

Change-Id: I5fe1eed851177d405d77ae6079da9642dc1a08f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6006
Tested-by: jenkins

* configure.ac: drop macro 'AC_PROG_CC_C99' from autoconf 2.70

The macro AC_PROG_CC_C99 has been obsoleted by autoconf 2.70 and
triggers a set of warnings from both 'aclocal' and 'autoconf'.
The test of AC_PROG_CC_C99 is now included in AC_PROG_CC.

For autoconf 2.69 and earlier the macro is still required, so
cannot be simply dropped.

Use a conditional test to avoid the warning on autoconf 2.70 but
still use AC_PROG_CC_C99 on older autoconf.

Change-Id: I5e8437f5a826fb63be6d07bcb5bb824f94683020
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6009
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* configure: drop macro 'AC_HEADER_TIME'

The macro AC_HEADER_TIME has been obsoleted by autoconf 2.70.

Not all systems provide 'sys/time.h', plus some old system didn't
allowed to include both 'time.h' and 'sys/time.h' because 'time.h'
was included by 'sys/time.h' and was not properly protected to
allow multiple inclusion.
The macro AC_HEADER_TIME helps to detect such odd case.
Nowadays all the systems properly protect 'time.h', so its safe to
unconditionally include 'time.h', even if it is also included by
'sys/time.h'.

The case of systems without 'sys/time.h' is already covered by
configure.ac through the directive
	AC_CHECK_HEADERS([sys/time.h])

Remove the obsoleted autoconf macro and simplify the code by
including 'time.h' unconditionally and check HAVE_SYS_TIME_H to
include 'sys/time.h'.

Change-Id: Iddb3f3f1d90c22668b97f8e756e1b4f733367a7d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6010
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* README.macOS: explain how to install suitable Texinfo

Change-Id: Ic5906111f412eebd906a9be3fd0e133484def3eb
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/6026
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* jlink: fix device discovery when network is off

If user specifies a serial number for the jlink device, openocd
extends the search to network jlink devices too, without checking
if the host has a valid and functional network connection. If the
network is not functional, libjaylink returns error. This error
invalidates the discovery on USB, even if it was successful.

Factor-out parts of the jlink_init into separate jlink_open_device
function, use that function to firstly discover and match USB
devices and, if matching device was not found on the USB bus and
serial number was specified, repeat discovery and matching via TCP.

Fixes: https://sourceforge.net/p/openocd/tickets/294/

Change-Id: Iea0de1640d4e5b21ecc7e9c1dd6d36f214d647c2
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-on: http://openocd.zylin.com/6025
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* README: add missing items for 0.11

JTAG adapters
  Cadence DPI, Cypress Kitpro, FTDI FT232R, Linux GPIOD, Mellanox rshim,
  Nuvoton Nu-Link, Nu-Link2, NXP IMX GPIO, Remote Bitbang, TI XDS110,
  Xilinx XVC/PCIe

Debug targets
  AArch64, Cortex-M (ARMv8-M), ARCv2, MIPS64, RISC-V, ST-STM8

Flash Drivers
  ATmega128RFA1, Atmel SAM, eSi-RISC, EZR32HG, MAX32, MXC, nRF52, PSoC6,
  Renesas RPC HF and SH QSPI, SiFive Freedom E, ST BlueNRG,
  STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, SWM050, TI CC13xx, TI CC26xx,
  TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF

Change-Id: I341618ac5d7189e4f98268cecd66c99447b72af8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6027
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* The openocd-0.11.0-rc2 release candidate

Signed-off-by: Paul Fertser <fercerpav@gmail.com>

* Restore +dev suffix

Signed-off-by: Paul Fertser <fercerpav@gmail.com>

* steppenprobe: fix file permission

Commit 895d4a5995 ("tcl/interface/ftdi: Add Steppenprobe open
hardware interface") erroneously set the execution permission to
the configuration file.

Strip the execution permission.

Change-Id: I556451d5e6fee4aee385451e8c90216a25b6ef46
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: http://openocd.zylin.com/5653
Reviewed-on: http://openocd.zylin.com/6038
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Paul Fertser <fercerpav@gmail.com>

* github: fix github wokflow while pushing a tag

this fix permits to add correctly the generated artifact (windows binaries)
into the release section.

Change-Id: Ia982370d3a1e08c623ebcabb5ac97e9fb49d00e0
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6047
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* doc: Fix type in Hooking up the JTAG Adapter

We are talking about adapter connectivity in this chapter. It should
be "dongles" instead of "cables".

Change-Id: I7bd4307765517375caa2af86dfc929d0ef66c3e6
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6040
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

* doc/manual: Fix @subpage handling

The subpage "thelist" used to have a title "Pending and Open Tasks"
but the commit c41db358a0 changed it to "The List". With
@subpage, it now renders:

    "The List of The List enumerates opportunities for"

instead of

    "The List of Pending and Open Tasks enumerates opportunities for"

This commit fix it to

    "The List enumerates opportunities for"

Change-Id: Ifee0dcd9b3c9f7e651a8748a7afda99eedea3c5c
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6041
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* doc/manual: Fix function name typo

We have both the singular form, register_command(), and the plural form
register_commands().

Change-Id: I905ea83988b8ac70dd809b02d53b646aa4d66697
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6042
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

Co-authored-by: Paul Fertser <fercerpav@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Jiri Kastner <cz172638@gmail.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Co-authored-by: Bohdan Tymkiv <bohdan200@gmail.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Co-authored-by: Yasushi SHOJI <yashi@spacecubics.com>
2021-02-11 11:27:18 -08:00
Jan Matyas 9e174604b9
Fix in write_memory_bus_v1: Read sbcs properly (#578)
* Fix in write_memory_bus_v1: Read sbcs properly

Fixed an issue with system bus write: sberrors were not properly
detected because of an incomplete read of "sbcs". The read was initiated
but not completed (value not acquired by a second DMI scan).

Added debug prints in case sberror != 0.
Added few comments to explain the algorithm.

Change-Id: Id5eb07f2f1bf8e9afee2dec04b9ff5c5a57f606b
Signed-off-by: Jan Matyas <matyas@codasip.com>

* Updated per review discussion at #577.

Change-Id: I65c07edcd4e86eaa5327280a81f74db0b9c84f9c
Signed-off-by: Jan Matyas <jmatyas@codasip.com>

* Empty commit to re-trigger Travis build.

Change-Id: I95deeb28584a891203c8904be621e48003f069dc

Co-authored-by: Jan Matyas <jmatyas@codasip.com>
2021-02-04 10:04:01 -08:00
Tim Newsome 3651cbdfdc
Add memory access while running to `riscv info` (#576)
This way people can write TCL scripts that rely on these more abstract
properties instead of having to check for the existence of sbaccess,
which is not part of 0.11. (There is a similar feature but things are
named differently.)

Change-Id: I5c95a29ef43cb40c3a73b904f11fa7ca38d87b21
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-29 12:51:22 -08:00
Tim Newsome 8980c2038a
Select current hart before accessing vector regs. (#574)
I don't know how this worked before. Possibly caused by overzealous
removal of `-rtos riscv`.

Change-Id: I7259267b861ef45655f469ab39cc463d608fe149
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-29 10:58:34 -08:00
Tim Newsome 6628394c2c
Minor cleanups. (#573)
* Make a few globals const.

Looking through globals to see what needs to be removed, but const
globals are OK.

Change-Id: I4126a3f629daf91b109a3bd7120e4b4f62a9d8ee
Signed-off-by: Tim Newsome <tim@sifive.com>

* Fix comment typo.

Change-Id: I0c20837559411410b6870e0d0e52c0179a3a167e
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-29 10:58:11 -08:00
Tim Newsome a83ac81022
Add authdata_read/authdata_write support to 0.11. (#575)
AFAIK there is no hardware that implements this, but it should be a
close-to-done starting point in case it is ever required.

Change-Id: I49e3082e8629b1d70b12e8a847c2848e75b04508
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-28 09:56:51 -08:00
Jan Matyas 4d0efe0fbb
riscv-013: Fix comment for register_read() (#569)
Signed-off-by: Jan Matyas <matyas@codasip.com>
2021-01-20 13:01:16 -08:00
Tim Newsome d52e4668a6
Remove `-rtos riscv` (#567)
* Remove `-rtos riscv`.

`-rtos hwwthread` is target-independent and a cleaner way to achieve the
same thing.

Change-Id: I863a91f9ad66e37dc36f2fbcbffe403b91355556

* Little more cleanup.

Change-Id: I8fda2317368a94760bc734abc7f1de6ee5b82a7c

* Clean up some more.

Change-Id: I64a1e96aa3bd8c0561d4d19930f99e9bc40eab86

* Get rid of riscv_[sg]et_register_on_hart

Change-Id: I5ea9439bad0e74d7ed2099935e7fc7292c4a2b7f

* Remove hartid arg from set_register.

Change-Id: Ib560e3c63ff32191589c74d3ee06b12295107c6f

* Remove more references to hartid.

Change-Id: Ie9d932fb8b671c478271c1084dad43cad3b2bfbc

* Remove some unused code.

Change-Id: I233360c6c420d1fc98b923d067e65a9419d88d7b
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-18 12:22:43 -08:00
Tarek BOCHKATI 404993b29f target/riscv: fix build error with -Werror=maybe-uninitialized
using gcc 9.3 on ubuntu focal fossa with -Werror=maybe-uninitialized
we get this error:
  /src/target/riscv/riscv.c: In function ‘riscv_address_translate’:
  /src/target/riscv/riscv.c:1536:13: error: ‘pte’ may be used uninitialized

Change-Id: I51e180b43f9b6996e4e4058db49c179b9f81bcdc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6013
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-01-18 15:31:56 +00:00
Tim Newsome fcdecd88ae Don't write to zero.
It doesn't have any effect on real hardware, and by caching the value we
pretended it did.

Fixes #564

Change-Id: I9f4e2cc8abddee61435bbd8d992cbff971a0c28d
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-14 13:53:43 -08:00
Antonio Borneo 7e64e5a895 openocd: fix doxygen parameters of functions
Add to doxygen comment the missing parameters.
Remove from doxygen comment any non-existing parameter.
Fix the parameter names in doxygen comment to match the one in the
function prototype.
Where the parameter name in the doxygen description seems better
than the one in the code, change the code.
Escape the character '<' to prevent doxygen to interpret it as an
xml tag.

Change-Id: I22da723339ac7d7a7a64ac4c1cc4336e2416c2cc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6002
Tested-by: jenkins
2021-01-13 11:33:53 +00:00
Craig Blackmore 1158acec66 riscv: Fix comment in read_memory_progbuf
The comment should refer to reading rather than writing.

Change-Id: I72937bb48053233ab5e48d343c4bd1e394f77bda
Signed-off-by: Craig Blackmore <craig.blackmore@embecosm.com>
2021-01-13 11:32:38 +00:00
Tim Newsome 11b8110443 Merge branch 'master' into from_upstream
Conflicts:
	.github/workflows/snapshot.yml
	.gitmodules
	src/flash/nor/drivers.c
	src/helper/jep106.inc
	src/rtos/hwthread.c
	src/target/riscv/riscv.c
	src/target/target.c

Change-Id: I62f65e10d15dcda4c405d4042cce1d96f8e1680a
2020-12-31 13:40:49 -08:00
Tim Newsome b8620764c0
Add `riscv info` command. (#558)
Add `riscv info` command. Final output is "TCL format" and looks like this:
```
hart.xlen              64
hart.trigger_count      4
dm.abits                6
dm.progbufsize          2
dm.sbversion            0
dm.sbasize              0
dm.sbaccess128          0
dm.sbaccess64           0
dm.sbaccess32           0
dm.sbaccess16           0
dm.sbaccess8            0
```

* Add `riscv info` command.

This command displays some basic information that OpenOCD has detected
about the target. The output is displayed in YAML so it can easily be
parsed. Example of current output:
```
Hart:
  XLEN: 32
  trigger count: 4
Debug Module:
  abits: 6
  progbufsize: 2
  sbversion: 0
  sbasize: 0
  sbaccess128: 0
  sbaccess64: 0
  sbaccess32: 0
  sbaccess16: 0
  sbaccess8: 0
```

Change-Id: If920c083ff6ec9f482c50f913cd8ceaa62461217
Signed-off-by: Tim Newsome <tim@sifive.com>

* Disable workflow inherited from upstream.

Change-Id: Ifc5ed1b4f5ec2278b8bcf3279c9fd462e469fefa
Signed-off-by: Tim Newsome <tim@sifive.com>

* Switch from YAML to TCL "set array" input format.

Change-Id: I3833210e5bf6d7cffc9934c04ec5201ae7732ad8
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove indent in `riscv info` output.

That was getting a little too cute, and probably more confusing than
helpful.

Change-Id: Ie51416f53ab4b69294962f0565767d370db82867
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-12-14 12:40:08 -08:00
Tim Newsome f72e5bb0d8
Fix error handling in read_memory_progbuf_one(). (#560)
* Fix error handling in read_memory_progbuf_one().

Be sure to restore mstatus/s0 even if there is a failure during the
operation.

Fixes #559.

Change-Id: Ib86ca2c7455bad4a668f34703566060a782116db
Signed-off-by: Tim Newsome <tim@sifive.com>

* Style fix suggested in review.

Change-Id: I444112a9dffea483b7d0e5f96ef7bbdaf58d249f
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-12-14 12:39:00 -08:00
Jan Matyas 5d0543cc1c
Clear sbcs.sbbusyerror without affecting other sbcs bits (#547)
This is a fix for an issue reported by Joe Stoy at:
https://sourceforge.net/p/openocd/mailman/message/37128537/

When clearing sbcs.sbbusyerror, preserve other bits in the sbcs
register that are needed for subsequent system bus transactions.
2020-12-14 12:32:31 -08:00
Antonio Borneo 1d3d87695c target/register: use an array of uint8_t for register's value
The use of 'void *' makes the pointer arithmetic incompatible with
standard C, even if this is allowed by GCC extensions.
The use of 'void *' can also hide incorrect pointer assignments.

Switch to 'uint8_t *' and add GCC warning flag to track any use of
pointer arithmetic extension.

Change-Id: Ic4d15a232834cd6b374330f70e2473a359b1607f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5937
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-12-05 23:18:37 +00:00
Adrian Negreanu 850e85fa6f semihosting: print the semihosting operation id
Change-Id: If5c3568bd1c99a48ac492137f48da0d9764efe14
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/5923
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Reviewed-by: Tim Newsome <tim@sifive.com>
2020-11-07 20:50:16 +00:00
Tim Newsome 3cf46af271
Add before/after timestamps to memory sampling. (#550)
This lets a user see exactly what period of time was sampled, without
having to guess how much time the target was ignored in between bursts.

Change-Id: I5c0639528636bf1a88f249be3ba59bec28c001e2
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-10-21 12:21:05 -07:00
Tim Newsome ccb21ab5ac
Merge pull request #549 from riscv/from_upstream_histogram
Merge upstream changes into this branches
2020-10-16 14:16:45 -07:00
Samuel Obuch bc1d689e6d
Allow riscv_semihosting without 16 bit access to memory with instructions (#544)
* Allow riscv_semihosting without 16 bit access to memory with instrustions

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* rename *_by_any_size to riscv_*_by_any_size
2020-10-16 09:19:53 -07:00
Tim Newsome e8379cda32 Make it build again.
Change-Id: I851cfb8811d8e5d25760c9fddaeb99d7af1fdf6f
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-10-15 15:06:28 -07:00
Tim Newsome 7a933ea7ad Merge branch 'master' into from_upstream_histogram
Used histogram diff strategy, which was much better than the default.

Conflicts:
	doc/openocd.texi
	src/flash/nor/fespi.c
	src/jtag/drivers/libjaylink
	src/rtos/rtos.c
	src/target/riscv/batch.c
	src/target/riscv/encoding.h
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/target.c
	tcl/target/gd32vf103.cfg

Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
2020-10-15 12:32:45 -07:00
Antonio Borneo 4fc61a2f9d riscv: fix compile error
The commit b68674a1da ("Upstream tons of RISC-V changes.") was
proposed well before commit 3ac010bb9f ("Fix debug prints when
loading to flash"), but the merge got in different order.
After latest merge, the master branch fails to compile.

Fix the compile error.

Change-Id: Ia3bd21d970d589343a3b9b2d58c89e0c49f30015
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5856
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
2020-10-14 11:05:22 +01:00
Tim Newsome b68674a1da Upstream tons of RISC-V changes.
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.

Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.

I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.

Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2020-10-14 05:43:05 +01:00
Tobias Kaiser fb477376da
Do not throw error if RISC-V tselect unimplemented (#542)
* Do not throw error if RISC-V tselect unimplemented

A RISC-V hart without Trigger Module may not implement any of the
associated CSRs such as tselect according to the specification.
riscv_enumerate_triggers previously threw an error in this case, but
only on the first invocation due to r->triggers_enumerated being set
regardless of this. Due to the propagation of this error condition to
disable_triggers and riscv_openocd_step, such a hart would remain
halted after the first 'step' (or 'continue') of a debug session.

This problem can be reproduced with the Ibex RISC-V CPU when
the DbgTriggerEn parameter is set to zero.

This commit changes the behavior of riscv_enumerate_triggers to
return ERROR_OK when tselect was not readable. This fixes the
described malfunction.

Change-Id: Ie813cb119b03702fe708801b5f3581f9bf337243
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>

* Add debug message if RISC-V tselect not readable

Change-Id: Ic3ad5bff9de5c50142cad983f351ce0099cec5c8
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>

* RISC-V triggers: continue if tselect is unreadable

In riscv_enumerate_triggers, even if for one hart tselect cannot be
accessed, other harts might provide trigger support. For this reason,
"continue;" is the appropriate action on a read failure of tselect,
which indicates that triggers are not implemented, instead of
"return ERROR_OK;".

Change-Id: Ied56f3e237b76195a15bfde159532eda9d347d21
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
2020-10-12 09:16:12 -07:00
Tim Newsome 6c1bd05088
Add memory sample feature (#541)
* Add memory sampling feature.

Currently only gets 10 samples per second, but the overall scaffolding
looks like it works.

Change-Id: I25a2bbcba322f2101c3de598c225f83c902680fa

* Basic memory sample speed-ups.

977 samples/second.

Change-Id: I6ea874f25051aca1cbe3aa2918567a4ee316c4be

* Add base64 dumping of sample buffer.

We can't just dump raw data, because the API we use to get data to the
"user" uses NULL-terminated strings.

Change-Id: I3f33faaa485a74735c13cdaad685e336c1e2095f

* WIP on optimizing PC sampling.

1k samples per second on my laptop, which is roughly double what it was.

Change-Id: I6a77df8aa53118e44928f96d22210df84be45eda

* WIP

Change-Id: I4300692355cb0cf997ec59ab5ca71543b295abb0

* Use small batch to sample memory.

5k samples/second. No error checking.

Change-Id: I8a7f08e49cb153699021e27f8006beb0e6db70ee

* Collect memory samples near continuously.

Rewrite OpenOCD's core loop to get rid of the fixed 100ms delay.
Now collecting 15k samples/second.

Change-Id: Iba5e73e96e8d226a0b5777ecac19453c152dc634

* Fix build.

Change-Id: If2fe7a0c77e0d6545c93fa0d4a013c50a9b9d896

* Fix the mess I left after resolving conflicts.

Change-Id: I96abd47a7834bf8f5e005ba63020f0a0cc429548

* Support 64-bit address in memory sampling.

* Support sampling 64-bit values.

* Better error reporting. WIP on 64-bit support.

* Speed up single 32-bit memory sample.

21k samples/second.

* WIP on review feedback.

Change-Id: I00e453fd685d173b0206d925090beb06c1f057ca

* Make memory sample buffers/config per-target.

Change-Id: I5c2f5997795c7a434e71b36ca4c712623daf993c

* Document, and add bucket clear option.

Change-Id: I922b883adfa787fb4f5a894db872d04fda126cbd
Signed-off-by: Tim Newsome <tim@sifive.com>

* Fix whitespace.

Change-Id: Iabfeb0068d7138d9b252ac127d1b1f949cf19632
Signed-off-by: Tim Newsome <tim@sifive.com>

* Document sample buffer full behavior.

Change-Id: Ib3c30d34b1f9f30cf403afda8fdccb850bc8b4df
Signed-off-by: Tim Newsome <tim@sifive.com>

* Actually clear the sample buffer in dump_sample_buf.

Change-Id: Ifda22643f1e58f69a6382abc90474659d7330ac5
Signed-off-by: Tim Newsome <tim@sifive.com>

* Use compatible string formatting.

Change-Id: Ia5e5333e036c1dbe457bc977fcee41983b9a9b77
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-10-07 14:31:36 -07:00
Tom Hebb e2cfd4e063
Improve support for GD32VF103 MCU (#538)
* riscv: work around buggy hart states during reset in some DMs

As described in the comment this change adds, the GD32VF103 DM reports
that the hart is in more than one state while it is resetting. Because
of this, the current code acknowledges resets before they actually
complete. This sometimes prevents havereset from getting cleared as
intended, leading to a spurious "Hart 0 unexpectedly reset!" message the
next time riscv_is_halted() gets called.

To work around this, check for the absence of the unavailable state
rather than the presence of the running or halted states. This behavior
is also arguably more true to the spec than what exists now: Section 3.2
states that "The system may take an arbitrarily long time to come out of
reset, as reported by allunavail, anyunavail."

Change-Id: I34e90a16233125608bce8e4c2414dbead637600e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>

* riscv: support custom reset-assert scripts

The reset-assert event is used, if present, to override the default
reset logic for ARM and MIPS cores. Do the same for RISC-V so that
devices with buggy ndmreset functionality (like GD32VF103) or
nonstandard reset sequences can specify the appropriate logic in Tcl.

Change-Id: I5e12077d67509853edb8ef3ad3f037f293a5fbb6
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>

* tcl/target: support GD32VF103 RISC-V MCU

The GD32VF103 is a low-cost 32-bit RISC-V microcontroller with
peripherals that are more-or-less compatible with the STM32F103 ARM
microcontroller. It is available on several low-cost dev boards, such as
the Sipeed Longan Nano, which is what I am testing on.

Add initial support for this chip, including a workaround for a buggy
ndmreset line (i.e. one that doesn't actually trigger a reset) in its
integrated debug module. Use the existing GD32VF103 flash driver that
was ported from the vendor's code in commit 48e40f3513 ("Add support
for GD32VF103 flash").

Change-Id: Iadac47ceb5437b8e18f3d35901388f10fef9f876
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>

* tcl/target/gd32vf103: add main flash alias

The GD32VF103 creates an alias to either main flash or the bootloader at
0x0, depending on how it was booted. As such, we want to indicate to
debuggers that the memory at 0x0 is flash and so cannot support software
breakpoints. To do this, add an alias to the main flash in the config.
This isn't strictly accurate in the case where we're running the
bootloader, but it still suits our purpose of fixing breakpoint
behavior.

Change-Id: I9eb8462d354f096eee231c0e5e2bffa538a5903e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2020-10-01 11:06:11 -07:00
Samuel Obuch 6db3ed2c86
Improve riscv expose_[csrs|custom] commands (#536)
* Improve riscv expose_[csrs|custom] commands

* Add option to specify custom name for registers.
* Allow to call commands multiple times without loss of previous data.
* Make sure the commands can only be used in the config phase (before "init").
* Validity checks and warnings.
* Change commands to be per target.
* Fix memory leaks.
* Also fix unrelated memory leaks to keep valgrind happy.

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* fixes after review

* improve error message
2020-10-01 11:05:41 -07:00
Tom Hebb 2c909f8faa
riscv: remove unused riscv_error_t type (#539)
This seems to be completely unused in these two files. It was probably
accidentally copied from riscv-011.c, where it is used.

Change-Id: I3f7ad8b2d26b005d3ea4438e2b3ec46a6c801792
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2020-09-28 09:46:47 -07:00
Tom Hebb db2e8ad10a
riscv: remove outdated documentation in riscv.c (#540)
These comments appear to have been copied from riscv-011.c, for which
they are accurate. However, it makes no sense to also have them in
riscv.c, because 1) none of the things described are actually in
riscv.c; and 2) riscv-013.c has an entirely different code structure,
meaning everything in the comment is an implementation detail of
riscv-011.c. Remove the copy in riscv.c and just leave the one in
riscv-011.c.

Change-Id: I2873af1522482681325525040b3caad2ddddce9d
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2020-09-28 09:45:18 -07:00
Tim Newsome 13b2ed5ec5
Minor cleanups. (#537)
Requested in http://openocd.zylin.com/#/c/5821/9

Change-Id: I775d9dd3cc8642361d4d129a05053ee3d27b99bb
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-09-28 09:41:08 -07:00
Jan Matyas 11c4f89b32
Allocate RISC-V arch_info during target creation (#531)
* Allocate RISC-V arch_info during target creation

* Ensured that target->arch_info is allocated as soon as the
  target is created. Needed so that per-target config commands
  (e.g. "riscv set_mem_access") can be executed also in the
  OpenOCD's config phase (before calling "init").

* Added several assert()'s for safety.

Signed-off-by: Jan Matyas <matyas@codasip.com>

* Removed a TODO comment
2020-09-17 13:20:12 -07:00
Tim Newsome 1712dc2c54
{read_from,write_to}_buf -> buf_[sg]et_u{32,64} (#529)
Requested in http://openocd.zylin.com/#/c/5821/7/src/target/riscv/riscv-013.c

Change-Id: I764d77192e902466eed8a6ccf1042b42016afb7e
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-09-15 11:40:37 -07:00
Tim Newsome d4bcd8846a
Make a couple variables static. (#528) 2020-09-15 11:39:32 -07:00
Samuel Obuch 22d771d20c
Allow to put breakpoints in memories without 16 bit access (#525)
* Allow to put breakpoints in memories without 16 bit access

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* tmp

* tmp

* tmp

* read/write by any size for breakpoints

* fix style for checkpatch
2020-09-14 08:00:59 -07:00
Samuel Obuch 2ea18ef7f6
Selection of memory access methods, aampostincrement detection (#508)
* Add flexible selection of memory access methods, detection of aampostincrement.

New configuration command introduced: "riscv set_mem_access".
It allows to specify which RISC-V memory access methods (progbuf,
sysbus and/or abstract access) should be tried and in which order
of priority.

Command "riscv set_prefer_sba" is left and works in backward
compatible way, but is marked as deprecated.

First time abstract memory access is executed, it is tried with
set aampostincrement bit. If the abstract command fails or the
address is not incremented correctly, aampostincrement will not
be used for any subsequent accesses.

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* remove unnecessary variable

* fix doc
2020-09-10 13:57:51 -07:00
Tim Newsome 2bde4a918a
Add empty usage strings back in. (#526)
Comment on #521 pointed out that they're required.
2020-09-10 13:53:27 -07:00
Antonio Borneo 3934483429 target: avoid checking for non NULL pointer to free it
The function free() can be called with a NULL pointer as argument,
no need to check the argument before. If the pointer is NULL, no
operation is performed by free().

Remove the occurrences of pattern:
	if (ptr)
		free(ptr);

In target/openrisc/jsp_server.c, an error is logged if the ptr was
already NULL. This cannot happen since the pointer was already
referenced few lines before and openocd would have been already
SIGSEGV in that case, so remove the log.

Change-Id: I290a32e6d4deab167676af4ddc83523c830ae49e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5809
Tested-by: jenkins
2020-09-05 20:47:11 +01:00
Tim Newsome 5e84c5dd8a
Fix usage for our RISC-V commands. (#521)
Change-Id: Ia4e020637aae2384af223b0210ef2aef6a14b31a
2020-09-03 11:59:48 -07:00
Tim Newsome 9357818bb9
Check malloc/calloc return values. (#517)
Should not affect anything, but requested in
http://openocd.zylin.com/#/c/5821/5/src/target/riscv/batch.c@28

Change-Id: Ib7185bd93eeb918e72872416ab6364f8776cff88
2020-09-03 11:57:25 -07:00
Jiuyang Liu 57b57989b4
user4 0x23 should be MSB. (#519)
Signed-off-by: Jiuyang Liu <jiuyang.liu@sifive.com>
2020-09-01 10:32:31 -07:00
Tim Newsome f5a44b0d14
Make checkpatch require Signed-off-by (#516)
* Make checkpatch require Signed-off-by

This will make it easier to send changes contributed here to mainline
OpenOCD.

(Intentionally not including the required line here to make sure I can't
just merge this.)

Change-Id: I089084d38f3e08859d62cf7eface405f37af4799

* Whitespace fix.

This PR isn't building on travis. Maybe because I only changed
.travis.yml. Here's a source change to force a build (hopefully).

Change-Id: I8a828fe1d56a1960bc4bfb91d3d2f3a0790ad571

* Can't check for signoff on sources alone.

Change-Id: I741a299b64bf14857a4e1807b254a7d270b2e466
Signed-off-by: Tim Newsome <tim@sifive.com>

* Actual whitespace fixes.

Why didn't this fail to build before?

Change-Id: I339c03c4ef96546dbef5f16e635921a4fdaf9b35
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-08-31 13:20:46 -07:00
Tim Newsome 91dc0c0c8e
Add SPDX tags for RISC-V files. (#513)
Requested in http://openocd.zylin.com/#/c/5821/3

Change-Id: I95551a3311d8e128300bacdf463da7ab4edf29a0
2020-08-24 15:43:03 -07:00
Tim Newsome ad5f40af8d
Update encoding.h from riscv-opcodes (#514)
Rename dscratch to dscratch0, since that is what it's called in the
spec.

Change-Id: Id6271ae272e979cef69e8ef0577b23452fb84f51
2020-08-24 15:42:45 -07:00
Tim Newsome ca6b1eff1d
Update debug_defines.h from riscv-debug-spec (#515)
A ton of constants got a new prefix, so I made a lot of changes to
match, but no functional changes.

I did define DTM_DMI_MAX_ADDRESS_LENGTH	in batch.c. That definition
never should have been in debug_defines.h, which I missed during code
review.

Change-Id: If5d86660f84bb0a3f2865fb36ef05d6630486d8b
2020-08-24 15:42:29 -07:00
Tim Newsome 920497c62f
Mostly whitespace changes. (#511)
Requested in http://openocd.zylin.com/#/c/5821/3

Change-Id: I75e6d551091396fc6e81b3642ae44bafe358eed7
2020-08-21 12:56:04 -07:00
Tim Newsome c116dc50b2
Update to version 1.0 of the vector spec. (#505)
Accessing registers on targets that implement 0.9 or earlier will no
longer work. If you need that we can talk about making it a config
option.

Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
2020-08-18 11:07:34 -07:00
Tim Newsome 53ec10b61d
Create `riscv repeat_read` command (#510)
* WIP, apply stash with conflicts.

Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31

* Fix conflict resolution problems.

Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238

* Add repeat_read command.

Only implemented for sba v1 right now, and poorly tested at that.

Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b

* Hide bogus address in repeat_read

Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa

* WIP make repeat read work with progbuf.

Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79

* WIP

Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d

* Fix error handling when increment is non-zero.

Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a

* Correctly(?) handle failures when increment is 0.

I'm not 100% convinced that this ensures every read value shows up in
the output, but it ought to work.

Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa

* Don't crash when asked to read no data.

Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05

* Remove unnecessary comment.

Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f

* Document `riscv repeat_read`.

Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
2020-08-18 11:01:41 -07:00
Samuel Obuch c1c88dccee
Account for impebreak in size requirements for progbuf (#509)
* Account for impebreak in size requirements for progbuf

* add helper function
2020-08-17 13:07:11 -07:00
Jan Matyas e2d3184eba
Fix of DMI batch scans over 64-bits (#432)
This fixes buffer overrun/data corruption during DMI scan batches
on targets with large value of dtmcs.abits > 30 (unusual, but within
the spec).
2020-08-07 08:39:43 -07:00
Antonio Borneo 480ba8ca88 target: fix minor typos and duplicated words
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5766
Tested-by: jenkins
2020-07-26 23:09:45 +01:00
Antonio Borneo 996ff5bcfc coding style: add arguments to function prototypes
Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types FUNCTION_ARGUMENTS -f {} \;

This patch also fixes an incorrect function prototype in zy1000.c.
ZY1000 minidriver implementation overrides the function
arm11_run_instr_data_to_core_noack_inner(), but the prototype is
not the same as in src/target/arm11_dbgtap.c and to avoid compile
error it was changed also the prototype of the called function
arm11_run_instr_data_to_core_noack_inner_default().

Change-Id: I476cda8cdb0e1e280795b3b43ca95c40d09e4a3d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5630
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-07-08 22:08:19 +01:00
Tim Newsome 8b929c6497
Triggers with type=0 aren't real. (#496)
Fixes #491.

Change-Id: Id01adcc68d8c7d95f7e86d49d5d2b0c97c9fb1b0
2020-07-07 11:55:57 -07:00
Tim Newsome bbfc666eba
Merge pull request #494 from riscv/from_upstream
Get changes from upstream
2020-07-02 15:22:47 -07:00
Tim Newsome b50b8da476
Warn if we are asked to read/write 0 bytes. (#492)
Technically that might be OK, but in practice it probably indicates
something went wrong somewhere. Before this change OpenOCD would crash
if it happened.

Change-Id: I2500ba67ec282915dcf2b2488f2aac9fbfdb23a3
2020-07-01 08:28:27 -07:00
Tim Newsome 43463b30ed Merge branch 'riscv' into from_upstream
Change-Id: Ia9c5d7c7f0a4913c1af17e042266736943334c7f
2020-06-30 11:04:48 -07:00
Tim Newsome f0151889f0
Don't halt the algorith-running hart because another is halted. (#490)
This logic is a little tortured, but it still passes the semihosting
tests that were the cause for the recent rewrite.

Change-Id: Ic6760bb068621ab2a49feb0cf3998fc6957b5cfc
2020-06-25 17:33:56 -07:00
Tim Newsome 0b1b9e2034
Accept dmstatus.version==3 (0.14) (#489)
Fixes #485.

Change-Id: I60b3d68827ca726558bc28035c0b74c5cf0d9754
2020-06-25 15:34:48 -07:00
Tim Newsome e07613de33 Merge branch 'master' into from_upstream
Conflicts:
      .gitmodules
      .travis.yml
      jimtcl
      src/jtag/core.c
      src/jtag/drivers/ftdi.c
      src/jtag/drivers/libjaylink
      src/jtag/drivers/mpsse.c
      src/jtag/drivers/stlink_usb.c
      src/rtos/hwthread.c
      src/target/riscv/riscv-013.c
      src/target/riscv/riscv.c
      tcl/board/sifive-hifive1-revb.cfg

Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c
2020-06-23 13:05:43 -07:00
Tim Newsome 03f943ae23
Step/resume off manual hardware triggers (#486)
* Accommodate users setting custom triggers.

RISC-V hardware supports many more triggers than gdb can communicate to
OpenOCD. Accommodate users that set triggers by writing tdata* directly,
by disable/step/reenable when a user has done that.

Note that users must set dmode in tdata1 for this behavior to work
properly. Triggers with dmode=0 are assumed to be set and handled by the
software that is being debugged.

Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066

* Enumerate triggers when resuming from a trigger

Otherwise when we connect to a target that's already halted due to a
trigger, we won't correctly step past it.

Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c

* Also disable/reenable triggers around single step.

Gdb is smart enough to disable/step/resume if it set the triggers, but
if a user set them manually it also needs to happen.

Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f

* Fix whitespace.

Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
2020-06-18 14:47:42 -07:00
Khem Raj 3c6592cf62
riscv: Avoid shadowing read_csr/write_csr macros (#483)
The name conflict is picked by compiler and it fails to compile for rv64
Fixes
src/target/riscv/riscv-011.c:1014:44: error: too many arguments provided to function-like macro invocation
static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
                                           ^
Signed-off-by: Khem Raj <raj.khem@gmail.com>
2020-06-16 11:37:44 -07:00
Tommy Murphy 95a8cd9b5d
Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)
* Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issues/474

* Updated code based on feedback from @timsifive
2020-05-26 10:33:30 -07:00
Tim Newsome 4f9e2d7171
Fix semihosting for multicore targets (#478)
* WIP making semihosting work with -rtos hwthread.

Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e

* More WIP.

Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb

* Fix halting due to a trigger.

Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad

* Fix multicore semihosting without halt groups.

Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4

* WIP

Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40

* Fix single core semihosting.

This was the last bug!

Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28

* Fix whitespace.

Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
2020-05-19 10:34:36 -07:00
Tim Newsome 1524487a13
Speed up SBA block reads roughly 2x. (#477)
* Speed up SBA block reads roughly 2x.

Change-Id: I4e4f5530d4abae7470fd00308361e727904367d2

* Fix whitespace.

Change-Id: I28a1269c489d051560a2455973f9a8574f35f487
2020-05-18 14:43:41 -07:00
Antonio Borneo 59cc1f6629 coding style: open function's brace at beginning of new line
Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types OPEN_BRACE -f {} \;

Change-Id: I6d1356ed11e2699525f384efb7556bc2efdc299f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5628
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
2020-05-09 14:41:31 +01:00
Antonio Borneo 185834ef8a coding style: add missing space when split strings
Long strings are split across few lines; usually split occurs at
the white space between two words.
Check that the space between the two words is still present.
While there, adjust the amount of space between words.

Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types MISSING_SPACE -f {} \;

Change-Id: I28b9a65564195ba967051add53d1c848c7b8fb30
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5620
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:44 +01:00
Antonio Borneo 4f459660a9 coding style: avoid unnecessary line continuations
Line continuation, adding a backslash as last char of the line, is
requested in multi-line macro definition, but is not necessary in
the rest of C code.

Remove it where present.

Identified by checkpatch script from Linux kernel v5.1 using the
command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types LINE_CONTINUATIONS -f {} \;

Change-Id: Id0c69e93456731717a7b290b16580e9f8ae741bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5619
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:29 +01:00
Antonio Borneo 9b29cb58ac coding style: remove useless break after a goto or return
In a switch/case statement, a break placed after a goto or return
is never executed.
The script checkpatch available in Linux kernel v5.1 issues a
warning for such unused break statements.
In the process of reviewing the new checkpatch for its inclusion
in OpenOCD, let's get rid of these warnings.

The script checkpatch is unable to fixup automatically this case.
Thanks to having "break" command using a single code line, this
patch has been generated using the script below:

	find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \
	 --types UNNECESSARY_BREAK -f {} \; \
	| sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \
	| awk 'function P() {print "sed -i '\''"b"'\'' "a};
	       {
	         if ($1!=a) {
	           if (a) {P()};
	           a=$1;
	           b=$2"{d}";
	         } else {
	           b=b";"$2"{d}"
	         }
	       };
	       END {P()}'

Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5617
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:05 +01:00
Tim Newsome 0c3e50a06a
Don't cache PC, but do cache DPC. (#473)
This fixes a bug where we read PC and marked it cached without actually
updating the cached value. The DPC value was correctly marked as valid
and updated.

Change-Id: Id6d3e94a96b981688b06f7f4a998019f2c02f6f5
2020-05-06 08:43:59 -07:00
Tim Newsome 55dd7e83ca
Add awareness of halt group cause. (#472)
Change-Id: I7f7b967ccaa3d1ff05a7e7d0c2a7ba4fa7d68ac0
2020-05-06 08:42:38 -07:00
Tim Newsome e6e281197f
Cache accesses through riscv_[sg]et_register. (#467)
* Cache accesses through riscv_[sg]et_register.

This helps a lot with the address translation code, which checks satp
over and over again. Now satp is only read once per halt. It should also
help in a few other cases (but I don't have a good test setup to really
measure the impact).

Change-Id: I90392cc60d2145a70cf6c003d6a956dc9f3c0cc4

* Fix whitespace.

Change-Id: I05c5342d8a461cd8c618a3f60296925e9e84643f

* Don't read registers that we know don't exist.

Change-Id: Ie5c6226b3d4ecb6cf8f0d8954a52fda88e6e5bdd
2020-04-21 14:58:59 -07:00
Florian Fainelli 5c6e32612d Remove BUILD_TARGET64
BUILD_TARGET64 creates a larger test matrix and mostly gates the
building of the aarch64/armv8 target, make that unconditional, which
would help fixing any issues with 64-bit address types anyway.

Rebased by Antonio Borneo after commit 1fbe8450a9 ("mips: Add
MIPS64 support")

Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5240
Tested-by: jenkins
2020-04-21 12:55:41 +01:00
Tim Newsome 2e9aad8914
Don't propagate failure to read satp in riscv_mmu() (#466)
If we return failure, then the caller will think something's wrong. But
it could very well be that the hardware doesn't have SATP, in which case
we should just report that the MMU is disabled.

This fixes a bug where flashing wasn't using the target algorithm
because allocating a work area failed.

Change-Id: I16e8e660036d3f8584c0b17e842c4ec8961a8410
2020-04-13 12:53:26 -07:00
Tim Newsome 464407cfd2
Expose FPRs as single and double for F and D. (#465)
If a hart support both F and D, then expose the FPRs as a union of float
and double. Fixes #336.

Change-Id: I3d4503bbf9281d6380c51259388cd01d399b94d6
2020-04-10 13:32:12 -07:00
Tim Newsome cbb15587dc
Document default values for some config options. (#461)
Change-Id: I4373b9487ea11664d3a6ea7ea10e99ea6d337232
2020-03-27 11:21:02 -07:00
Tim Newsome 3967f48843
Fix some clang static checker complaints. (#464)
The OpenOCD project looks at this, so once in a while I go through and
make sure our code is OK.

Change-Id: I50032c847f30e93604d83d6366cfad85918d6e66
2020-03-27 11:20:48 -07:00
Tim Newsome 5b2426a4b2
Deal with vlenb being unreadable. (#458)
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.

Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
2020-03-26 09:08:56 -07:00
Tim Newsome f6f30fb148
Update to 1.11 privileged spec. (#455)
Change-Id: I25029f7e83819464e71528fb4225b4761787793f
2020-03-18 12:24:22 -07:00
Tarek BOCHKATI a99bf2ea94 semihosting: reorganize semihosting commands
the same semihosting handlers chain is declared twice:
 1. in src/target/armv4_5.c
 2. in src/target/riscv/riscv.c

to make it simpler we moved the declaration into
'src/target/semihosting_common.c' under semihosting_common_handlers[].
then we used this into both of armv4_5.c and riscv.c

Change-Id: If813b3fd5eb2476658f1308f741c4e805141f617
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5473
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
2020-03-10 20:20:22 +00:00
Tomas Vanek a2e822834d helper/binarybuffer: fix clang static analyzer warnings
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)

Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-03-07 15:30:05 +00:00
Tim Newsome 1ae21b3874
Fix address translation when high bits are set. (#453)
Fixes #452.
Also check that the high bits match the MSB of the virtual address.

Change-Id: Ib1d3d04db9ad9327ef71ea3736d5cf5d3b65b9c4
2020-03-05 11:33:51 -08:00
Antonio Borneo e7306d361b coding style: fix space around pointer's asterisk
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.

This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command
	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types POINTER_LOCATION --fix-inplace -f {} \;
then manually reviewed.

OpenOCD coding style does not mention the space around pointer's
asterisk, so no check is enforced. This patch only makes the style
uniform across the files.

The patch only changes amount and position of whitespace, thus
the following commands show empty diff
	git diff -w
	git log -w -p
	git log -w --stat

Change-Id: Iefb4998e69bebdfe0d1ae65cadfc8d2c4f166d13
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5197
Tested-by: jenkins
2020-02-24 10:30:36 +00:00
Tim Newsome 1449af5bdb
Give control over dcsr.ebreak[msu] bits. (#451)
This allows a user to debug code that uses software breakpoints itself.

Change-Id: If40cb626354e11703017cdf8c5919a31e83ebc3f
2020-02-20 13:58:15 -08:00
Tim Newsome 95462a8a35
Add support for vector register access (#448)
* WIP

Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd

* Reading v* registers appears to work.

Can't really test it though, because gdb doesn't print them right.

Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5

* Total hack to communicate registers to gdb.

Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765

* Implement writing vector registers.

Fixed reading vector registers.

Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214

* Show gdb the actual size of the vector registers.

This length may be different per hart.

Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493

* Remove outdated todo comment.

Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128

* Removed TODO comment.

Filed #449 to track this.

Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47

* Nicely handle some errors reading/writing V regs.

Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
2020-02-14 14:54:05 -08:00
Tim Newsome 2f456abd55
Complain about debug version before authentication. (#441)
Change-Id: I769af8323545c2c18e4253a1543e9202f0bdfabc
2020-01-27 16:07:08 -08:00
Tim Newsome 69e6891434
Handle DMI busy in sba write. (#437)
* Handle DMI busy in sba write.

If we encounter DMI busy on the NOP after a read, we'll never get the
value out because DMI busy is sticky. The read must be retried, but we
don't know whether it was ever issued. Since the read has side effects
(incrementing of the address) this retry must be handled at a higher
layer. So now dmi_op_timeout can be told to retry or not, and if retry
is disabled it'll return an error when busy.

Also actually properly do the retry in dmi_op_timeout(). Previously the
code would not reissue the command and end up returning a garbage value.

Change-Id: I3b52ebd51ebbbedd6e425676ac861b57fbe711b1

* Fix whitespace.

Change-Id: Icb76d964e681b22346368d224d1930c9342343f3

* Handle a few more DMI busy cases.

Change-Id: I8503a44e4bf935c0ebfff0d598fe4c322fda702a

* Explain when to use dmi_op_timeout(retry).

Change-Id: I1a5c6d76ac41a84472a8f79faecb2f48105191ff

* dmi_reset does not affect the current transaction.

That means the retry scheme we had been using works fine. This does
contain some minor tweaks, and now we pass my tests which hammer the DMI
busy case harder.

Change-Id: I13eee384dbba82bc5a5b1d387c75c547afe557b5

* Remove unnecessary changes to make the PR readable

Change-Id: I87079876e6965563cf590e3936b3595aeab8715d

* Move idle to end of line...

... because we go through run-test/idle after the scan.

Change-Id: I21a8cff22471f0b895d8cd8d25373dced9bf1ca9

* Remove unused code.

Change-Id: I07a7cdd2d64ca40a4fe181111a34cf55ff1928d1
2020-01-13 15:10:43 -08:00
Jan Matyas fcea4f79ba Don't issue extra FENCE+FENCE.i for the current hart. (#439)
The original OpenOCD code issued FENCE & FENCE.i twice for the current
hart (which is harmless, but takes time).

Avoiding this extra FENCE is a slight performance improvement. Per my rough
measurements, this improves performance of certain debugger actions
(single-stepping) by approx. 20% in single-hart systems.
2020-01-10 12:29:10 -08:00
Tim Newsome 8b8db033ee
Upcast mask value to work with 64-bit physical (#436)
Change-Id: I00f0d2a3c79a431e1aa49c7478fa6c17e2fa5256
2020-01-06 16:57:15 -08:00
Hsiangkai 2c3f099b73 Fix bugs. Do not touch SATP if there is no MMU. (#435)
* riscv: Fix bugs. Do not touch SATP if there is no MMU.

In some platform, there is no SATP register at all.
OpenOCD will report unexpected errors if SATP is unreadable.
So, use 'riscv_enable_virtual' to guard SATP access.

* riscv: fix format typo.
2019-12-31 11:27:22 -08:00
Hsiangkai 9886f77374 riscv: translate virtual address to physical address. (#425)
* riscv: translate virtual address to physical address.

* riscv: fix formatting errors.

* riscv: fix build errors.

* riscv: Remove redundant command for virtual address access.

* Revert "riscv: Remove redundant command for virtual address access."

This reverts commit 990d09eac3.

* riscv: Change command disable_virt2phys  to set_enable_virt2phys

1. Avoid double negative logic to make users easy to use.
2. Add document about new comomand 'riscv set_enable_virt2phys on|off'
2019-12-10 12:18:03 -08:00
bluew aec5cca15b Increase maximum number of harts (#429)
OpenOCD can't deal with systems that have more than 32 harts.
2019-12-05 17:22:12 -08:00
Tim Newsome 780d8e4d3e
Remove unused data structure. (#431)
Saves 1.4MiB of RAM too, with just 1 hart configured.

Change-Id: I68d8c003a67c280b62ff6c9285ac6f54865f99f2
2019-12-04 16:23:22 -08:00
Jan Matyas e03dd199e0 Fixed write_memory_progbuf() on RV64. (#426)
Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
2019-11-27 15:24:25 -08:00
Tim Newsome de00906ebd
Fix memory access on some targets. (#428)
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.

This fixes https://github.com/riscv/riscv-tests/issues/217.

Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
2019-11-22 11:37:46 -08:00
Jan Matyas 739d16d503 Fix: Take into account progbuf writability. (#424)
When allocating scratch memory within RISC-V target
(scratch_reserve()), take into account whether progbuf
is writable or not, as determined by examine_progbuf().
2019-11-20 12:00:00 -08:00
Greg Savin b7bd3f8d47 BSCAN batch fix (#422)
* fix for batch scans not honoring presence of BSCAN tunnel

* fix formatting to placate checkpatch

* replace DIM with ARRAY_SIZE

* Refactor code that adds a bscan tunneled scan.

* Move bscan tunnel context to the batch structure, and in array
form, one per scan

* adjust code that was inconsistent with project code formatting standards
2019-11-12 09:00:35 -08:00
Tim Newsome f93ede5401
Add support for 64-bit memory reads/writes (#419)
* 64-bit progbuf memory reads work.

Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399

* 64-bit writes work.

Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23

* Let targets indicate number of supported data bits.

This is used by the default memory read/write functions when creating an
aligned block.

I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.

Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b

* Make mingw32 happy.

Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
2019-11-04 11:04:30 -08:00
Tim Newsome 20804cb4d2
pmpcfg[13] only exist on RV32. (#416)
Change-Id: I38f10d34b163eb7d0bf44b5717bbb027b0e43e76
2019-10-23 11:37:51 -07:00
Tim Newsome 3b4fcf471f The compliance test is poorly supported.
In reaction to #412.

Change-Id: I183bd8b4995c04e44cbc4f1c475eae391030fae6
2019-10-03 16:36:24 -07:00
Tim Newsome 9aac179cf2 Merge branch 'master' into from_upstream
Change-Id: I036350ee06aa396344fb8a80c7dba148ec24c9c8
2019-09-27 12:07:00 -07:00
darius-bluespec 20fc862b15 Perform SBA writes with batch transactions for improved performance. (#405)
* Add riscv_batch_available_scans().

This function will query the number of available scans in a batch.

* Perform SBA writes with batch transactions for improved performance.

Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
2019-09-24 17:49:25 -07:00
Tim Newsome 274be9587f
Fix flashing HiFive Unleashed (#402)
* Align algorithm stack to XLEN.

This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.

Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d

* Compile 32-bit RISC-V algorithms for RV32E.

Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa

* Remove debug code.

Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b

* Dump start of gdb packets escaping non-printable.

Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915

* Propagate flash programming errors.

Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7

* Improve debug messaging.

Change-Id: I47ac3518f3b241986c677824864102936100adf6

* Add debug output to flash image.

This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.

Change-Id: Id44c6498c288872cc2cec79044116ac38198c572

* Make timeout depend on how much data is written.

Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e

* Fix issi erase commands.

This is required to flash HiFive Unleashed.

Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10

* Fix running algorithm on multicore `-rtos riscv`.

The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.

Change-Id: I140431898285cf471b372139cef2378ab4879377

* Make fespi flash algorithm debugging optional.

Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.

Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-09 12:01:17 -07:00
Tim Newsome 5173ddf75e
Use only one hart to run algorithm. (#396)
* Clear cmderr by writing all ones.

This should have been part of #389.

Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0

* Don't update reg cache in register_write_direct().

This function explicitly bypasses any caches.

Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9

* Use only one hart to run algorithm.

Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.

Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
2019-08-26 11:24:29 -07:00
dave-estes-syzexion cd7eea6d76 Adds support for RISCV Access Memory Abstract Commands (#394)
* Adds support for RISCV Access Memory Abstract Commands

The Access Memory Abstract Command is one of the three optional
methods for reading and writing memory on a complient RISCV
debug module. The previous two options were already implemented
in OpenOCD.

Implementation Notes:
- aamvirtual is hard-coded to false until the design for accessing
  virtual addresses is finalized.
- aamsizes corresponding to 8b, 16b, 32b, and 64b are supported.
  128b support is postponed until it is required, as it will mean
  changes to the read/write_abstract_arg() interface to pass 128b
  values.
- aampostincrement is not used and hard-coded to false.

* Changes from review.

* Additional lint fixes and a typo from last commit.

* Fixing a clang error.

* Fixes a last-minute change that broke writes with width > 8b.

* Removing memcpy after adding read_from_buf().
2019-08-19 14:03:20 -07:00
Tim Newsome 7eaf60f1b5
Properly detect errors in SBA reads. (#392)
Also don't set/clear sbreadondata when only reading one word.

Change-Id: Ia81834014895f1f4b552312ad0b60b3d3967a2c7
2019-07-26 11:08:35 -07:00
Nils Wistoff 239a515a9c Access memory through the scope of current privilege level (#386)
* add opcode for csrrsi and csrrci

* enable MMU while reading/writing memory using progbuf

* fix style issues

* keep old behavior for progbufsize<4, perform r/w/csr only when necessary

* do not pass progbufsize, only write mstatus if changed

* add config option to enable virtualization feature

* throw error if virt enabled but unavaliable, outsource modify_privilege

* support virtualization for read_memory_progbuf_one
2019-07-18 13:15:28 -07:00
Tim Newsome 09016bcb6e
Optimize reading a single byte/short/word. (#390)
gdb has developed a nasty habit of very often reading 30-some
half-words. This change speeds that up significantly.

Change-Id: Iab1b7575bec5c57051c6e630ae292dddf8fe6350
2019-07-15 10:34:40 -07:00
Tim Newsome 9b34f8ca3c
Write all ones to clear cmderr. (#389)
Change-Id: Ia76e749ed9f5a5f3509f253eeb69d1208bcfc929
2019-07-15 10:33:52 -07:00
Tim Newsome 6983eda0e9
Make resume order configurable. (#388)
* Make resume order configurable.

This is a customer requirement. Using this option is discouraged.

Change-Id: I520ec19cc23d7837cb8576f69dadf2b922fa2628

* Fix style.

Change-Id: If8e515984c92ce8df52aa69e87abde023897409f

* Make mingw32-gcc happy.

Change-Id: I39852aedec293294b2b2638ab2cc45494fe77beb
2019-07-15 10:32:28 -07:00
Tim Newsome c5dee66a71
Redo fespi flash algorithm (#384)
* WIP, rewrite of flash algorithm.

Just put all the flashing logic into the algorithm, instead of using an
intermediate format. This should reduce total data written while
flashing by about 9%, and also makes the code much simpler.

Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79

* New algorithm works.

Speeds up Arty flashing another 9%.

wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s)
verified 2192012 bytes in 6.693336s (319.816 KiB/s)
8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k

Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4

* Fix whitespace.

Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b

* Don't reserve so much stack space.

Also properly check XLEN in riscv_wrapper.S.

Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
2019-07-09 10:05:07 -07:00
Tim Newsome 8f2d2c27e8
RV32E support (#387)
* In theory support RV32E.

Change-Id: Icfe2a40976ae3161f2324e5bb586915aa4c4c7ee

* In theory support RV32E.

At least very basic tests pass.

Change-Id: Ia42e28a3fa020b3e52c92109392c46d009330355

* Fix cut and paste bug.

Change-Id: Ibfea68b39d706f59a8c3aa8153bb4db9803958c6

* Add hacks to make RV32E work with gdb.

gdb currently requires all 32 GPRs to be present, even on RV32E targets.
Once gdb is fixed these hacks can be removed.

Change-Id: Idcde648de2ca1a3f5b31315aab35fac86580af2c
2019-07-08 12:26:01 -07:00
Tim Newsome 91faf1a573
Reduce abstract command execution by one scan. (#383)
Speeds up Arty flashing another 7%.

```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 96.997032s (22.434 KiB/s)
verified 2192012 bytes in 6.642059s (322.285 KiB/s)
11.86user 12.75system 1:44.13elapsed 23%CPU (0avgtext+0avgdata 18684maxresident)k
```

Change-Id: If609ce3de1726332f420d131e9fa6e04a5d974a1
2019-06-21 09:59:28 -07:00
jhjung81 86cc07a757 fix memory leak (#382) 2019-06-20 10:02:06 -07:00
Tim Newsome bb03f79bde
Improve block read and checksum speed (#381)
* Cache program buffer writes.

Speeds up flash program by 3%, flash verify by 2%.

Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a

* Remove nop from batch reads.

program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).

Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935

* Use "algorithm" to compute CRC on RISC-V targets.

Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.

riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.

Small target.[ch] change to be able to run algorithms at 64-bit
addresses.

Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```

Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190

* Clean up formatting.

Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 10:56:37 -07:00
Tim Newsome c05ad1a92a
Set mstatus.FS to access FPU CSRs. (#380)
This improves behavior when executing function calls from mainline gdb.

Change-Id: Ia37507a16cd76fc03d26457e84fd68402969c534
2019-06-14 15:55:56 -07:00
Paul George fd9c54b1fe Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode

Given the variable supported message length , a prefix  decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len =  max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected.

* style patch

* non-conflict with original

* style patch

* style patch

* requested changes

* style-patch
2019-06-10 13:33:50 -07:00
Tim Newsome 998fed1fe7
Don't write sbcs while sbbusy is set. (#375)
* Fix small SBA bug.

We were not compliant with the spec, but I'm not sure if this was
causing problems for anybody.

Change-Id: Ia31ee400fd75ad907349c4dd995b1e03bd2116c7

* Don't write sbcs while sbbusy is set.

Probably not hurting anything, but the spec says we shouldn't.
Also propagate more errors, and fully decode sbcs in debug output.

Change-Id: I1a36646772fe794c8780702565103a309bbcc5e9
2019-05-21 14:40:47 -07:00
Philipp Wagner 44f595b2b8 RISC-V: Make compliance tests more verbose (#366)
Currently the RISC-V compliance test suite doesn't output the test is
currently runs before it succeeds. It also uses the same message for
many tests. This makes it very hard to find out which test fails.

This commit makes things slightly easier by printing the test that's
being executed before it actually runs, and by adding the source code
line where the test is located, making it easier to look up the test in
the source code.

New output looks like this:

Info : Executing test 149 (riscv-013.c:3800): Regular calls must return ERROR_OK
Info :   PASSED
2019-05-20 13:36:41 -07:00
Philipp Wagner 45b5178b1a RISC-V compliance test: target must be examined (#367)
The test assumes that the target has been examined. If that fails (for
whatever reason) the test will segfault:

Program received signal SIGSEGV, Segmentation fault.
register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
109             struct reg *reg = cache->reg_list;
(gdb) bt
0  register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
1  0x0000000000520735 in riscv_invalidate_register_cache (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2160
2  0x000000000052224f in riscv_halt_all_harts (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2022
3  0x0000000000574e82 in riscv013_test_compliance (target=0x779b50) at ../src/target/riscv/riscv-013.c:3600
2019-05-20 13:35:58 -07:00
Tim Newsome da12994d9d
More helpful debug output. (#374)
I often want to see what OpenOCD is telling gdb, and it's annoying to
have to recompile.

Change-Id: Icce07606f253d67e2523cf2732dbe5042c6e483e
2019-05-16 14:39:12 -07:00
Antonio Borneo 6cb5ba6f11 helper/command: change prototype of command_print/command_print_sameline
To prepare for handling TCL return values consistently, all calls
to command_print/command_print_sameline should switch to CMD as
first parameter.

Change prototype of command_print() and command_print_sameline()
to pass CMD instead of CMD_CTX.
Since the first parameter is currently not used, the change can be
done though scripts without manual coding.
This patch is created using the command:
	sed -i PATTERN $(find src/ doc/ -type f)
with all the following patters:
	's/\(command_print(cmd\)->ctx,/\1,/'
	's/\(command_print(CMD\)_CTX,/\1,/'
	's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/'
	's/\(command_print_sameline(cmd\)->ctx,/\1,/'
	's/\(command_print_sameline(CMD\)_CTX,/\1,/'
	's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/'

This change is inspired by http://openocd.zylin.com/1815 from Paul
Fertser but is now done through scripting.

Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5081
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14 19:37:11 +01:00
Tim Newsome 5cb2f200f8
Simultaneous halt (#372)
* WIP

Change-Id: I4f50dced77e9ded4a58ab152824a841a73bc0dc1

* riscv_halt() only halt harts that are running.

Progress towards simultaneous halt.

Change-Id: I749b6d9ba5e77aa7aca4342c7af841312b78be0e

* -rtos riscv passes.

But dual gdb is failing again.

Change-Id: I1747ba42ce3f3062f6e8c28a75ac40e17f80e980

* Dual gdb works again.

-rtos riscv still works.

Change-Id: Idddddda79e5918b26e181384def1a305ecceced2

* -rtos hwthread almost completely works.

Change-Id: I845feb0bd93484e28ca8620f4760c234d4ce5310

* Maybe better?

Change-Id: I669c67e83acf1b749bfb534d3b3c0915c129d686

* All three methods work.

Change-Id: If77074fa43f6420d1ec9b594fe366415f5a41f2c

* Fix hitting hardware triggers with `-rtos riscv`.

Change-Id: I8d4600e1c66fa0e3b9d986b96a5973d09f40735c

* Fix halting dual core E31.

Change-Id: Ic2d885e027312b68e2f3c6854957fbfee09f814b

* Not addressing this TODO right now.

Change-Id: Ic7c0d32424068ae1de04d37d15a411c1957207c4

* Remove duplicate line.

Change-Id: I14fe8d422f23c97afdaa20a02c0e3ab568219467
2019-05-09 11:32:04 -07:00
Greg Savin 5190dd4cef
Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#370)
Including adjustments in response to review comments.
2019-04-23 16:25:22 -07:00
Marc Schink d5936dc688 target/riscv: Free registers to avoid memory leak
Tested with SiFive HiFive1 development board.

Change-Id: I96a9a528057fcf9fc54d3da46a672d2cd54c3d5f
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4885
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-10 16:37:21 +01:00
Tim Newsome d78ff5ab4e Propagate some errors in execute_abstract_command().
Change-Id: Ia3ec457dd5d65378a6c922802713e36d6828bcea
2019-04-09 10:55:25 -07:00
Antonio Borneo 69ba2a677b target/riscv: use coherent syntax in struct initialization
While initializing struct command_registration, the field's name "name"
is not specified, thus relying on the fact that it is the first field
declared in the struct and it's initialization value can be listed as
the first one.

Be coherent in the struct initialization and always use the field's
name.

Change-Id: Iefaeb15cc051db9f1e0f0140fe2f231b45f5bb12
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5013
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2019-04-07 08:14:50 +01:00
Tim Newsome 79f9672615 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/at91sam4.c
	src/flash/nor/at91sam4l.c
	src/flash/nor/at91samd.c
	src/flash/nor/ath79.c
	src/flash/nor/atsame5.c
	src/flash/nor/cfi.c
	src/flash/nor/core.c
	src/flash/nor/fespi.c
	src/flash/nor/kinetis.c
	src/flash/nor/kinetis_ke.c
	src/flash/nor/lpc2000.c
	src/flash/nor/niietcm4.c
	src/flash/nor/nrf5.c
	src/flash/nor/numicro.c
	src/flash/nor/pic32mx.c
	src/flash/nor/stm32h7x.c
	src/flash/nor/stm32lx.c
	src/flash/nor/stmsmi.c
	src/flash/nor/tcl.c
	src/flash/nor/tms470.c
	src/flash/nor/virtual.c
	src/flash/nor/xmc4xxx.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/server/gdb_server.c
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
2019-04-03 12:38:27 -07:00
Tim Newsome c089e6ae9a
Support simultaneous resume using hasel (#364)
* Remove unnecessary 0.11 code.

Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().

Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.

Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc

* WIP little refactor working towards hasel support.

Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf

* More refactoring.

Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b

* More refactoring.

Change-Id: Icea1308499492da51354f89e1529353e8385f3a1

* Starting to work towards actual hasel changes.

Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e

* Implement simultaneous resume using hasel.

Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f

* Add support back for targets that don't have hasel.

Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a

* Make hasel work with >32 harts.

Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
2019-04-03 12:13:09 -07:00
Tim Newsome bc72695f67 Lots of RISC-V improvements.
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`

Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27 08:53:09 +00:00
Tim Newsome 57e30102ea gdb_server, target: Add target_address_bits()
Targets can use this to expose how many address bits there are.
gdb_server uses this to send gdb the appropriate upper limit in the
memory-map. (Before this change the upper limit would only be correct
for 32-bit targets.)

Change-Id: Idb0933255ed53951fcfb05e040674bcdf19441e1
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4947
Tested-by: jenkins
Reviewed-by: Peter Mamonov <pmamonov@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-03-08 14:05:19 +00:00
Tim Newsome 9fac2de633
Set up halt groups for SMP groups. (#353)
If the hardware supports it, when one hart in an SMP group halts all the
other harts in that same SMP group will automatically, quickly, halt as
well.

Change-Id: Ida81f1309c180674e8c9d8060e3d2a4bbb910a6f
2019-03-05 13:05:53 -08:00
Marc Schink a851b91c4c target/riscv-011: Fix memory leak in handle_halt_routine()
Tested with SiFive HiFive1 development board.

Change-Id: Ie0d9fa0899804d17ccdd84b03ba4028e97b632b8
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4884
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-14 09:28:33 +00:00
Tim Newsome e96f4b1b06 Fix old cut and paste bug.
Change-Id: Id06fb98ed3dd1b3987e4eafa0ec271c1cd77fef6
2019-02-11 14:04:21 -08:00
Tim Newsome 1c6d52cd88 Merge branch 'master' into from_upstream
Conflicts:
	README
	contrib/loaders/flash/fespi/Makefile
	src/flash/nor/fespi.c
	src/flash/nor/spi.c

Change-Id: I78a4e73685cc95daace95e9d16066a6fb51034fb
2019-02-08 14:39:47 -08:00
Tim Newsome 80ef54dba2
Rtos riscv (#350)
* Implement riscv_get_thread_reg().

This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).

CustomRegisterTest went from 1329s to 106s.

Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32

* Also implement riscv_set_reg().

Now all the `-rtos riscv` tests pass again, at regular speed.

Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1

* Better error messages.

Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5

* Add target_get_gdb_reg_list_noread().

Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.

Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7

* Revert a change I made that has no effect.

I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.

Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
2019-02-07 13:24:44 -08:00
Tomas Vanek 7a3eec2b4d target algo: do not write reg_param if direction is PARAM_IN
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.

While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.

Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-02-07 07:51:50 +00:00
Tim Newsome e186f62962 More cleanup.
Change-Id: I804bdcec23b69d77dfc376e23c6d1f29f99e7335
2019-01-25 15:31:42 -08:00
Tim Newsome 96df1db7b1 Remove debug statements.
Change-Id: If37bc883fea0b83740bfd6a7fcb2091db0ac61f0
2019-01-25 14:48:22 -08:00
Tim Newsome 49dd7ded87 Merge branch 'riscv' into hwthread 2019-01-25 14:17:32 -08:00
Tim Newsome 82cf37d36c Invalidate register cache on reset.
All tests pass with `-rtos hwthread` against spike32!

Change-Id: I9051259d2702c76b7c35aeffeac020a773e0597a
2019-01-25 13:11:06 -08:00
Tim Newsome afedcb337a WIP on hardware breakpoints.
This is messy, but contains at least some bugfixes.

39/43 tests pass now.

Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-24 15:27:53 -08:00
Tim Newsome 906635c4bd Move version check until after dmactive=1.
This should allow OpenOCD to work with targets where version is not
readable when dmactive=0, which is allowed by the spec.
2019-01-22 12:48:47 -08:00
Tim Newsome c296c62521 Halt all SMP harts on halt request.
38/45 tests pass.

Change-Id: Ia4fd523139c197020d9277be4bf5f92079520068
2019-01-18 13:18:15 -08:00
Tim Newsome c1ef5f61c3 Fix reading of non-general registers for hwthread
Previously the code made the assumption (which is valid for conventional
RTOSs) that special registers (e.g. CSRs) are the same across threads.

26/45 tests pass.

Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
2019-01-17 15:01:47 -08:00
Tim Newsome 02ece46105 Clean up register caching a little.
Change-Id: Id039aedac44d9c206ac4bd30eb3ef754e190c3fe
2019-01-10 12:32:03 -08:00
Darius Rad 00b591a09a Add 'riscv set_ir' command to set IR value for JTAG registers.
This allows using different TAP addresses, for example, if using
BSCANE2 primitives on a Xilinx FPGA.
2019-01-09 17:20:39 -05:00
Tim Newsome e6b6aa615b Add comment for reset_delays_wait.
Also refactor so there's just one of them in riscv, instead of one for
0.11 and one for 0.13.

Change-Id: I0dbbf112b4c57f76bed971a22dadf844fa27cd4e
2019-01-08 14:01:25 -08:00
Tim Newsome fd49f5e967 Make riscv_get_gdb_reg_list read the registers.
This may not be the correct behavior, but it gets me further through the
tests.

Change-Id: I6e9b77e927700de706b6ece723f4d530fa566761
2019-01-07 12:17:41 -08:00
Tim Newsome 6faa9ded26 Clean up debug printf.
I only need to see 64 bits of PC if the high bits are non-zero.

Change-Id: I29397791da1e3f1705e573b2eaafc3eac202e178
2019-01-07 12:16:51 -08:00
Tim Newsome a9d436e77f WIP make riscv work with -rtos hwthread.
Change-Id: I37bb16291fa87a83f21e5fd8bad53492a4d69425
2019-01-03 15:06:35 -08:00
Tim Newsome ccc093ab82 Fix typo.
Change-Id: Ibdd26c5c524b10a3518fe708e9b7fc917b0cb1b6
2019-01-02 12:42:31 -08:00
Tim Newsome d6a6699f15 Fix block read corner cases.
Change-Id: I841f264ca881078075beaa58023dd0e0a81f3ff3
2018-12-13 12:05:55 -08:00
Tim Newsome 41e5272adc Add `riscv reset_delays` for testing.
This allows me to test corner cases in block read/write errors.

Change-Id: I3ccfe707851dbc578277ea0d5e278eab81a3c7ef
2018-12-04 12:38:51 -08:00
Tim Newsome d650ef6089 Deal with DMI busy in block reads/writes.
Rename dtmcontrol_idle to dtmcs_idle, because the register is now called
dtmcs.
Simplify read_memory_progbuf_inner(), getting rid of several unnecessary
variables.

Change-Id: Ibac655a45c63cf2210ab282568b54f8097526c10
2018-12-03 16:04:58 -08:00
Tim Newsome 42be17aed6
Add idle count to debug output. (#337)
Few other minor cleanups/debug improvements.

Change-Id: I370a86ddc17a2d888afa178448125661e12caf72
2018-11-29 12:52:06 -08:00
Tim Newsome f042dcb0a3
examine() should leave halted harts halted (#327)
Previously all harts would be resumed at the end of examine().
Fixes #326.

Change-Id: Id82b361e98f151911f8679538ee4b3c754efd6a5
2018-11-12 13:01:55 -08:00
Tim Newsome d18c2f23d3
Doxygen style, too. (#325)
* Doxygen style, too.

Change-Id: I85e60e8577c4177ac7094ae41ee84357b292a89c

* More Doxygen.

Change-Id: Ic7477dce5459146f299e080cac1a3f133af7abdb
2018-11-07 13:53:52 -08:00
Tim Newsome 874cadca31
Conform to OpenOCD style. (#323)
Change-Id: I11b5b66e474d3e1d979b4db537363d025f8e2c9a
2018-11-05 12:27:56 -08:00
Tim Newsome 005cfca219
Install patchutils for the build. (#321)
* Install patchutils for the build.

This contains filterdiff, which we need to check that our changes
conform to OpenOCD style.

Change-Id: Id522f4e62fee3efad4e0e00933abfeada9635624

* Fix paths for filterdiff line.

Change-Id: Ic50e13c7fe64e65b2d2af0260fb19c07a9f10e20

* Conform to OpenOCD style.

Change-Id: I51660d30404c0a625b58c9bed2d948695575e72e
2018-11-05 11:50:09 -08:00
Tim Newsome ca1a1f8db7
Complete single step before returning. (#319)
This fixes the following error, that has been reported occasionally:
Error: 34072 2712 riscv-011.c:1175 reg_cache_get(): Register cache entry for 0 is invalid!
openocd: ../src/target/riscv/riscv-011.c:1176: reg_cache_get: Assertion `r->valid' failed.

The problem was that we'd tell the target to step, and then gdb (which
assumed the target halted already) asked to read a register before the
target had actually halted. With this fix the target is actually halted,
and everything works.

Change-Id: Icfcef456f3cec4bb352fb90186f5bbabb00a5ff8
2018-11-05 11:48:52 -08:00
Pavel S. Smirnov 60368dd62e FIX(src/target/riscv/riscv.c): riscv_add_breakpoint: RVC: invalid 32bit transactions size for 16bit aligned instruction (#322) 2018-11-05 11:34:44 -08:00
Tim Newsome 936c514bbf
Fix 0.11 memory leak. (#318)
Change-Id: I78dbdfc7d599b0edcfcae94070cdd7a552a1bc0c
2018-11-02 12:45:34 -07:00
Carsten Gosvig dc4fe85880 Old fixes from June (#311)
* Changed logging level

* Added logging statement

* Removed halt event when attaching to target

* Extended some packet handling

* Extended handling of rtos_hart_id and clearing of register cache

* Extended execute_fence to handle all harts

* Removing logging statement again

* Updated according to review comments

* Forgot to re-add the return statement

* Was removing too much for the if statement to work

* This needs to >= 3 now to handle both a fence and a fence.i
2018-10-30 11:29:00 -07:00
Tim Newsome e54511ffa4
Revert "Don't report exact watchpoint to gdb. (#300)" (#304)
This reverts commit 933cb875a8.

https://github.com/riscv/riscv-openocd/issues/295 was fixed in gdb.
2018-10-24 13:02:44 -07:00
Carsten Gosvig 983a07be64
Merge pull request #308 from riscv/eclipse_memory_read
Fixing Eclipse block memory read
2018-10-19 23:07:22 +02:00
cgsfv 9703c00b25 Moved comment and added initial buffer clearing 2018-10-19 17:47:58 +02:00
Tim Newsome 60c37e1679
dmi_scan() allocate bytes depending on abits value (#307)
* dmi_scan() allocate bytes depending on abits value

Fixes #303.

Change-Id: Iac45959cf342180c60cd0b5462f864ad81beddd2

* Incorporate review feedback.

Change-Id: I1cc7d20fed6f2d891bec0e858fca53ece450720c
2018-10-18 13:26:03 -07:00
Tim Newsome b986d29bc9
Fix segfault in riscv_deinit_target(). (#306)
This would happen when OpenOCD is unable to connect to the JTAG device.

Change-Id: I1785fd5f5a20db9b4b574bdddfe3eab9bdc0b0bc
2018-10-18 10:06:23 -07:00
cgsfv 0a31d919e3 Corrected wrong C syntax 2018-09-17 13:53:35 -07:00
cgsfv 10a2823191 Read memory words individually if burst read fails 2018-09-17 13:53:35 -07:00
Tim Newsome 933cb875a8
Don't report exact watchpoint to gdb. (#300)
We should have a fix for #295 first.

Change-Id: Ic72a7a3fa866fbb5aaed22689adfebf9ce913b50
2018-09-06 15:39:25 -07:00
Ryan Macdonald 631f6cd55b More style fixes
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:30:17 -07:00
Ryan Macdonald 3516fd5019 Style fixes
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:29:09 -07:00
Ryan Macdonald 583c90e87c Add pass message for SBA and compliance tests
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:26:32 -07:00
Megan Wachs 4b29af433d Merge remote-tracking branch 'origin/riscv' into sba_tests 2018-08-31 09:02:55 -07:00
Megan Wachs 24513fe51f riscv-compliance: fix comment typo 2018-08-30 15:37:15 -07:00
Megan Wachs 7448f8780a riscv-compliance: fix whitespace 2018-08-30 11:30:14 -07:00
Megan Wachs 934440b80e riscv-compliance: incorporate review feedback 2018-08-30 11:26:05 -07:00
Tim Newsome a0afcba66d
Fix typo. 2018-08-29 16:05:54 -07:00
Tim Newsome 2608b8e25d
Fix strange merge. 2018-08-29 16:00:51 -07:00
Tim Newsome 164415cfbe
Merge branch 'riscv' into sba_tests 2018-08-29 15:55:30 -07:00
Megan Wachs 34ee883aef Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase 2018-08-29 15:47:54 -07:00
Tim Newsome b4b2ec7d2d
Add command to expose custom registers (#293)
* Added `riscv expose_custom` command.

Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.

Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f

* Conform to OpenOCD style.

Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf

* Free all the memory allocated by register init.

Change-Id: I04e35ab54613f99708cee85e41fef989079adefc

* Properly document `riscv expose_custom`.

Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
2018-08-29 14:22:50 -07:00
craigblackmore 7897d40099 Handle hardware watchpoints hit by RV32 loads and stores (#291)
* Add riscv_hit_watchpoint function for RV32I loads and stores

For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB
which data address has been hit. OpenOCD relies on a target-specific
hit_watchpoint function to do this. If GDB is not given the address, it
will not print the hit variable name or its old and new value.

There does not seem to be a way for the hardware to tell us which trigger
was hit (0.13 introduced the 'hit bit' but this is optional). Alternatively,
we can decode the instruction at dpc and find out which memory address
it accesses.

This commit adds support for RV32I load and store instructions
and could be extended for additional instructions in the future.

* 0.11: change debug reason for hw triggers to DBG_REASON_WATCHPOINT

This is to make sure riscv_hit_watchpoint is called to check for a data
address hit.

* Fix style issues

* Change %lx to PRIx64 to clear -m32 build errors

* Add clarifying comments/todos

* Fix types in format strings
2018-08-27 12:42:34 -07:00
Dmitry Ryzhov f54eaf0b8e Switch active rtos thread on any hart halt. (#290) 2018-08-23 16:52:12 -07:00
Tim Newsome 2a69f1bd2f
From upstream (#286)
* flash/nor: Add support for TI CC26xx/CC13xx flash

Added cc26xx flash driver to support the TI CC26xx and CC13xx
microcontrollers. Driver is capable of determining which MCU
is connected and configures itself accordingly. Added config
files for four specific variants: CC26x0, CC13x0, CC26x2, and
CC13x2.

Note that the flash loader code is based on the sources used
to support flash in Code Composer Studio and Uniflash from TI.

Removed cc26xx.cfg file made obsolete by this patch.

Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4358
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>

* flash/nor/nrf5: remove is_erased setting and autoerase before write

Cached flash erase state in sectors[].is_erased is not reliable as running
target can change the flash.

Autoerase was issued before flash write on condition is_erased != 1
Remove autoerase completely as it is a quite non-standard feature.

Change-Id: I19bef459e6afdc4c5fcaa2ccd194cf05be8a42b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4400
Tested-by: jenkins

* src/flash/tms470: remove testing of sectors[].is_erased state

The erase check routine checked sectors only if is_erased != 1

Check sector unconditionally.

While on it fix clang static analyzer warnings.

Change-Id: I9988615fd8530c55a9b0c54b1900f89b550345e9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4401
Tested-by: jenkins

* tcl/target/stm32f7x: configure faster system clock in reset-init

STM32F7xx devices need faster clock for flash programming
over JTAG transport. Using reset default 16 MHz clock
resulted in lot of DAP WAITs and substantial decrease
of flashing performance.

Adapted to the restructured dap support
(see 2231da8ec4).

Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4464
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>

* flash/nor/psoc5lp: fix compile issue on GCC 8.1.0

Issue already identified by Alex https://sourceforge.net/u/alexbour/
in ticket #191 https://sourceforge.net/p/openocd/tickets/191/

	src/flash/nor/psoc5lp.c:237:2: error: ‘strncpy’ output
	truncated before terminating nul copying 2 bytes from a
	string of the same length [-Werror=stringop-truncation]

Fix it by assigning the value to the array elements.

Change-Id: I22468e5700efa64ea48ae8cdec930c48b4a7d8fb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4563
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/arm: Add PLD command to ARM disassembler.

Updates the ARM disassembler to handle PLD (PreLoad Data) commands.
Previously handled by printing a TODO message. There are three forms of
the command: literal, register, and immediate. Simply decode based off
of the A1 encoding for the instructions in the ARM ARM. Also fixes mask
to handle PLDW commands.

Change-Id: I63bf97f16af254e838462c7cfac80f6c4681c556
Signed-off-by: James Marshall <jcmarsh@gwmail.gwu.edu>
Reviewed-on: http://openocd.zylin.com/4348
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

* mips_m4k.c: Fix build with --disable-target64

Replace PRIx64 with TARGET_PRIxADDR to avoid build problems
when --disable-target64 is used during configure.

Change-Id: I054a27a491e86c42c9386a0488194320b808ba96
Signed-off-by: Liviu Ionescu <ilg@livius.net>
Reviewed-on: http://openocd.zylin.com/4566
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tim Newsome <tim@sifive.com>

* target/arm_adi_v5: sync CSW and TAR cache on apreg write

When using apreg to change AP registers CSW or TAR we get internal
cached value not valid anymore.

Reuse the setup functions for CSW and TAR to write them.
Invalidate the cached value before the call to force the write, thus
keeping original apreg behaviour.

Change-Id: Ib14fafd5e584345de94f2e983de55406c588ac1c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4565
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/arm_adi_v5: keep CSW and TAR cache updated

The call to dap_queue_ap_write() can fail and the value in CSW and
TAR becomes unknown.

Invalidate the OpenOCD cache if dap_queue_ap_write() fails.

Change-Id: Id6ec370b4c5ad07e454464780c1a1c8ae34ac870
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4564
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl/target: Add Renesas R-Car R8A7794 E2 target

Add configuration for the Renesas R-Car R8A7794 E2 target.
This is an SoC with two Cortex A7 ARMv7a cores, both A7
cores are supported.

Change-Id: Ic1c81840e3bfcef8ee1de5acedffae5c83612a5e
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4531
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl/board: Add Renesas R-Car R8A7790 H2 Stout board

Add configuration for the Renesas R-Car R8A7790 H2
based Stout ADAS board.

Change-Id: Ib880b5d2e1fab5c8c0bc0dbcedcdce8055463fe2
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4497
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl/board: Add Renesas R-Car R8A7791 M2W Porter board

Add configuration for the Renesas R-Car R8A7791 M2W
based Porter evaluation board.

Change-Id: Iaadb18f29748f890ebb68519ea9ddbd18e7649af
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4498
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl/board: Add Renesas R-Car R8A7794 E2 Silk board

Add configuration for the Renesas R-Car R8A7794 E2
based Silk evaluation board.

Change-Id: I504b5630b1a2791ed6967c6c2af8851ceef9723f
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
NOTE: This requires SW7[1] in position 1 (default is 0)
Reviewed-on: http://openocd.zylin.com/4532
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl/board: Factor out common R-Car Gen2 code

Factor out the code shared by all R-Car Gen2 boards into a single
file to get rid of the duplication.

Change-Id: I70b302c2e71f4e6fdccb2817dd65a5493bb393d8
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4533
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* jtag/drivers/cmsis-dap: fix connect in cmsis_dap_swd_switch_seq()

The proc cmsis_dap_swd_switch_seq() is part of the SWD API for
this interface driver. It is valid only when the interface is
used in SWD mode.
In this proc there is the need to call, in sequence, first
cmsis_dap_cmd_DAP_Disconnect() then cmsis_dap_cmd_DAP_Connect().
The latter call requires the connection mode as parameter, that
inside cmsis_dap_swd_switch_seq() can only be CONNECT_SWD.

The current implementation is not correct and in some cases can
pass mode CONNECT_JTAG. Moreover, JTAG is optional in CMSIS-DAP
and passing mode CONNECT_JTAG triggers an error with SWD-only
interfaces.

Use mode CONNECT_SWD in SWD specific cmsis_dap_swd_switch_seq().

Change-Id: Ib455bf5b69cb2a2d146a6c8875387b00c27a5690
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4571
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/cortex_m: return error if breakpoint address is out of range

If the "Flash Patch and Breakpoint" unit is rev.1 then it can only
accept breakpoint addresses below 0x1FFFFFFF.
Detailed info in "ARM v7-M Architecture Reference Manual", DDI0403E
at chapter "C1.11 Flash Patch and Breakpoint unit".

Print a message and return error if the address of hardware
breakpoint cannot be handled by the breakpoint unit.

Change-Id: I95c92b1f058f0dfc568bf03015f99e439b27c59b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4535
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>

* flash/nor/stm32: Report errors in wait_status_busy

Flash operation errors that occur during algorithm programming are
reported via the algorithm return value. However, Flash operation
errors that occur during non-algorithm work (erasing, programming
without a work area, programming the last non-multiple-of-32-bytes on
an H7, etc.) generally end with a call to stm32x_wait_status_busy,
which reads the status register and clears the error flags but fails
to actually report that something went wrong should an error flag
(other than WRPERR) be set. Return an error status from
stm32x_wait_status_busy in those cases. Correct a log message
accordingly.

Change-Id: I09369ea5f924fe58833aec1f45e52320ab4aaf43
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4519
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* flash/nor/stm32: Eliminate working area leak

On a specific early-return path, an allocated working area was not
freed. Free it.

Change-Id: I7c8fe51ff475f191624086996be1c77251780b77
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4520
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* flash/nor/stm32h7: Fix incorrect comment

The name of the bit according to the reference manual is inconsistency
error, not increment error.

Change-Id: Ie3b73c0312db586e35519e03fd1a5cb225673d97
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4521
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

* target: fix 'bp' command help message

"asid" and "length" are separate arguments of the command.
Put space between them.

Change-Id: I36cfc1e3a01caafef4fc3b26972a0cc192b0b963
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4511
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* Add ARM v8 AArch64 semihosting support

This patch implements semihosting support for AArch64. This picks
code from previously submitted AArch64 semihosting support patch
and rebases on top of reworked semihosting code. Tested in AArch64
mode on a Lemaker Hikey Board with NewLib and GDB.

Change-Id: I228a38f1de24f79e49ba99d8514d822a28c2950b
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4537
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* GDB fileIO stdout support

This patch fixes gdb fileio support to allow gdb console to be used as stdout.

Now we can do something like
gdb <inferior file>

(gdb) tar ext :3333
(gdb) load
(gdb) monitor arm semihosting enable
(gdb) monitor arm semihosting_fileio enable
(gdb) continue

Here: Output from inferior using puts, printf etc will be routed to gdb console.

Change-Id: I9cb0dddda1de58038c84f5b035c38229828cd744
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4538
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target: armv8: Avoid semihosting segfault on halt

Avoid a NULL pointer dereference when halting an aarch64 core.

Change-Id: I333d40475ab26e2f0dca5c27302a5fa4d817a12f
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/4593
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl: target: Add NXP LS1012A config

As seen on the FRDM-LS1012A board.

Change-Id: Ifc9074b3f7535167b9ded5f544501ec2879f5db7
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/4594
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl: board: Add NXP Freedom FRDM-LS1012A config

An update for the K20 CMSIS-DAP firmware can be found here:
https://community.nxp.com/thread/387080?commentID=840141#comment-840141

Change-Id: I149d7f8610aa56daf1aeb95f14ee1bf88f7cb647
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/4595
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* gdb_server: only trigger once the event gdb-detach at gdb quit

When GDB quits (e.g. with "quit" command) we first execute
gdb_detach() to reply "OK" then, at GDB disconnect (either TCP
or pipe connection type), we execute gdb_connection_closed().
In case GDB is killed or it crashes, OpenOCD only executes the
latter when detects the disconnection.
Both gdb_detach() and gdb_connection_closed() trigger the event
TARGET_EVENT_GDB_DETACH thus getting it triggered twice on clean
GDB quit.

Do not trigger the event TARGET_EVENT_GDB_DETACH in gdb_detach()
and let only gdb_connection_closed() to handle it.

Change-Id: Iacf035c855b8b3e2239c1c0e259c279688b418ee
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4585
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* gdb_server: set current_target from connection's one

In a multi-target environment we are supposed to have a single
gdb server for each target (or for each group of targets within
a SMP node).
By default, the gdb attached to a server sends its command to
the target (or to the SMP node targets) linked to that server.

This is working fine for the normal gdb commands, but it is
broken for the native OpenOCD commands executed through gdb
"monitor" command. In the latter case, gdb "monitor" commands
will be executed on the current target of OpenOCD configuration
script (that is either the last target created or the target
specified in a "targets" command).

Fixed in gdb_new_connection() by replacing the current target
in the connection's copy of command context.

Change-Id: If7c8f2dce4a3138f0907d3000dd0b15e670cfa80
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4586
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>

* target/image: make i/j unsigned to avoid ubsan runtime error

	src/target/image.c:1055:15: runtime error: left shift of 128 by 24 places cannot be represented in type 'int'

Change-Id: I322fd391cf3f242beffc8a274824763c8c5e69a4
Signed-off-by: Cody Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4584
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>

* target/stm32f7x: Clear stuck HSE clock with CSS

Change-Id: Ica0025ea465910dd664ab546b66f4f25b271f1f5
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4570
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

* psoc5lp: fix erase check, add free_driver_priv

psoc5lp_erase_check() was not properly adapted to the new
armv7m_blank_check_memory() in the hot fix 53376dbbed
This change fixes handling of num_sectors in dependecy of ecc_enabled.
Also add comments how ecc_enabled influences num_sectors.

Add pointer to default_flash_free_driver_priv() to all psoc5lp flash
drivers to keep valgrind happy.

Change-Id: Ie1806538becd364fe0efb7a414f0fe6a84b2055b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4569
Tested-by: jenkins

* target: atmel samd10 xplained mini

cortex m0+ on a tiny board, with an mEDBG (CMSIS-DAP) debug interface.

Change-Id: Iaedfab578b4eb4aa2d923bd80f220f59b34e6ef9
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/3402
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl/board: add SAMD11 Xplained Pro evaluation board

Change-Id: Id996c4de6dc9f25f71424017bf07689fea7bd3af
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/4507
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* Adds SAMD11D14AU flash support.

Corrects names of SAMD11D14AM and SAMD11D14ASS per datasheet.

Change-Id: I8beb15d5376966a4f8d7de76bfb2cbda2db440dc
Signed-off-by: Christopher Hoover <ch@murgatroid.com>
Reviewed-on: http://openocd.zylin.com/4597
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* nds32: Avoid detected JTAG clock

AICE2 doesn't support scan for the maximum clock frequency of
JTAG chain. It will cause USB command timeout.

Change-Id: I41d1e3be387b6ed5a4dd0be663385a5f053fbcf9
Signed-off-by: Hellosun Wu <wujiheng.tw@gmail.com>
Reviewed-on: http://openocd.zylin.com/4292
Tested-by: jenkins
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* flash/nor/tcl: Distinguish between sectors and blocks in status messages

Use the right word in flash protect command status messages based on
whether the target bank defines num_prot_blocks. Minor message style
tidy-up.

Change-Id: I5f40fb5627422536ce737f242fbf80feafe7a1fc
Signed-off-by: Dominik Peklo <dom.peklo@gmail.com>
Reviewed-on: http://openocd.zylin.com/4573
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>

* drivers: cmsis-dap: pull up common connect code

Just a minor deduplication

Change-Id: Idd256883e5f6d4bd4dcc18462dd5468991f507b3
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/3403
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* drivers: cmsis-dap: Print version info when available

No need to wait until after connecting, might help diagnose part information by
printing earlier.

Change-Id: I51eb0d584be306baa811fbeb1ad6a604773e602c
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/3404
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* flash/nor: add support for TI MSP432 devices

Added msp432 flash driver to support the TI MSP432P4x and
MSP432E4x microcontrollers. Implemented the flash algo
helper as used in the TI debug and flash tools. This
implemention supports the MSP432E4, Falcon, and Falcon 2M
variants. The flash driver automatically detects the
connected variant and configures itself appropriately.
Added command to mass erase device for consistency with
TI tools and added command to unlock the protected BSL
region.

Tested using MSP432E401Y, MSP432P401R, and MSP432P4111
LaunchPads.
Tested with embedded XDS110 debug probe in CMSIS-DAP
mode and with external SEGGER J-Link probe.

Removed ti_msp432p4xx.cfg file made obsolete by this
patch.
Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* flash/nor/at91sam4: fix sam4sa16c flash banks and its gpnvms count

There was already a github fork that had this fixed, but as we try
to use the latest, non-modified version of all software we use,
I would like to have this fix in the next releases of OpenOCD so
that if people uses $packagemanager, they will not have issues flashing
the last part of the flash of sam4sa16c chips.

Additionally, I've added some more logging related to the flash
bank that was used, and the chip ID that was detected.

Change-Id: I7ea5970105906e4560b727e46222ae9a91e41559
Signed-off-by: Erwin Oegema <blablaechthema@hotmail.com>
Reviewed-on: http://openocd.zylin.com/4599
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins

* flash/nor/stm32lx: Add revision 'V' for STM32L1xx Cat.3 devices

Change-Id: Ic92b0fb5b738af3bec79ae335876aa9e26f5f4cd
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4600
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Avoid null target->semihosting references.

The new common semihosting code introduced a bug,
in certain conditions target->semihosting was
used without semihosting being initialised.

The solution was to explicitly test for
target->semihosting before dereferencing it.

Change-Id: I4c83e596140c68fe4ab32e586e51f7e981a40798
Signed-off-by: Liviu Ionescu <ilg@livius.net>
Reviewed-on: http://openocd.zylin.com/4603
Tested-by: jenkins
Reviewed-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* nrf5: Add HWID 0x139 (52832 rev E0)

Change-Id: I71b7471ccfcb8fcc6de30da57ce4165c7fb1f73f
Signed-off-by: James Jacobsson <slowcoder@gmail.com>
Reviewed-on: http://openocd.zylin.com/4604
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target: Fix segfault for 'mem2array'

Call 'mem2array' without arguments to reproduce the segmentation
fault.

Change-Id: I02bf46cc8bd317abbb721a8c75d7cbfac99eb34e
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4534
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>

* target/armv7m_trace: Fix typo in enum

Change-Id: I6364ee5011ef2d55c59674e3b97504a285de0cb2
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3904
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* target/armv7m_trace: Use prefix for enums

Change-Id: I3f199e6053146a1094d96b98ea174b41bb021599
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3905
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* target/aarch64: Call aarch64_init_debug_access() earlier in aarch64_deassert_reset()

On Renesas R-Car, calling 'reset halt' and 'reset init' always made DAP inaccessible. Calling 'reset' and 'halt' seperatly worked fine.
The only differences seems to be the point in time when aarch64_init_debug_access() is called. This patch aligns the behaviour.

Change-Id: I2296c65e48414a7d9846f12a395e5eca315b49ca
Signed-off-by: Dennis Ostermann <dennis.ostermann@renesas.com>
Reviewed-on: http://openocd.zylin.com/4607
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* server: Improve signal handling under Linux

Commit 5087a955 added custom signal handlers for the openocd
server process.

Before this commit, when openocd is run as a background process
having the same controlling terminal as gdb, Control-C would be
handled by gdb to stop target execution and return to the gdb prompt.

However, after commit 5087a955, the SIGINT caused by pressing
Control-C also terminates openocd, effectively crashing the
debugging session.  The only way to avoid this is run openocd in
a different controling terminal or to detach openocd from its
controlling terminal,
thus losing all job control for the openocd process.

This patch improves the server's handling of POSIX signals:
1) Keyboard generated signals (INT and QUIT) are ignored
   when server process has is no controlling terminal.
2) SIGHUP and SIGPIPE are handled to ensure that .quit functions
   for each interface are called if user's logs out of X
   session or there is a network failure.

SIG_INT & SIG_QUIT still stop openocd
when it is running in the foreground.

Change-Id: I03ad645e62408fdaf4edc49a3550b89b287eda10
Signed-off-by: Brent Roman <genosensor@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3963
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* armv7a: read ttbcr and ttb0/1 at every entry in debug state

Commit bfc5c764df avoids reading
ttbcr and ttb0/1 at every virt2phys translation by caching them,
and it updates the cached values in armv7a_arch_state().
But the purpose of any (*arch_state)() method, thus including
armv7a_arch_state(), is to only print out and inform the user
about some architecture specific status.
Moreover, to reduce the verbosity during a GDB session, the
method (*arch_state)() is not executed anymore at debug state
entry (check use of target->verbose_halt_msg in src/openocd.c),
thus the state of translation table gets out-of-sync triggering
	Error: Address translation failure
or even using a wrong address in the memory R/W operation.

In addition, the commit above breaks the case of armv7r by
calling armv7a_read_ttbcr() unconditionally.

Fixed by moving in cortex_a_post_debug_entry() the call to
armv7a_read_ttbcr() on armv7a case only.
Remove the call to armv7a_read_ttbcr() in armv7a_identify_cache()
since it is (conditionally) called only in the same procedure
cortex_a_post_debug_entry().

Fixes: bfc5c764df ("armv7a: cache ttbcr and ttb0/1 on debug
state entry")
Change-Id: Ifc20eca190111832e339a01b7f85d28c1547c8ba
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4601
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* Avoid dereferencing NULL pointer.

If a NULL pointer is passed, don't attempt to increment it.  This avoids
passing the now not-NULL pointer on and eventually segfaulting.  Also
remove some unnecessary temporary variables.

Change-Id: I268e225121aa283d59179bfae407ebf6959d3a4e
Signed-off-by: Darius Rad <darius@bluespec.com>
Reviewed-on: http://openocd.zylin.com/4550
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

* Remove FSF mailing address.

Checkpatch complains about this (FSF_MAILING_ADDRESS).

Change-Id: Ib46a7704f9aed4ed16ce7733d43c58254a094149
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4559
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

* drivers: cmsis_dap_usb: implement cmd JTAG_TMS

Simply add a wrapper around cmsis_dap_cmd_DAP_SWJ_Sequence()

Change-Id: Icf86f84b24e9fec56e2f9e155396aac34b0e06d2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4517
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

* arm_adi_v5: put SWJ-DP back to JTAG mode at exit

When SWD mode is used, current OpenOCD code left the SWJ-DP in
SWD mode at exit. Also, current code is unable to switch back the
SWJ-DP in JTAG at next run, thus a power cycle of both target and
interface is required in order to run OpenOCD in JTAG mode again.

Put the SWJ-DP back to JTAG mode before exit from OpenOCD.

Use switch_seq(SWD_TO_JTAG) instead of dap_to_jtag(), because the
latter is not implemented on some interfaces. This is aligned
with the use of switch_seq(JTAG_TO_SWD) in swd_connect().

Change-Id: I55d3faebe60d6402037ec39dd9700dc5f17c53b0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4493
Tested-by: jenkins
Reviewed-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* Add RISC-V support.

This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* usb_blaster: Don't unnecessarily go through DR-/IR-Pause

There is no need to pass through DR-/IR-Pause after a scan if we want to
go to DR-/IR-Update. We just have to skip the first step of the path to
the end state because we already did that step when shifting the last
bit.

v2:
 - Fix comments as remarked in review of v1

Change-Id: I3c10f02794b2233f63d2150934e2768430873caa
Signed-off-by: Daniel Glöckner <daniel-gl@gmx.net>
Reviewed-on: http://openocd.zylin.com/4245
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* cortex_a: fix virt2phys when mmu is disabled

When the MMU is not enabled on debug state entry, virt2phys cannot
perform a translation since it is unknown whether a valid MMU
configuration existed before. In this case, return the virtual
address as physical address.

Change-Id: I6f85a7a5dbc200be1a4b5badf10a1a717f1c79c0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4480
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* drivers: cmsis-dap: print serial if available

Helpful for sanity checking connections

Change-Id: Ife0d8b4e12d4c03685aac8115c9739a4c1e994fe
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/3405
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/cortex_m: make a variable local

The vec_ids variable is not referenced anywhere other than the vector
catch command handler. Make it local to that function.

Change-Id: Ie5865e8f78698c19a09f0b9d58269ced1c9db440
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4606
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/cortex_a: fix compile error for uninitialized variable

Commit ad6c71e151 introduced the
variable "mmu_enabled" whose pointer is passed to cortex_a_mmu()
that initialises it.
This initialization is not visible to the compiler that issue
a compile error.
The same situation is common across the same file and the usual
workaround is to initialize it to zero; thus the same fix i
applied here.

Ticket: https://sourceforge.net/p/openocd/tickets/197/
Fixes: commit ad6c71e151 ("cortex_a: fix virt2phys when mmu is disabled")
Change-Id: I77dec41acdf4c715b45ae37b72e36719d96d9283
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4619
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* mips_m4k: add optional reset handler

In some cases by using SRST we can't halt CPU early enough. And
option PrRst is not available too. In this case the only way is
to set BOOT flag over EJTAG and reset CPU or SoC from CPU itself.
For example by writing to some reset register.

This patch is providing possibility to use user defined reset-assert
handler which will be enabled only in case SRST is disabled. It is
needed to be able switch between two different reset variants on run
time.

Change-Id: I6ef98f1871ea657115877190f7cc7a5e8f3233e4
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4404
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* tcl/target: add config for Qualcomm QCA4531

The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
https://www.qualcomm.com/products/qca4531

Change-Id: I58398c00943b005cfaf0ac1eaad92d1fa4e2cba7
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4405
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* tcl/board: add config for 8devices LIMA board

More information about this board can be found here:
https://www.8devices.com/products/lima

Change-Id: Id35a35d3e986630d58d37b47828870afd107cc6a
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4406
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* tcl/target|board: move common AR9331 code to atheros_ar9331.cfg

The ar9331_25mhz_pll_init and ar9331_ddr1_init routines
can be used not only for TP-Link MR3020 board,
so move them to the common atheros_ar9331.cfg file.

Change-Id: I04090856b08151d6bb0f5ef9cc654efae1c81835
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2999
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* tcl/target/atheros_ar9331: add DDR2 helper

this helper works on many different boards, so it is
good to have it in target config

Change-Id: I068deac36fdd73dbbcedffc87865cc5b9d992c1d
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4422
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* tcl/target/atheros_ar9331: add documentation and extra helpers

Sync it with experience gathered on Qualcomm QCA4531 SoC. This
chips are in many ways similar.

Change-Id: I06b9c85e5985a09a9be3cb6cc0ce3b37695d2e54
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4423
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* tcl/board: add DPTechnics DPT-Board-v1

it is Atheros AR9331 based IoT dev board.

Change-Id: I6fc3cdea1bef49c53045018ff5acfec4d5610ba6
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4424
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* fpga/altera-10m50: add all device id

add all currently know Intel (Alter) MAX 10 device ids

Change-Id: I6a88fef222c8e206812499d41be863c3d89fa944
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/4598
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* target|board: Add Intel (Altera) Arria 10 target and related board

Target information about this SoC can be found here:
https://www.altera.com/products/fpga/arria-series/arria-10/overview.html

Achilles Instant-Development Kit Arria 10 SoC SoM:
https://www.reflexces.com/products-solutions/development-kits/arria-10/achilles-instant-development-kit-arria-10-soc-som

Change-Id: Id78c741be6a8b7d3a70f37d41088e47ee61b437a
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/4583
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* target/riscv: fix compile error with gcc 8.1.1

Fix compile error:
src/target/riscv/riscv-011.c: In function ‘slot_offset’:
src/target/riscv/riscv-011.c:238:4: error: this statement may fall through
 [-Werror=implicit-fallthrough=]
    switch (slot) {
    ^~~~~~
src/target/riscv/riscv-011.c:243:3: note: here
   case 64:
   ^~~~

Fixes: a51ab8ddf6 ("Add RISC-V support.")
Change-Id: I7fa86b305bd90cc590fd4359c3698632d44712e5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4618
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* server: explicitly call "shutdown" when catch CTRL-C or a signal

Every TCL command can be renamed (or deleted) and then replaced by
a TCL proc that has the same name of the original TCL command.
This can be used either to completely replace an existing command
or to wrap the original command to extend its functionality.
This applies also to the OpenOCD command "shutdown" and can be
useful, for example, to set back some default value to the target
before quitting OpenOCD.
E.g. (TCL code):
	rename shutdown original_shutdown
	proc shutdown {} {
		puts "This is my implementation of shutdown"
		# my own stuff before exit OpenOCD
		original_shutdown
	}

Unfortunately, sending a signal (or pressing CTRL-C) to terminate
OpenOCD doesn't trigger calling the original "shutdown" command
nor its (eventual) replacement.

Detect if the main loop is terminated by an external signal and
in such case execute explicitly the command "shutdown".
Replace with enum the magic numbers assumed by "shutdown_openocd".

Please notice that it's possible to write a custom "shutdown" TCL
proc that does not call the original "shutdown" command. This is
useful, for example, to prevent the user to quit OpenOCD by typing
"shutdown" in the telnet session.
Such case will not prevent OpenOCD to terminate when receiving a
signal; OpenOCD will quit after executing the custom "shutdown"
command.

Change-Id: I86b8f9eab8dbd7a28dad58b8cafd97caa7a82f43
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4551
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* zy1000: fix compile error with gcc 8.1.1

The fall-through comment is not taken in consideration by gcc 8.1.1
because it is inside the braces of a C-code block.

Move the comment outside the C block.

Change-Id: I22d87b2dee109fb8bcf2071ac55fdf7171ffcf4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4614
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* flash/nor/tcl.c: fix flash bank bounds check in 'flash fill' command handler

Steps to reproduce ( STM32F103 'Blue Pill', 128KiB of flash ):
> flash fillh 0x0801FFFE 00 1
wrote 2 bytes to 0x0801fffe in 0.019088s (0.102 KiB/s)
> flash fillw 0x0801FFFE 00 1
Error: stm32f1x.cpu -- clearing lockup after double fault
Error: error waiting for target flash write algorithm
Error: error writing to flash at address 0x08000000 at offset 0x0001fffe

Change-Id: I145092ec5e45bc586b3df48bf37c38c9226915c1
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4516
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/arm_adi_v5: add command "dpreg"

For very low level debug or development around DAP, it is useful
to have direct access to DP registers.

Add command "dpreg" by mimic the syntax of the existing "apreg"
command:
	$dap_name dpreg reg [value]

Change-Id: Ic4ab451eb5e74453133adee61050b4c6f656ffa3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4612
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* nrf5: add free_driver_priv

Change-Id: I429a9868deb0c4b51f47a4bbad844bdc348e8d21
Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/4608
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* rtos: add support for NuttX

This patch introduces RTOS support for NuttX. Currently,
only ARM Cortex-M (both FPU and FPU-less) targets are supported.

To use, add the following lines to ~/.gdbinit.

define hookpost-file
  eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid
  eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs
  eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state
  eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name
  eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name)
end

And please make sure the above values are the same as in
src/rtos/nuttx_header.h

Change-Id: I2aaf8644d24dfb84b500516a9685382d5d8fe48f
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Signed-off-by: Masatoshi Tateishi <Masatoshi.Tateishi@jp.sony.com>
Signed-off-by: Nobuto Kobayashi <Nobuto.Kobayashi@sony.com>
Reviewed-on: http://openocd.zylin.com/4103
Tested-by: jenkins
Reviewed-by: Alan Carvalho de Assis <acassis@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* server/server: Add ability to remove services

Add the ability to remove services while OpenOCD is running.

Change-Id: I4067916fda6d03485463fa40901b40484d94e24e
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4054
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/cortex_m: fix incorrect comment

The code sets C_MASKINTS if that bit is not already set (correctly). Fix
the comment to agree.

Change-Id: If4543e2660a9fa2cdabb2d2698427a6c8d9a274c
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4620
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl/target/stm32f0x: Allow overriding the Flash bank size

Copy & paste from another stm32 target.

Change-Id: I0f6cbcec974ce70c23c1850526354106caee1172
Signed-off-by: Dominik Peklo <dom.peklo@gmail.com>
Reviewed-on: http://openocd.zylin.com/4575
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* tcl/target: add Allwinner V3s SoC support

Change-Id: I2459d2b137050985b7301047f9651951d72d9e9e
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4427
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* target/arm_adi_v5: allow commands apsel and apcsw during init phase

The current implementation of apsel cannot be executed during the
initialization phase because it queries the DAP AP to retrieve and
print the content of IDR register, and the query is only possible
later on during the exec phase.
But IDR information is already printed by the dedicated command
apid, making redundant printing it by apsel too.
Being unable to run apsel during initialization, makes also apcsw
command (that depends on apsel) not usable in such phase.

Modify the command apsel to only set the current AP, without making
any transfer to the (possibly not initialized yet) DAP. When run
without parameters, just print the current AP number.
Change mode to COMMAND_ANY to apsel and to apcsw.

Change-Id: Ibea6d531e435d1d49d782de1ed8ee6846e91bfdf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4624
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/cortex_a: allow command dacrfixup during init phase

There is no reason to restrict the command "cortex_a dacrfixup"
to the EXEC phase only.
Change the command mode to ANY so the command can be used in
the initialization phase too.

Change-Id: I498cc6b2dbdc48b3b2dd5f0445519a51857b295f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4623
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/armv7a_cache: add gdb keep-alive and fix a missing dpm finish

Depending on range size, the loop on cache operations can take quite
some time, causing gdb to timeout.

Add keep-alive to prevent gdb to timeout.
Add also a missing dpm->finish() to balance dpm->prepare().

Change-Id: Ia87934b1ec19a0332bb50e3010b582381e5f3685
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4627
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* Add detail to `wrong register size` error.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Id31499c94b539969970251145e42c89c943fd87c
Reviewed-on: http://openocd.zylin.com/4577
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* doc: fix typo in cortex_m maskisr command

Change-Id: I37795c320ff7cbf6f2c7434e03b26dbaf6fc6db4
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4621
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/cortex_m: restore C_MASKINTS after reset

The cortex_m maskisr user-facing setting is not changed across a target
reset. However, the in-core C_MASKINTS bit was always cleared as part of
reset processing, meaning that a cortex_m maskisr on setting would not
be respected after a reset. Set C_MASKINTS based on the user-facing
setting value rather than always clearing it after reset.

Change-Id: I5aa5b9dfde04a0fb9c6816fa55b5ef1faf39f8de
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4605
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl/board: update all uses of interface/stlink-v2-1 to interface/stlink

Change-Id: I5e27e84d022f73101376e8b4a1bdc65f58fd348a
Signed-off-by: Cody P Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4456
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/riscv/riscv-011: fix compile warning about uninitialized variable

In MSYS2 MinGW 64-bit
git clone git://git.code.sf.net/p/openocd/code openocd
$ gcc --version
gcc.exe (Rev1, Built by MSYS2 project) 8.2.0
./bootstrap
./configure --prefix=
$ cat config.status | grep CFLAGS
CFLAGS='-g -O2'
make bindir = "bin-x64"

depbase=`echo src/target/riscv/riscv-011.lo | sed 's|[^/]*$|.deps/&|;s|\.lo$||'`;\
/bin/sh ./libtool  --tag=CC   --mode=compile gcc -DHAVE_CONFIG_H -I.  -D__USE_MINGW_ANSI_STDIO -I./src -I./src -I./src/helper -DPKGDATADIR=\"/mingw64/share/openocd\" -DBINDIR=\"bin-x64\" -I./jimtcl -I./jimtcl  -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/target/riscv/riscv-011.lo -MD -MP -MF $depbase.Tpo -c -o src/target/riscv/riscv-011.lo src/target/riscv/riscv-011.c &&\
mv -f $depbase.Tpo $depbase.Plo
libtool: compile:  gcc -DHAVE_CONFIG_H -I. -D__USE_MINGW_ANSI_STDIO -I./src -I./src -I./src/helper -DPKGDATADIR=\"/mingw64/share/openocd\" -DBINDIR=\"bin-x64\" -I./jimtcl -I./jimtcl -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/target/riscv/riscv-011.lo -MD -MP -MF src/target/riscv/.deps/riscv-011.Tpo -c src/target/riscv/riscv-011.c -o src/target/riscv/riscv-011.o
src/target/riscv/riscv-011.c: In function 'poll_target':
src/target/riscv/riscv-011.c:1799:6: error: 'reg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
      reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/target/riscv/riscv-011.c:1686:17: note: 'reg' was declared here
    unsigned int reg;
                 ^~~
cc1.exe: all warnings being treated as errors
make[2]: *** [Makefile:3250: src/target/riscv/riscv-011.lo] Error 1

Change-Id: I6996dcb866fbace26817636f4bedba09510a087f
Signed-off-by: Svetoslav Enchev <svetoslav.enchev@gmail.com>
Reviewed-on: http://openocd.zylin.com/4635
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-08-20 14:55:30 -07:00
Tim Newsome 684d7d6764
Remove unused variable. (#284)
Change-Id: Iedebce86b5d914ff612a4747ffdc6f776edca783
2018-08-20 12:42:30 -07:00
Svetoslav Enchev 404495b191 target/riscv/riscv-011: fix compile warning about uninitialized variable
In MSYS2 MinGW 64-bit
git clone git://git.code.sf.net/p/openocd/code openocd
$ gcc --version
gcc.exe (Rev1, Built by MSYS2 project) 8.2.0
./bootstrap
./configure --prefix=
$ cat config.status | grep CFLAGS
CFLAGS='-g -O2'
make bindir = "bin-x64"

depbase=`echo src/target/riscv/riscv-011.lo | sed 's|[^/]*$|.deps/&|;s|\.lo$||'`;\
/bin/sh ./libtool  --tag=CC   --mode=compile gcc -DHAVE_CONFIG_H -I.  -D__USE_MINGW_ANSI_STDIO -I./src -I./src -I./src/helper -DPKGDATADIR=\"/mingw64/share/openocd\" -DBINDIR=\"bin-x64\" -I./jimtcl -I./jimtcl  -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/target/riscv/riscv-011.lo -MD -MP -MF $depbase.Tpo -c -o src/target/riscv/riscv-011.lo src/target/riscv/riscv-011.c &&\
mv -f $depbase.Tpo $depbase.Plo
libtool: compile:  gcc -DHAVE_CONFIG_H -I. -D__USE_MINGW_ANSI_STDIO -I./src -I./src -I./src/helper -DPKGDATADIR=\"/mingw64/share/openocd\" -DBINDIR=\"bin-x64\" -I./jimtcl -I./jimtcl -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/target/riscv/riscv-011.lo -MD -MP -MF src/target/riscv/.deps/riscv-011.Tpo -c src/target/riscv/riscv-011.c -o src/target/riscv/riscv-011.o
src/target/riscv/riscv-011.c: In function 'poll_target':
src/target/riscv/riscv-011.c:1799:6: error: 'reg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
      reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/target/riscv/riscv-011.c:1686:17: note: 'reg' was declared here
    unsigned int reg;
                 ^~~
cc1.exe: all warnings being treated as errors
make[2]: *** [Makefile:3250: src/target/riscv/riscv-011.lo] Error 1

Change-Id: I6996dcb866fbace26817636f4bedba09510a087f
Signed-off-by: Svetoslav Enchev <svetoslav.enchev@gmail.com>
Reviewed-on: http://openocd.zylin.com/4635
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-08-14 04:32:46 +01:00
craigblackmore e4d98b83da Fix target not halting when GDB jumps to a hardware breakpoint (#283)
* Fix target not halting when GDB jumps to a hardware breakpoint

This issue affects riscv-0.11. It is caused by OpenOCD manually
stepping over hardware breakpoints to resume or step after a halt.
This is not necessary as GDB should remove and add breakpoints as
required.

At the moment OpenOCD still steps over hardware watchpoints manually
as GDB needs to know which address triggered the watchpoint and
OpenOCD does not currently provide this information.

Tested on the freedom-e310-arty using the GDB regression suite.
There is one regression which is a corner case caused by a GDB bug.
If a breakpoint is set in GDB and then the executable file is
discarded, GDB reverts to its default information about address
sizes e.g. on the freedom-e310-arty, 0x20400000 becomes
0xffff20400000. As a result, GDB is unable to step over breakpoints
set before the executable was discarded.

* Fix style issues

* Revert "Fix style issues"

This reverts commit 43e7e4b60a.

* Revert "Fix target not halting when GDB jumps to a hardware breakpoint"

This reverts commit e2717e4cfa.

* Don't step over breakpoints
2018-08-06 12:41:42 -07:00
Antonio Borneo d537cce7ef target/riscv: fix compile error with gcc 8.1.1
Fix compile error:
src/target/riscv/riscv-011.c: In function ‘slot_offset’:
src/target/riscv/riscv-011.c:238:4: error: this statement may fall through
 [-Werror=implicit-fallthrough=]
    switch (slot) {
    ^~~~~~
src/target/riscv/riscv-011.c:243:3: note: here
   case 64:
   ^~~~

Fixes: a51ab8ddf6 ("Add RISC-V support.")
Change-Id: I7fa86b305bd90cc590fd4359c3698632d44712e5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4618
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-08-01 08:26:44 +01:00
Tim Newsome a51ab8ddf6 Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-07-24 13:07:26 +01:00
Tim Newsome f0a9976eaa Mimic openrisc Makefile structure
That's better than inventing our own. Also this fixes a build issue in
the official OpenOCD regression build.

Change-Id: I042faa5b93b26e6f6b2d62bee62f21474ec74131
2018-07-18 13:42:30 -07:00
Tim Newsome 8b25d2f2ee
Merge pull request #279 from riscv/work_area
Use work area instead of riscv-specific config
2018-07-17 12:06:09 -07:00
Tim Newsome ead2a595b8 Use work area instead of riscv-specific config
Per review requested at http://openocd.zylin.com/#/c/4578/3

Change-Id: I1a8117665d38844dc1479f33b4f9b7c8f9f101c8
2018-07-16 14:43:15 -07:00
Tim Newsome 6c59fb8df4 Explain why reg_cache_values isn't per-hart.
Change-Id: Ie67e43bf89fdc68b4b2c12f37fa8a3ec3e6088ef
2018-06-20 14:52:38 -07:00
Liviu Ionescu 45921eecd8 target/riscv: fix trailing spaces 2018-06-12 23:58:56 +03:00
Liviu Ionescu 8022a315a6 target/riscv: explain why `arm` commands are used 2018-06-12 23:54:41 +03:00
Liviu Ionescu 08a814686d target/riscv: add semihosting support
- use the semihosting_common code
- to enable it, use the same commands as for arm

Signed-off-by: Liviu Ionescu <ilg@livius.net>
2018-06-12 18:21:01 +03:00
Tim Newsome 2a6332f620 Update debug defines to match spec
The main difference is we need to deal with hartsello/hartselhi. (Note
that there's a compile-time limit to 16 harts, but that can be changed.)
My largest target has 4 harts, so I can't tell how well this really
works. But it doesn't break anything.

Fixes #240.

Change-Id: Ie1a2a789b5e00f55174994568749da1cf3a33b92
2018-06-06 13:43:35 -07:00
Tim Newsome ab7ab8a867
Merge pull request #261 from riscv/trigger_enum
Delay trigger enumeration until it's required.
2018-05-25 11:52:10 -07:00
Megan Wachs bdc4355493 Merge remote-tracking branch 'origin/trigger_enum' into riscv-compliance 2018-05-22 16:27:52 -07:00
Megan Wachs a0e811580a Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-22 16:27:29 -07:00
Tim Newsome c3ffbc66e6
Merge pull request #257 from riscv/comment
Comment riscv_set_register, register_write_direct
2018-05-22 14:39:28 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required.
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22 13:07:25 -07:00
Dan Robertson 0493ff81a1
Fix posible null deref in get_target_type
A null deref occurs if riscv_deinit_target is called and the
target has not been initialized.

Change-Id: Ic34057508ed6686eb48e9fe8220110c42ba2fc5e
2018-05-22 02:57:16 +00:00
Tim Newsome 0ad060d97a Review feedback.
Change-Id: If58c011fc8d89d329d65a6c624ffb631f111cef2
2018-05-17 18:08:08 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Tim Newsome bb86173f37
Merge pull request #251 from riscv/from_upstream
From upstream
2018-05-17 16:47:48 -07:00
Megan Wachs 9a5a5c2dc9 Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compliance 2018-05-16 22:29:45 -07:00
Megan Wachs 802c3b4003
riscv: remove unexpected check during reset
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
2018-05-16 22:25:38 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome dabaf170ba blank_check_memory prototype has changed.
Just remove our nop implementation. The default behavior when this is
left NULL does the same thing.

Change-Id: I865976c694d24661941584cb0efc92fc26612316
2018-05-08 15:21:49 -07:00
Tim Newsome 2a103bae44 Don't error if hart select isn't implemented.
It's not implemented for 0.11 because we don't need it. Returning error
caused 0.11 targets to not be debuggable since change
848062d0d1.

Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07 15:16:57 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
2018-05-03 16:02:59 -07:00
Tim Newsome 67b4e2c522 counter*h registers only exist on RV32
Fixes #245.

Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-03 12:26:30 -07:00
Tim Newsome 292180fb44
Merge pull request #246 from darius-bluespec/sysbus-bugfix
Bug fixes for system bus access
2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Ryan Macdonald 0ed96e80d3 Fix more style issues
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-04-24 14:15:30 -07:00
Ryan Macdonald 9089854b84 Code cleanup from feedback. 2018-04-24 14:01:21 -07:00
Tim Newsome 9a69c1c096 Fix mingw32 build.
Change-Id: If7a57749ba8c49385a4020ce8d2d8dbb94242122
2018-04-20 16:28:24 -07:00
Tim Newsome 4593659edf Fix error messages for reset dmi timeouts.
Change-Id: I00869ba20db6f27415af8e53e7b3e67741bf894d
2018-04-20 15:10:56 -07:00
Tim Newsome ba2174249d Make encoding.h pass style guide.
There's a manual step in commenting this out, but this file changes very
rarely.

Change-Id: I332d6490940ecc81e18c3b112a7ba415331b9c86
2018-04-20 14:47:27 -07:00
Tim Newsome b5dae238a1 Fix comments in encoding.h.
This was updated in the source a long time ago:
25881d8a22

Change-Id: Ia158205d046522c6802a3a32b330759f5e65566f
2018-04-20 14:47:27 -07:00
Megan Wachs eeac4f7fd4 riscv-compliance: remove whitespace 2018-04-19 10:52:19 -07:00
Megan Wachs debf2b040a riscv-compliance: correct the HALTSUM0/HALTSUM1 checks 2018-04-19 10:36:52 -07:00
Megan Wachs ac953c71c0 riscv-compliance: add dummy comments to appease the linter 2018-04-18 16:15:07 -07:00
Megan Wachs 06fc61f464 riscv-compliance: whitespace 2018-04-18 16:10:41 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 005630d24d Use reset timeout to read dmstatus out of reset
Change-Id: I74cc6a1e006269270c5197994d21523d01206141
2018-04-18 14:31:00 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Megan Wachs 8fa81c1f97 riscv-compliance... code that compiles > code that makes linter happy 2018-04-17 16:11:03 -07:00
Megan Wachs 8ce4f787ca riscv-compliance: whitespace cleanup 2018-04-17 16:05:15 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs 401dcf7a06 riscv-compliance: make sure reset assertion and deassertion actually worked. 2018-04-17 15:47:15 -07:00
Megan Wachs f516825079 riscv-compliance: make sure not to clear DMACTIVE 2018-04-17 14:30:37 -07:00
Megan Wachs aef4888249 riscv-compliance: Fix writing hartsello 2018-04-17 11:55:50 -07:00
Ryan Macdonald e025cb320c Fix style issues. Code cleanup. 2018-04-17 10:47:44 -07:00
Megan Wachs 30e1dbdc6b riscv-compliance: fix compile errors and whitespace 2018-04-17 10:43:36 -07:00
Ryan Macdonald 4f4d5f46f1 Fix build issues 2018-04-17 10:35:32 -07:00
Megan Wachs ef684c2e68 riscv-compliance: Incorporate feedback to make tests make fewer assumptions about hte implementation and properly use OpenOCD functions 2018-04-17 10:28:13 -07:00
Megan Wachs 716c12bcaf riscv: don't supporess errors 2018-04-17 07:57:32 -07:00
Megan Wachs 4c6c4cb078 riscv: Add a TODO note we need to handle hartselhi 2018-04-17 07:53:34 -07:00
Megan Wachs fa99b8e3b1 riscv-compliance: Fix OpenOCD lint checks 2018-04-17 07:49:06 -07:00
Megan Wachs bc32aaafa4 riscv-compliance: whitespace cleanup 2018-04-16 17:49:16 -07:00
Ryan Macdonald 0b027a2854 Code cleanup. Bump debug_defines.h version 2018-04-16 17:20:31 -07:00
Ryan Macdonald bf0ffff1db Fix issue with COMMAND_PARSE_NUMBER 2018-04-13 16:09:57 -07:00
Ryan Macdonald 065671b311 Code style cleanup 2018-04-13 11:20:12 -07:00
Megan Wachs ff365173a0 riscv-compliance: fix too-narrow constant 2018-04-12 17:31:23 -07:00
Megan Wachs 2deff1b2c9 riscv: hartsel-> hartsello (not supporting hartselhi yet) 2018-04-12 16:10:45 -07:00
Megan Wachs 415da7ed4e riscv: update definitions to meet current version of spec 2018-04-12 16:06:30 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Megan Wachs 7eca2dfe5d Squashed commit of the following:
commit fb7009fc38
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55eb
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4a
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
2018-04-12 15:02:04 -07:00
Ryan Macdonald 1ba3986eb7 More test/SBA RTL debug 2018-04-12 12:26:54 -07:00
Ryan Macdonald a9b8820916 Checkpoint: debugging tests 2018-04-11 18:10:48 -07:00
Ryan Macdonald 50cd4203a5 Fix more style issues with previous commit 2018-04-11 14:41:00 -07:00
Ryan Macdonald 4191505b76 Fix style issues with previous commit 2018-04-11 14:38:51 -07:00
Ryan Macdonald cc98a14839 Added address alignment test, code fixups from review 2018-04-11 14:26:16 -07:00
Tim Newsome 1fda89c3ce Only write hartsel if we're changing it.
DebugBreakpoint went from 2.94s to 2.74s.

Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
2018-04-09 15:13:24 -07:00
Ryan Macdonald 836bd7cb69 Fix sign compare compiler error 2018-04-09 11:55:46 -07:00
Ryan Macdonald c2c52c89b1 Fix some build issues 2018-04-09 11:38:41 -07:00
Ryan Macdonald 99f2f5a272 Change #ifdef SIM_ON to be a run-time arg 2018-04-09 11:26:31 -07:00
Ryan Macdonald de329f4004 Fixed style issues in previous commit. 2018-04-09 10:54:21 -07:00
Ryan Macdonald a9b2277574 Add #ifdef to only enable sbbusyerror test in simulation. 2018-04-09 10:51:53 -07:00
Tim Newsome 238b1e9f06 Cache registers while halted.
This saves us from re-reading s0 before doing just about anything
program buffer related.

Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.

Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
2018-04-06 15:52:40 -07:00
Ryan Macdonald 7c6f6d79bc Fixed more style issues 2018-04-05 17:59:43 -07:00
Tim Newsome 5c0a9a9ee4 Just read abstractcs once when executing a command
DebugBreakpoint went from 3.41s to 3.05s!

Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
2018-04-05 17:59:07 -07:00
Ryan Macdonald d471fff3db Fixed build issues 2018-04-05 17:57:53 -07:00
Ryan Macdonald ada78cae11 Checkpoint: fix even more code style issues 2018-04-05 16:49:00 -07:00
Ryan Macdonald 8c8bed878c Checkpoint: fix some more code style issues 2018-04-05 16:42:28 -07:00
Ryan Macdonald 761aaeba98 Checkpoint: fix some code style issues 2018-04-05 16:39:33 -07:00
Ryan Macdonald 3bdb8b29a8 Checkpoint: finish debug of tests, working on hitting sbbusyerror case 2018-04-05 16:31:09 -07:00
Ryan Macdonald c5a8e1cf4c Initial commit of tests for SBA feature 2018-04-04 13:50:17 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome eeae8c4261 Add gdb_report_register_access_error command
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.

Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
2018-04-02 13:37:53 -07:00
Tim Newsome 755c6a4caa Add wall clock timeout to dmi_op()
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.

Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
2018-03-30 15:24:16 -07:00
Tim Newsome 58a2994b00
Merge pull request #231 from riscv/auth
Fix auth error message.
2018-03-30 14:02:29 -07:00
Tim Newsome 3c7c7e26a4
Merge pull request #230 from riscv/deleg
Make m*deleg regs conditional on U/S/N
2018-03-30 14:02:13 -07:00
Tim Newsome 4ee7d5373d Fix auth error message.
Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
2018-03-30 13:21:00 -07:00
Tim Newsome 224e7b4f16 Once more... Less sloppy this time.
Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset.
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
Tim Newsome 0c05aafbf8 Fix m*deleg logic.
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00
Tim Newsome b6dca68b2e Make m*deleg regs conditional on U/S/N
Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
2018-03-23 13:43:12 -07:00
Tim Newsome c534a37fc3 Make reset work again for multicore
Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
2018-03-23 12:53:24 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
Tim Newsome e5591c2584 Halt the target again if it was reset while halted
Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
2018-03-20 12:34:17 -07:00
Tim Newsome 52eabbd2a5 Add `riscv set_prefer_sba`
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
Tim Newsome d5b450c508 Fix build, broken by b7c5c5d228.
Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
2018-03-19 12:56:05 -07:00
Tim Newsome 40e0c5b976 Format error messages.
Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
2018-03-19 12:46:10 -07:00
Tim Newsome b7c5c5d228
Merge pull request #225 from riscv/old_bus2
Support v0 System Bus Access
2018-03-19 12:11:28 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset.
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
Tim Newsome fd2759a63d Clear havereset in examine() and deassert_reset().
Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
2018-03-16 15:03:31 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00
Tim Newsome 3ddbbd525d
Merge pull request #222 from riscv/dmi_commands
Add riscv dmi_read/dmi_write commands.
2018-03-15 11:32:33 -07:00
Tim Newsome 68a6812a41 Use TARGET_PRIxADDR instead of PRIx64.
Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
2018-03-09 18:02:18 -08:00
Tim Newsome 075610d495 Support v0 system bus access
This code was submitted at
https://github.com/riscv/riscv-openocd/pull/214. This change
incorporates that code, makes it build, and fixes the style to fit the
OpenOCD style guide.

I have not tested the new code because I don't have a target. It does
not cause any regressions.

Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46d
2018-03-09 18:02:18 -08:00
Tim Newsome fd9de02fac
Merge pull request #221 from riscv/reg_running
Error instead of asserting on reg access failure
2018-03-07 12:22:33 -08:00
Tim Newsome c10c570dca Fix cut and paste error message.
Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
2018-03-06 13:22:57 -08:00
Tim Newsome ddb894edf6 Add riscv dmi_read/dmi_write commands.
Mostly addresses #207.

Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.

Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
Tim Newsome 509e0e4715 Error instead of asserting on reg access failure
Instead of asserting, return error when an abstract register access
fails on running target.

Fixes #201

Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
2018-03-02 20:24:58 -08:00
Tim Newsome 84c0fdd5d1 Don't always error if a debug program fails
This is often expected, and the calling code should decide whether to
emit an error or not.

Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
2018-03-02 20:02:32 -08:00
Tim Newsome 1d00d03dc0 Remove unable to read register error message
It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.

Fixes #176

Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
2018-03-02 19:41:31 -08:00
Tim Newsome 1d9418fbb0 Only propagate register errors on some targets
Without this change, connecting to ARM targets is impossible.

Fixes #115.

Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
2018-03-01 15:11:11 -08:00
Tim Newsome 0c8235d11f
Merge pull request #216 from kaspar030/fix_some_fallthroughs
target/riscv: add some switch fallthrough comments
2018-02-28 12:31:22 -08:00
Tim Newsome d388f1cbb2
Merge pull request #218 from riscv/auth
Add `riscv authdata_read` and `riscv authdata_write` commands to support arbitrary authentication through TCL scripts
2018-02-28 09:20:31 -08:00
Tim Newsome 39716b15ab Fix authentication for multi-core targets.
When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.

Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
2018-02-27 14:22:06 -08:00
Tim Newsome 10108b623d Add `authdata_read` and `authdata_write` commands.
They can be used to authenticate to a Debug Module.

There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.

Example usage (very simple challenge-response protocol):
```
init

set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]

reset halt
```

Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
Tim Newsome 9033d99491
Merge pull request #217 from riscv/disable_target64
build with --disable-target64
2018-02-26 12:06:47 -08:00
Tim Newsome 3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
Kaspar Schleiser d570f89303 target/riscv: add some switch fallthrough comments 2018-02-20 14:31:31 +01:00
Tim Newsome 6b02ab4196 Fix build with --disable-target64
Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
2018-02-19 15:07:10 -08:00
Tim Newsome 352e6b82ed
Merge pull request #208 from riscv/run_from_trigger
Handle resuming from a trigger...
2018-02-19 13:42:50 -08:00
Megan Wachs 1b37f60969 riscv-compliance: Check that DPC is sign extended properly. 2018-02-13 15:02:31 -08:00
Megan Wachs 8f7195af76 riscv-compliance: Turn off ABSTRACTAUTO until the appropriate time 2018-02-13 13:47:14 -08:00