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Invalidate register cache on reset. 

All tests pass with `-rtos hwthread` against spike32!

Change-Id: I9051259d2702c76b7c35aeffeac020a773e0597a
This commit is contained in:
Tim Newsome 2019-01-25 13:11:06 -08:00
parent b29215735c
commit 82cf37d36c
1 changed files with 3 additions and 1 deletions
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4
src/target/riscv/riscv.c
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@ -867,13 +867,15 @@ static int old_or_new_riscv_halt(struct target *target)
static int riscv_assert_reset(struct target *target)
{
LOG_DEBUG("[%d]", target->coreid);
struct target_type *tt = get_target_type(target);
riscv_invalidate_register_cache(target);
return tt->assert_reset(target);
}
static int riscv_deassert_reset(struct target *target)
{
LOG_DEBUG("RISCV DEASSERT RESET");
LOG_DEBUG("[%d]", target->coreid);
struct target_type *tt = get_target_type(target);
return tt->deassert_reset(target);
}