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Make it build again. 

Change-Id: I851cfb8811d8e5d25760c9fddaeb99d7af1fdf6f
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2020-10-15 13:03:47 -07:00
parent 7a933ea7ad
commit e8379cda32
6 changed files with 13 additions and 244 deletions
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1
src/flash/nor/fespi.c
View File

@ -495,7 +495,6 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
struct target *target = bank->target;
struct fespi_flash_bank *fespi_info = bank->driver_priv;
uint32_t cur_count, page_size;
int sector;
int retval = ERROR_OK;
LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32,

25
src/flash/nor/gd32vf103.c
View File

@ -341,7 +341,7 @@ static int gd32vf103_protect_check(struct flash_bank *bank)
struct gd32vf103_flash_bank *gd32vf103_info = bank->driver_priv;
uint32_t protection;
int i, s;
int i;
int num_bits;
int set;
@ -369,7 +369,7 @@ static int gd32vf103_protect_check(struct flash_bank *bank)
/* bit 31 controls sector 62 - 255 protection for high density
* bit 31 controls sector 62 - 127 protection for connectivity line */
for (s = 62; s < bank->num_sectors; s++)
for (unsigned s = 62; s < bank->num_sectors; s++)
bank->sectors[s].is_protected = set;
if (bank->num_sectors > 61)
@ -381,7 +381,7 @@ static int gd32vf103_protect_check(struct flash_bank *bank)
if (protection & (1 << i))
set = 0;
for (s = 0; s < gd32vf103_info->ppage_size; s++)
for (int s = 0; s < gd32vf103_info->ppage_size; s++)
bank->sectors[(i * gd32vf103_info->ppage_size) + s].is_protected = set;
}
} else {
@ -392,7 +392,7 @@ static int gd32vf103_protect_check(struct flash_bank *bank)
if (protection & (1 << i))
set = 0;
for (s = 0; s < gd32vf103_info->ppage_size; s++)
for (int s = 0; s < gd32vf103_info->ppage_size; s++)
bank->sectors[(i * gd32vf103_info->ppage_size) + s].is_protected = set;
}
}
@ -400,10 +400,9 @@ static int gd32vf103_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
static int gd32vf103_erase(struct flash_bank *bank, int first, int last)
static int gd32vf103_erase(struct flash_bank *bank, unsigned first, unsigned last)
{
struct target *target = bank->target;
int i;
uint32_t optiondata;
uint32_t obstat;
@ -440,7 +439,7 @@ static int gd32vf103_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
for (i = first; i <= last; i++) {
for (unsigned i = first; i <= last; i++) {
retval = target_write_u32(target, gd32vf103_get_flash_reg(bank, FMC_CTL), FMC_CTL_PER);
if (retval != ERROR_OK)
return retval;
@ -467,12 +466,12 @@ static int gd32vf103_erase(struct flash_bank *bank, int first, int last)
return ERROR_OK;
}
static int gd32vf103_protect(struct flash_bank *bank, int set, int first, int last)
static int gd32vf103_protect(struct flash_bank *bank, int set, unsigned first, unsigned last)
{
struct gd32vf103_flash_bank *gd32vf103_info = NULL;
struct target *target = bank->target;
uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
int i, reg, bit;
int reg, bit;
int status;
uint32_t protection;
@ -527,7 +526,7 @@ static int gd32vf103_protect(struct flash_bank *bank, int set, int first, int la
if (last > 61)
last = 61;
for (i = first; i <= last; i++) {
for (unsigned i = first; i <= last; i++) {
reg = (i / gd32vf103_info->ppage_size) / 8;
bit = (i / gd32vf103_info->ppage_size) - (reg * 8);
@ -538,7 +537,7 @@ static int gd32vf103_protect(struct flash_bank *bank, int set, int first, int la
}
} else {
/* medium density flash */
for (i = first; i <= last; i++) {
for (unsigned i = first; i <= last; i++) {
reg = (i / gd32vf103_info->ppage_size) / 8;
bit = (i / gd32vf103_info->ppage_size) - (reg * 8);
@ -1255,8 +1254,6 @@ static int gd32vf103_mass_erase(struct flash_bank *bank)
COMMAND_HANDLER(gd32vf103_handle_mass_erase_command)
{
int i;
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@ -1268,7 +1265,7 @@ COMMAND_HANDLER(gd32vf103_handle_mass_erase_command)
retval = gd32vf103_mass_erase(bank);
if (retval == ERROR_OK) {
/* set all sectors as erased */
for (i = 0; i < bank->num_sectors; i++)
for (unsigned i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = 1;
command_print(CMD, "gd32vf103 mass erase complete");

2
src/rtos/rtos.c
View File

@ -42,6 +42,7 @@ extern struct rtos_type hwthread_rtos;
extern struct rtos_type riot_rtos;
static struct rtos_type *rtos_types[] = {
&riscv_rtos,
&ThreadX_rtos,
&FreeRTOS_rtos,
&eCos_rtos,
@ -55,7 +56,6 @@ static struct rtos_type *rtos_types[] = {
&riot_rtos,
/* keep this as last, as it always matches with rtos auto */
&hwthread_rtos,
&riscv_rtos,
NULL
};

126
src/target/riscv/riscv-013.c
View File

@ -3090,132 +3090,6 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
return result;
}
/*
* Performs a memory read using memory access abstract commands. The read sizes
* supported are 1, 2, and 4 bytes despite the spec's support of 8 and 16 byte
* aamsize fields in the memory access abstract command.
*/
static int read_memory_abstract(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
if (size != increment) {
LOG_ERROR("abstract command reads only support size==increment");
return ERROR_NOT_IMPLEMENTED;
}
int result = ERROR_OK;
LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
size, address);
memset(buffer, 0, count * size);
/* Convert the size (bytes) to width (bits) */
unsigned width = size << 3;
if (width > 64) {
/* TODO: Add 128b support if it's ever used. Involves modifying
read/write_abstract_arg() to work on two 64b values. */
LOG_ERROR("Unsupported size: %d bits", size);
return ERROR_FAIL;
}
/* Create the command (physical address, postincrement, read) */
uint32_t command = access_memory_command(target, false, width, true, false);
/* Execute the reads */
uint8_t *p = buffer;
bool updateaddr = true;
unsigned width32 = (width + 31) / 32 * 32;
for (uint32_t c = 0; c < count; c++) {
/* Only update the address initially and let postincrement update it */
if (updateaddr) {
/* Set arg1 to the address: address + c * size */
result = write_abstract_arg(target, 1, address, riscv_xlen(target));
if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg1 during read_memory_abstract().");
return result;
}
}
/* Execute the command */
result = execute_abstract_command(target, command);
if (result != ERROR_OK) {
LOG_ERROR("Failed to execute command read_memory_abstract().");
return result;
}
/* Copy arg0 to buffer (rounded width up to nearest 32) */
riscv_reg_t value = read_abstract_arg(target, 0, width32);
buf_set_u64(p, 0, 8 * size, value);
updateaddr = false;
p += size;
}
return result;
}
/*
* Performs a memory write using memory access abstract commands. The write
* sizes supported are 1, 2, and 4 bytes despite the spec's support of 8 and 16
* byte aamsize fields in the memory access abstract command.
*/
static int write_memory_abstract(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int result = ERROR_OK;
LOG_DEBUG("writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
size, address);
/* Convert the size (bytes) to width (bits) */
unsigned width = size << 3;
if (width > 64) {
/* TODO: Add 128b support if it's ever used. Involves modifying
read/write_abstract_arg() to work on two 64b values. */
LOG_ERROR("Unsupported size: %d bits", width);
return ERROR_FAIL;
}
/* Create the command (physical address, postincrement, write) */
uint32_t command = access_memory_command(target, false, width, true, true);
/* Execute the writes */
const uint8_t *p = buffer;
bool updateaddr = true;
for (uint32_t c = 0; c < count; c++) {
/* Move data to arg0 */
riscv_reg_t value = buf_get_u64(p, 0, 8 * size);
result = write_abstract_arg(target, 0, value, riscv_xlen(target));
if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg0 during write_memory_abstract().");
return result;
}
/* Only update the address initially and let postincrement update it */
if (updateaddr) {
/* Set arg1 to the address: address + c * size */
result = write_abstract_arg(target, 1, address, riscv_xlen(target));
if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg1 during write_memory_abstract().");
return result;
}
}
/* Execute the command */
result = execute_abstract_command(target, command);
if (result != ERROR_OK) {
LOG_ERROR("Failed to execute command write_memory_abstract().");
return result;
}
updateaddr = false;
p += size;
}
return result;
}
/**
* Read the requested memory, taking care to execute every read exactly once,
* even if cmderr=busy is encountered.

98
src/target/riscv/riscv.c
View File

@ -368,103 +368,6 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
return in;
}
void select_dmi_via_bscan(struct target *target)
{
jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
bscan_tunnel_data_register_select_dmi, TAP_IDLE);
else /* BSCAN_TUNNEL_NESTED_TAP */
jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
}
uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
{
/* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
uint8_t tunneled_dr_width[4] = {32};
uint8_t out_value[5] = {0};
uint8_t in_value[5] = {0};
buf_set_u32(out_value, 0, 32, out);
struct scan_field tunneled_ir[4] = {};
struct scan_field tunneled_dr[4] = {};
if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
tunneled_ir[0].num_bits = 3;
tunneled_ir[0].out_value = bscan_zero;
tunneled_ir[0].in_value = NULL;
tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
tunneled_ir[1].out_value = ir_dtmcontrol;
tunneled_ir[1].in_value = NULL;
tunneled_ir[2].num_bits = 7;
tunneled_ir[2].out_value = tunneled_ir_width;
tunneled_ir[2].in_value = NULL;
tunneled_ir[3].num_bits = 1;
tunneled_ir[3].out_value = bscan_zero;
tunneled_ir[3].in_value = NULL;
tunneled_dr[0].num_bits = 3;
tunneled_dr[0].out_value = bscan_zero;
tunneled_dr[0].in_value = NULL;
tunneled_dr[1].num_bits = 32 + 1;
tunneled_dr[1].out_value = out_value;
tunneled_dr[1].in_value = in_value;
tunneled_dr[2].num_bits = 7;
tunneled_dr[2].out_value = tunneled_dr_width;
tunneled_dr[2].in_value = NULL;
tunneled_dr[3].num_bits = 1;
tunneled_dr[3].out_value = bscan_one;
tunneled_dr[3].in_value = NULL;
} else {
/* BSCAN_TUNNEL_NESTED_TAP */
tunneled_ir[3].num_bits = 3;
tunneled_ir[3].out_value = bscan_zero;
tunneled_ir[3].in_value = NULL;
tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
tunneled_ir[2].out_value = ir_dtmcontrol;
tunneled_ir[1].in_value = NULL;
tunneled_ir[1].num_bits = 7;
tunneled_ir[1].out_value = tunneled_ir_width;
tunneled_ir[2].in_value = NULL;
tunneled_ir[0].num_bits = 1;
tunneled_ir[0].out_value = bscan_zero;
tunneled_ir[0].in_value = NULL;
tunneled_dr[3].num_bits = 3;
tunneled_dr[3].out_value = bscan_zero;
tunneled_dr[3].in_value = NULL;
tunneled_dr[2].num_bits = 32 + 1;
tunneled_dr[2].out_value = out_value;
tunneled_dr[2].in_value = in_value;
tunneled_dr[1].num_bits = 7;
tunneled_dr[1].out_value = tunneled_dr_width;
tunneled_dr[1].in_value = NULL;
tunneled_dr[0].num_bits = 1;
tunneled_dr[0].out_value = bscan_one;
tunneled_dr[0].in_value = NULL;
}
jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
jtag_add_dr_scan(target->tap, DIM(tunneled_ir), tunneled_ir, TAP_IDLE);
jtag_add_dr_scan(target->tap, DIM(tunneled_dr), tunneled_dr, TAP_IDLE);
select_dmi_via_bscan(target);
int retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("failed jtag scan: %d", retval);
return retval;
}
/* Note the starting offset is bit 1, not bit 0. In BSCAN tunnel, there is a one-bit TCK skew between
output and input */
uint32_t in = buf_get_u32(in_value, 1, 32);
LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
return in;
}
static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
{
struct scan_field field;
@ -3644,6 +3547,7 @@ int riscv_xlen_of_hart(const struct target *target, int hartid)
return r->xlen[hartid];
}
extern struct rtos_type riscv_rtos;
bool riscv_rtos_enabled(const struct target *target)
{
return target->rtos && target->rtos->type == &riscv_rtos;

5
src/target/riscv/riscv.h
View File

@ -267,11 +267,6 @@ extern bool riscv_ebreakm;
extern bool riscv_ebreaks;
extern bool riscv_ebreaku;
extern bool riscv_enable_virtual;
extern bool riscv_ebreakm;
extern bool riscv_ebreaks;
extern bool riscv_ebreaku;
/* Everything needs the RISC-V specific info structure, so here's a nice macro
* that provides that. */
static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));