Commit ff5ec942d8 made this target
always use generic arm7_9 memory write routines for software
breakpoints which resulted in inability to debug and single-step
sources in Gdb when icache is active as generic routine doesn't
invalidate it. This should fix it (and is real-life tested against
Samsung S3C2442). I expect other arm7-9 targets to be affected as
well.
Change-Id: Id7980e370ae4db47ac6b1490321d81ffe85711c0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1817
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit adds support for passing the ARM4 target description to GDB
when enabling gdb_target_description, in order to expose all banked
registers.
Change-Id: Id618bc6226f00fe83397ea28888a84b64b09cafd
Signed-off-by: Luca BRUNO <lucab@debian.org>
Reviewed-on: http://openocd.zylin.com/1810
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The out only version of jtag_add_dr_scan smells like a bogus optimization
that complicates the minidriver API for questionable gain.
The function was only used by four old ARM targets. Rewrite the callers
to use the generic function and remove all implementations.
Change-Id: I13b643687ee8ed6bc9b6336e7096c34f40ea96af
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1801
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Review and modify to conform to C99 integer types format specifiers.
Use arm-none-eabi toolchain to build successfully.
Change-Id: If855072a8f88886809309155ac6d031dcfcbc4b2
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Signed-off-by: Hsiangkai <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1794
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is used for the emulated DCC channel which is only maintained as long
as target->dbg_msg_enabled is set. Skip the saving and restoring if not
enabled to save one dap_run() per core register access.
Note that we could've probably queued all core register accesses in the
same transaction if the armv7 register framework hadn't required
synchronous register accesses.
Change-Id: I4fe6d713261ee5db42422203eb63035fdcc48891
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1848
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
It's far nicer to pass a size parameter than to split the calls to
separate wrappers which are combined to a single function anyway.
Change-Id: I716741ebf916f6f8e9358a31c8f4fe761107c82f
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1847
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is based on work from:
https://github.com/TheShed/OpenOCD-CMSIS-DAP/tree/cmsis-dap
Main changes include moving over to using HIDAPI rather than libusb-1.0
and cleaning up to merge into master. Support for reset using srst has
also been added.
It has been tested on all the mbed boards as well as the Freedom board
from Freescale. These boards only implement SWD mode, however JTAG mode
has been tested with a Keil ULINK2 and a stm32 target - but requires a lot
more work.
Change-Id: I96d5ee1993bc9c0526219ab754c5aad3b55d812d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1542
Tested-by: jenkins
This is not in the Intel hex file format specification but
some hex files may include comments (i.e. Altera USB-Blaster II
firmware) starting with '#'.
This patch makes image_ihex_buffer_complete_inner to skip
comment lines.
Change-Id: Id1f57d84d75da45e592f1c72b2b8c29193bc14e3
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1842
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.
Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If the flash is not ready (MDM_STAT_FREADY is 0) then
dap_syssec_kinetis_mdmap() would act as if the MDM_STAT_SYSSEC bit was
set and erase the flash. Wait until MDM_STAT_FREADY is set before
checking the MDM_STAT_SYSSEC bit.
Change-Id: I5c3352f625599016625ed9be8787033f49bfacea
Signed-off-by: Per Ekman <pekenator@gmail.com>
Reviewed-on: http://openocd.zylin.com/1762
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Attempt to use target_buffer_set_u32_array to convert to target endian
arrays rather reimplementing code.
This also removed cfi_fix_code_endian as its functionality is also
repeated.
Change-Id: I7c359dbe46ea791cd5f6fb18d8b0fb6895c599d3
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1783
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
if data size is bigger than transfer buffer, all portions are
transferred from/to the same target address - address advance
after successful transmission missed.
Change-Id: I79a6c388af197ac062d2807e397a2d7947400520
Signed-off-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/1679
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
Found by grepping for pointer casts.
Also rewrite to reduce scope and allocate the few bytes needed on stack
instead of on heap.
Change-Id: Ia2a369fb612e807b981ee60ebcfd9c09c2fbdf4c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1779
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
When pointer casts are needed, cast directly to the correct type, instead
of going via void*.
Don't explicitly cast to void* if it would have been done implicitly.
Change-Id: I4093209200051c5eb62847d00a4b9c8567480068
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1669
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Don't use const on pointers that hold heap allocated data, because that
means functions that free them must cast away the const.
Do use const on pointer parameters or fields that needn't be modified.
Remove pointer casts that are no longer needed after fixing the constness.
Change-Id: I5d206f5019982fd1950bc6d6d07b6062dc24e886
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1668
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This eliminates most of the warnings reported when building for
arm-none-eabi (newlib).
Hsiangkai, there're many similar warnings left in your nds32 files, I
didn't have the nerve to clean them all, probably you could pick it
up.
Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1674
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If the fpb_enabled is not set then as part of cortex_m3_set_breakpoint we
enable the fpb, however we do not signal the fpb as being enabled.
This issue only effects the hla target as the current cortex_m code enables
the fpb during cortex_m3_endreset_event.
Change-Id: I44d3fc65916c131b7a226869dd16aed5afb441b4
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1634
Tested-by: jenkins
Polling target does not change stste information
except if new state is TARGET_HALTED.
Connecting to the runing target result in target->state
not updated with retrieved value and remains "UNKNOWN"
until 'halt' command issued.
Change-Id: I803d6c0207f7f8699e648779d1df342c9ee7315a
Signed-off-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-on: http://openocd.zylin.com/1680
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add a mandatory field in struct arm7_9_common for regular, non-optimized
memory writes. Together with the existing bulk_memory_write field, this
allows variants to select any combination of implementations for regular
and bulk writes, without risking infinite loops from accidentally using
bulk writes for implementing bulk writes.
ARM 7/9 targets may now select arm7_9_memory_write_opt as their
target.write_memory implementation, which will dispatch to
arm7_9_common.bulk_write_memory if possible, or fallback to
arm7_9_common.write_memory otherwise.
To avoid loops, bulk write implementations mustn't call any other
functions than arm7_9_write_memory_no_opt() to write memory; it will
unconditionally call arm7_9_common.write_memory. If they fail, they should
simply return error to allow the caller to fallback to regular writes.
Tested on a regular ARM7TDMI only.
Change-Id: Iae42a6e093e2df68c4823c927d757ae8f42ef388
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1685
Tested-by: jenkins
Reviewed-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
We changed the actual target name quite a while ago.
This changes the actual target function names/defines to also match
this change.
Change-Id: I4f22fb107636db2279865b45350c9c776e608a75
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1626
Tested-by: jenkins
Create a single pair of relatively simple functions to handle all variants
of MEM-AP transfers. This replaces the many separate functions that
handled different access sizes and packed or non-packed transfers, which
were all implemented rather differently.
With this single implementation, performance should be more consistent,
regardless of transfer type.
Change-Id: I89960e437fc6ba68a389c074fab8eac91abcf844
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1658
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Accessing one byte of memory using a 16-bit access is not well defined.
The current implementation is forgiving and rounds up, but it should not
be relied upon.
Also, I suspect this code might fail if the byte order differs between
target and host, but I have no way of verifying it so I left it as it is.
Change-Id: I8d6a511151a194ed419f141703201f0632d84fc8
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1657
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The word count returned from max_tar_block_size() was compared with the
count of half-word/bytes in the u16 and u8 packed access functions,
causing an infinite loop if the access actually crossed the boundary.
Change max_tar_block_size() to return a byte count, and scale at the call
site.
Change-Id: I2fe9b5941eb485f3d8219cfdd29fb71e02006de4
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1649
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
For packed and/or unaligned accesses, the write functions reordered the
source buffer in place. Causing in the best case a segfault, in the worst
case silent data corruption.
Rewrite the data fetching to directly match the byte lane mapping
according to IHI0031C, without destroying the buffer.
Also slightly clean up variable usage and harmonize all the write
functions.
Change-Id: I9a01cfc5578653f9ec02043ff6b61a7a20f90d67
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1646
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for OpenRISC target. This implementation
supports the adv_debug_sys debug unit core. The mohor
dbg_if is not supported. Support for mohor TAP core
and Altera Virtual JTAG core are also provided.
Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1547
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
It's been like this since the check was added, in 5aa93a5e.
Change-Id: Iaa0586e0cd1ce57ad92735dcc3e51108a133fe96
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1640
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Due to issues reported when using the jtag mode of the stlink (see Trac #61),
the functionality/checking has been moved to the driver.
This change also fixes unaligned 32bit memory read/write for the stlink.
From testing this change also brings a 3KiB/s speed increase, this is due
to the larger read/write packets.
Change-Id: I8234110e7e49a683f4dadd54c442ecdc3c47b320
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1632
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is the first part in moving the adapter specific api back into the
driver.
The next task is to also move the hla read/write buffer size handling.
Change-Id: I86a19144b50b6de18659bfcd05b3729b2cafc051
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1621
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Now that we support the target description format we do not need
these hacks anymore, we can now tell gdb what registers we support.
Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1617
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add support for the default gdb register description type "int" and "float".
When this is given to gdb it will use the bitsize to determine the reg size.
Change-Id: Iaeed594d1feece54044128eae1baff9858bdcae0
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1622
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Half-word and byte writes using mwh/mwb has been completely broken since
bf71e34cbf, because it dispatched all writes, regardless of access size,
to target_write_buffer(), which uses as large accesses as possible.
Partially revert the commit by changing back to the correct write method.
Change-Id: I60731fc576bf4a076a7da02bee7879e121c21d17
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1628
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Currently we try and use MEM-AP packed transfers as much as possible for
8/16bit transfers. However not all targets support packed transfers, so
check before using.
Change-Id: I66256007f25ccd0c583f23db5acf6d1aa8b5e57d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1602
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
.soft_reset_halt is not necessary for nds32 target.
Remove the dependency.
Change-Id: Ic3b126d6c7eb995583a661b762627e736222fcaa
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1612
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
As GDB uses file-I/O protocol to access memory, use DMA to access
if no DCache. This commit improves the performance of Andes
Virtual Hosting.
Change-Id: I36bb2154b9f497fc4237625836cf8c7115330a60
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1580
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Modify handle_nds32_memory_access_command: do not use DCache
setting to block user's setting.
Change-Id: I2d33f893773e2a2e3e2f26edde5938ef5902609d
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1579
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If multiple read watchpoints are hit at the same time, report
any one of these hit watchpoints.
Change-Id: I8d4439aa80e4b62bb7d48bbdc0450920e2008a2e
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1576
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Do not turn on/off polling as leave/enter debug mode.
Enable polling after gdb attached, and disable polling
after gdb detached.
Change-Id: Id64459b86f44937af7ea5ccfe2cd13e31732eecf
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1574
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
1. gprof uses 2-bytes as minimum bucket size.
2. As user wants to use gprof --sum to summarize multiple
profiling data files, the range MUST be the same.
Add new arguments to specify profiling range.
Change-Id: Ie7e6afa6a4d82250e2d194a0eed2b428c1479ea1
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1572
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Profiling could be target-specific. Add .profiling interface
to target_type.
Change-Id: Ic0eea9db742971db1350a474fbbb5ed24565922b
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1571
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
I do not know what is the reasonable number of buckets.
If there are enough buckets, the result will be accurate.
I propose increase the maximum number of buckets to 128K.
If the size of program text section is less than 256KB, every
two bytes will be occupied by one buckets.
(The minimum size of one buckets is 2 bytes in gprof implementation.)
Change-Id: If9147743cefdc36f40f21e6dc73b9b28f28c9e1e
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1608
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
1. high_pc should be (maximum sample + 1) (Refer to gprof source code)
2. bucket index should be
sample offset
--------------- x (number of bucket)
sample range
For example, if minimum sample is 0 and maximum sample is 5
and the number of bucket is 3.
a = sampled_address - 0
b = 3
c = 6
(a, b, c refer to source code variables)
sampled_address = 0, => a = 0, => bucket_index = 0
sampled_address = 1, => a = 1, => bucket_index = 0
sampled_address = 2, => a = 2, => bucket_index = 1
sampled_address = 3, => a = 3, => bucket_index = 1
sampled_address = 4, => a = 4, => bucket_index = 2
sampled_address = 5, => a = 5, => bucket_index = 2
Change-Id: Ia9fa0e4d9c7183e3e9d7ceaf73e63729f07aa2ce
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1607
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Change variable name 'length' to 'numBuckets'. It is more readable.
Change-Id: I913cba0746f887adf6da401a46cd5e9ea88d2c6d
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1606
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Rewrite the target_*_buffer_default to generate as large accesses as
possible while maintaining natural alignment.
These versions are easy to extend to generate 8-byte accesses to support
64-bit targets, although it requires some conformity from all target
implementations (i.e. they need to refuse unsupported access sizes with
some defined error code, so we can try again with a smaller one).
Change-Id: I00ddcbb1d2fd33f9f8b99cb448cc93505a2421fc
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1221
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The only remaining user is arm7_9 so remove it from the target API and add
it to struct arm7_9_common to support all its variants with minimal
changes. Many of the variants are likely not correct in the cache/mmu
handling when the bulk write is triggered. This patch does nothing to
change that, except for arm946e, where it was easier to do what might be
the right thing.
Change-Id: Ie73ac07507ff0936fefdb90760046cc8810ed182
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1220
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
We already set cpsr in armv7m_build_reg_cache, so lets use it for all other
accesses to this field.
Change-Id: I19b3b21ecf1571bbea12e1be664845e6544f6fa1
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1539
Tested-by: jenkins
Make sure the target support target requests before we enable any receivers.
Change-Id: I8ce42922eaff76fb5e7a114da716f2a6585a6ab5
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1536
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Let the default handler issue an unsupported warning rather than using
empty handler routines that may/may not issue a unsupported warning.
Change-Id: Iafe3e45146981a4cfae39771c3ab7370ac86da48
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1535
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
If target does not support semi-hosting function, it has
no need to provide .get_gdb_fileio_info callback. OpenOCD
will use default function target_get_gdb_fileio_info_default.
The default function just return ERROR_FAIL and gdb_server
will treat every halted condition as normal halted and
return "Txx" to gdb.
Change-Id: I9ddb2be3a1145eae2ef5b712bdea89eb2e0fbc20
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1586
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
After the target was reset we can be sure it's not running any
algorithm.
This fixes the following failure scenario:
On my STM32F103 board after I start the firmware and then stop and try
to "load" in gdb (before doing mon reset halt), I get
Error: timeout waiting for algorithm, a target reset is recommended
However, target reset doesn't help as the flag is still there ("Error:
Target is already running an algorithm"), so I have no choice but to
restart the OpenOCD process.
I'm not sure yet what exactly prevents load from working after my
firmware is initialised, most probably some interrupt is firing and my
handler produces a fault due to garbled RAM.
Change-Id: Idd977f2780a64d84800e3abd412cffc1ab6801b0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1512
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Enable reading the SWO trace output via STLinkv2 dongles that support
it.
This adds an optional initialization parameter "trace" with which the user
specifies a destination file where SWO trace output is appended as it comes in
as well as the trace module's source clock rate.
STLink will be configured for a 2MHz SWO data rate (STLink's highest
supported rate) if the source clock is > 2MHz, otherwise the source
clock is used as the data rate directly.
For example:
trace swo.log 168000000
If "trace" is specified with a usable file path, the stlink_usb driver will
attempt to configure and read SWO trace data as follows:
- on _run(), the target's TPI and TMI are configured and the STLinkv2 is told
to enable tracing. Only generic ARM TPI and TMI registers are
configured, any MCU-specific settings (ex: pin routing) are the
responsibility of the target firmware. The configuration applied is
based on the STLinkv2's capabilities (UART emulation).
- on _v2_get_status(), the trace data (if any) is fetched from the
STLink after the target status is checked and the target is found to
be running.
- on _halt(), the STLink is told to disable tracing.
When fetching trace data, the entire trace frame is written to the output file
and that data is flushed. An external tool may be used to parse the
trace data into a more human-readable format.
Tested on ARM Cortex M4F and M3 MCUs (STM32F407 and STM32L152).
Change-Id: Ic3983d46c82ba77010c23b0e18ce7b275d917f12
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1524
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Currently, there is no way to notify gdb that program has exited.
Add new target_debug_reason called DBG_REASON_EXIT to notify gdb
the condition has occured. If the debug reason is DBG_REASON_EXIT,
gdb_server will send 'W' packet to tell gdb the process has exited.
Change-Id: I7a371da292716a3e6ac4cc2c31b009a651fe047a
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1242
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The File I/O remote protocol extension allows the target to use the
host's file system and console I/O to perform various system calls.
To use the function, targets need to prepare two callback functions:
* get_gdb_finish_info: to get file I/O parameters from target
* gdb_fileio_end: pass file I/O response to target
As target is halted, gdb_server will try to get file-I/O information
from target through target_get_gdb_fileio_info(). If the callback function
returns ERROR_OK, gdb_server will initiate a file-I/O request to gdb.
After gdb finishes system call, gdb will pass response of the system call
to target through target_gdb_fileio_end() and continue to run(continue or step).
To implement the function, I add a new data structure in struct target,
called struct gdb_fileio_info, to record file I/O name and parameters.
Details refer to GDB manual "File-I/O Remote Protocol Extension"
Change-Id: I7f4d45e7c9e967b6d898dc79ba01d86bc46315d3
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1102
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
In GDB remote serial protocol, the stop reply packet could contain more
detail stop reason. The currently defined stop reasons are listed below.
* watch
* rwatch
* awatch
* library
* replaylog
This commit adds stop reason, watch/rwatch/awatch, in stop reply packet for
just hit watchpoint. As manual indicates, at most one stop reason should be present.
The function needs target to implement new hook, hit_watchpoint. The hook will fill
the hit watchpoint in second parameter. The information will assist gdb to locate
the watchpoint. If no such information, gdb needs to scan all watchpoints by itself.
Refer to GDB Manual, D.3 Stop Reply Packets
Change-Id: I1f70a1a9cc772e88e641b6171f1a009629a43bd1
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1092
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Documentation says they should be given values in milliseconds,
DEFAULT_HALT_TIMEOUT matches that too.
Change-Id: Ic1a30fa90f75b412c43fe50ba187d01c3d0a5fba
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1504
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
When I do not have the JTAG adapter connected to the target, I often
end up always reading 1s from the chain. If the OpenOCD is configured
to connect to an ETM-equipped target (i.MX25 ARM9 in my case), this
results in writing garbage values in the etm reg_cache as the ETM bit
fields for the comparators, counters and outputs are wider than the
amount of entries in the corresponding arrays. This later results in a
segfault in the first etm_reg_lookup() call.
Change-Id: Ied81fdbf3a53a3dd749e2e5e97adf86c012df575
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1505
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
EJTAG 1.5, 2.0 and 2.5 have different breakpoint register addresses.
This patch add support of EJTAG 2.0, which is part some broadcom
SoCs.
This work was testet on Broadcom BCM7401.
Change-Id: I4b0ee23871fa9205f9001b7c9165e7b6ebe9ccbf
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1464
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Split function mips32_configure_break_unit
to mips32_configure_ibs and mips32_configure_dbs
to make code more readable.
This will probably make work easyer with differnet EJTAG versions.
Change-Id: I666f949fd7bc3656bdf75e7bcaadb164f15855dd
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1463
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On some CPUs, like bcm7401 with EJTAG v2.0 we can have situation where
CPU do not stops execution. For example, all CP0 commands will have this issue.
In this case we should some hove recover our session. Currently
jump to 0xff20.0200 seems to be good option. If it brake some thing on
newer EJTAG, then check for EJTAG v2.0 should be added.
Change-Id: Icd8841f38a1a85e0f7682b6dc358af8dfaae0744
Signed-off-by: Oleksij Rempel <bug-track@fisher-privat.net>
Reviewed-on: http://openocd.zylin.com/1353
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This instruction we will need to make jump to 0xff20.0000
Change-Id: Ic723e683e8848492cd8e186e71fd668dbd1d97e6
Signed-off-by: Oleksij Rempel <bug-track@fisher-privat.net>
Reviewed-on: http://openocd.zylin.com/1338
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Some parts of code are version specific. It will be easier
if we extract ejtag version and store it some where.
Change-Id: I8f9addc42108cba5ae9d61b8ade8f9d7f02a0fb5
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1462
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On slow targets we sometimes get false messages about timeouts due to poll
using 1sec rather than the default 5sec timeout.
Change-Id: Icc81c78e0ca86cebf9eeb2f5307cf7a82f1f4ee8
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1466
Tested-by: jenkins
Added missing breakpoint/watchpoint implementation to dsp563xx target.
Implementation is not yet complete, which means it does not leverage all
available features of the once debug interface.
This does NOT use the openocd breakpoint/watchpoint command because of
the "special" memory address spaces (X/Y/P/L) of the 56k DSP series.
Change-Id: I6840a3ff1e6fdebb38ab7758f164886aff773af6
Signed-off-by: Bernhard Kiesbauer <bernhard@kiesbauer.com>
Reviewed-on: http://openocd.zylin.com/1468
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
gcc (Gentoo Hardened 4.6.3 p1.13) produces a warning about the variable
assigned but not used. write() can sometimes write less than the specified
count so it's marked with warn_unused_result in the system headers and its
return value can't be ignored. The most correct solution would be to have a
loop writing the buffer until all bytes are written or an error is
returned but here it's impractical.
Change-Id: I75f7482e2b26fe0e6d70d34947518d3a8f0afe5c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1490
Reviewed-by: Laszlo Papp <lpapp@kde.org>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Double const is bogus and breaks the build on Clang 3.3.
Change-Id: I9f9394d17f66289ac74ae6dd48f3165483b72e9e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1489
Reviewed-by: Laszlo Papp <lpapp@kde.org>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
On XScale architecture, to write debug control register DCSR
and activate JTAG debug (ie. to choose Halt Mode), the
enabling can only be done while the board is held in reset
state (ie. PXAxx #RST line held low).
The current implementation writes to the register before
asserting the SRST line. Swap the order to activate the SRST
line before writing to DCSR.
Change-Id: I914b9d53d39bdeb5fe4ee5e11068cafafe0da4d2
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/1458
Tested-by: jenkins
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Replace hexadecimal masks for vector catching with words
representing the caught exception, such as dabt for data
abort, etc ...
This way, the new xscale command is :
- xscale vector_catch
Reads back to the user the current vector catching status
- xscale vector_catch reset dabt pabt
Sets the caught vectors to data abort and prefetch abort
for example.
This is mostly taken from Cortex-M3 openocd code.
Change-Id: I66591d5796f0e07f0f31edc8d28722e1e48aa8c5
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/1456
Tested-by: jenkins
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This prevents segmentation fault that can occur on cortex_a targets if
gdb connection is established before it's halted and CPSR examined.
Change-Id: Id996200e0fd95440496509c1fecaabbdbf425e23
Tested-by: Henrik Nordstrom <hno@squid-cache.org>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1446
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
soft_reset_halt was only really intended for the older arm arch, eg. armv4/5.
Newer arch such as armv7m/mips do not need this as they have better alternatives.
Change-Id: Ifb360680b7e4bfa5365f3c79d82574bded952b45
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1442
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
mips_m4k_bulk_write_memory was only called from target_write_buffer as an
optimization when the word count was large enough.
Remove mips_m4k_bulk_write_memory from the target type, causing the default
implementation to call the regular mips_m4k_write_memory instead.
Perform the dispatch to bulk write in mips_m4k_write_memory, enabling the
optimization for target_write_memory() writes with size 4, in addition to
target_write_buffer() writes.
It also enables making the choice of bulk write vs regular write
specifically for the architecture and not relying on the generic target
code to make a sensible decision.
Change-Id: I295f21a67ceaa195802403f2518ea2e0a025c1c7
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1215
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
If mem_ap_sel_write_atomic_u32 fails then tmp_buff may not be released.
Detected by clang.
Change-Id: I3d5416bd47d0eea61f61ec02ac5e43c82f114108
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1433
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change scope of the variable gdb_reg_list_idx from global to module.
Change-Id: Ib8273c0769c11c1d5a338e4711efbddb8e8a0243
Signed-off-by: Jim Norris <u17263@att.net>
Reviewed-on: http://openocd.zylin.com/1441
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Add target code for Andes targets.
Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Andes AICE uses USB to transfer packets between OpenOCD and AICE.
It uses high-level USB commands to control targets instead of using
JTAG signals. I define an interface as aice_port_api_s. It contains
all basic operations needed by target-dependent code.
Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1256
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This file is used by all the Cortex-M family not just Cortex-M3.
Change-Id: Ie8680535b220c66bb8fcd862510407a46a73e8a0
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1429
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Native compilation on RaspberryPi with
gcc (Debian 4.6.3-1) 4.6.3
Target: arm-linux-gnueabi
ends with error:
cortex_a.c: In function 'cortex_a8_read_apb_ab_memory':
cortex_a.c:2063:40: error: cast increases required alignment of target type [-Werror=cast-align]
cc1: all warnings being treated as errors
Also check for malloc failure.
This patch is compile-tested only.
Change-Id: I580c505424d03ac3a565de54182db22277c52ac1
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1369
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This should cover all the cases when RESET_SRST_NO_GATING is set
without RESET_HAS_SRST. This might happen when RESET_SRST_NO_GATING is
automatically set by a target code (and not from tcl).
However, there're some other places (mips_m4k, arm7_9_common) where
adding RESET_SRST_PULLS_TRST would lead to trying to use SRST even if
it's not present. Currently it's impossible for the user to enable
that flag without enabling SRST.
Change-Id: Ib1c6f68feed0b8057d55afd5f260bb22ab332ced
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Commit d9ba56c295 did a bunch of
renaming of cortex_a8 to cortex_a, including the names in config
files. However that introduced a regression as the name in target_type
struct remained unchanged.
This adds the last missing bit: actual renaming of the target name as
understood by OpenOCD.
Also change the (hopefully) last instance of using it in the supplied
config files, namely from imx6.cfg.
Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1420
Tested-by: jenkins
Reviewed-by: Chris Johns <chrisj@rtems.org>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
There seems to be a few missing semihosting calls. I
am not sure why this one is actually missing, since it
seems simple enough to implement. It was tested using
an HTC HD7 connected to openocd through a "home brew"
ftdi 4232H board.
Change-Id: Ie17dc96c6d48227a3dc9ff1e21201a85498a10b1
Signed-off-by: Brandon Warhurst <roboknight@gmail.com>
Reviewed-on: http://openocd.zylin.com/1345
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Rename cortex_a8 target to use a more correct cortex_a name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: I0eb1429c9281321efeb444b27a662a941a2ab67f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1130
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1129
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Sometimes the target may have breakpoint registers set from a previous
debug session, we can either sync them or as we have chosen here clear them.
Change-Id: I439a623ebbf010246a70e5596d04aa7d546da731
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1363
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Seems commit fc2abe63fd caused a regression
in that the arm reg cmd no longer worked. The issue was caused because we
changed the value of ARM_MODE_THREAD which was being checked in arm_init_arch_info.
Change-Id: Id571d4ab336d1b0e2b93363147af245d24b65ca5
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1362
Tested-by: jenkins
Reviewed-by: Luca Bruno <lucab@debian.org>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Now all the functions with only fetch accesses are modified.
The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work
at the same scan rates as the other pracc functions, but it needs higher scan_delays
to work.
Change-Id: Ifb31d8ea6de9d22674385782913d221a2494dbbf
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1196
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified.
mips32_cp0_read() is very similar to mips32_read_u32() with one store access.
mips32_pracc_read_regs() is the only function that can not be executed from only one queue.
Now this function is modified to use reg8, it saves all the registers but does not restore reg8.
To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in
mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and
restore it from ejtag info instead of using DeSave for save/restore.
Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1195
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Each pracc function defines a variable ctx of type struct pracc_queue_info.
To simplify the code tree auxiliary functions are defined: pracc_queue_init(), pracc_add() and
pracc_queue_free().
The second parameter in pracc_add() is the store address if the instruction is a store at dmseg,
otherwise it should be 0.
The code is executed by mips32_pracc_queue_exec(). If ejtag_info->mode is 0 mips32_pracc_exec()
is called and it should work like with current code.
To generate the delay between scans the number of clock ticks are calculated with the help of
jtag_get_speed_khz(). Due to delays in the execution of each single ftdi instruction the number of ticks
are higher as it should be, specially at higher scan rates.
mips32_pracc_read_u32() should now work with the new code.
Change-Id: I471590a4fc89b56af10bd46c48767b4c64de154f
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1194
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1193
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add command to fix CSW_SPROT in register AP_CSW.
This solves dap apmem access in non secure access.
Change-Id: I7cfcb6434d75f5cfd4a2630a059901cdeea010ce
Signed-off-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-on: http://openocd.zylin.com/1276
Tested-by: jenkins
Reviewed-by: mike brown
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary.
Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack:
mips32_pracc_read_u32()
mips32_cp0_read()
mips32_pracc_write_mem_generic()
And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack.
Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug
mode and can be modified by mips32_pracc_write_regs() when leaving debug mode.
There is no need to read their values from the processor registers every time.
The fields reg8 and reg9 are added to struct mips_ejtag to store these register values
and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order
to store them before any other function needs to restore these registers.
For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed,
should be made after calling mips_m4k_debug_entry().
For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code,
single word read takes now 10 instead of 12.
This patch is really the first in a set of patches for an alternate m4k pracc code
much faster that current code. At least for me with pic32mx works fine.
Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1146
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
In this function after loading the handler code and the jump code there is a call
to wait_for_pracc_rw() to verify that a pracc access is pending.
Next the address is read to verify that the handler is running, the address should be at
fastdata area.
Next, another call is made to wait_for_pracc_rw(). This call is not needed, we now already
that a pracc access is pending.
Better we call this function before loading the end address to be sure it is loaded correctly.
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Change-Id: If311450ea634786fc28cf1a8e18ed24ce5257d20
Reviewed-on: http://openocd.zylin.com/1142
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
To show up the fail try to step with the core clock set to 31.25Khz
and with a ftdi/hs adapter or with a wiggler, -not with ft2232-.
The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail.
The code exits with error because the pracc address is at 0x0.
It also fails when using the "all" register, but in this case the code works without any message because the
pracc address is at 0xff202004 when it fails.
I never saw this fail with the core clock set to 500Khz or higher, but ...
The workaround simply puts a 1 ms delay after the execution of the DERET instruction.
Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1139
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Fixes system hang for devices that don't ignore
transactions to bad addresses.
Change-Id: Ia98344d7efc12951ef79dbc82b8f792b70a22cee
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/1115
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Moved JTAG code out of transport-neutral file (arm_adi_v5.c) into
transport specific file (adi_v5_jtag.c).
Added ap_block_read to dap_ops interface (arm_adi_v5.h) to support
the move.
Change-Id: I796d3984f138aad052b97c77ac9c12ffd1158f74
Signed-off-by: mike brown <mike@theshedworks.org.uk>
Reviewed-on: http://openocd.zylin.com/1277
Tested-by: jenkins
Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This regression was caused due to the recent addition of R4 support and
the removal of the bulk_write_memory handler.
Change-Id: Ide692737f235c0e9906becb6f3502ba52c5907aa
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1246
Tested-by: jenkins
The only caller was arm_nandwrite(). Replace that call with
target_write_buffer() instead, which in turn may end up calling the same
bulk_write_memory target API function.
Change-Id: If34c7474df5cf14af3b732fb4774816818f28e79
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1214
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Remove dummy implementations from all targets except arm7_9 and mips, which
are the only ones with real implementations. Replace with a single default
implementation simply calling target_write_memory().
Change-Id: I9228104240bc0b50661be20bc7909713ccda2164
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1213
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Move the global target back off timer to the target struct. This will
fix the wrong error handling with multi target devices like smp systems.
Change-Id: Ia327182ed5d13ca87323700017a8c40ecc6b25a3
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/1179
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Because we were always running using target state TARGET_RUNNING target
algorithm's were a bit verbose compared to other targets.
This brings the hla target inline with the other targets.
Change-Id: I3a257fdc878b87660fac8b5eca22b421eee5b349
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1134
Tested-by: jenkins
The was missed when the armv7m was moved over to using the std arm
core_cache, probably because it is disabled by default.
Change-Id: I2f5a18ef6dd783b36e8c29f4c52379104bda4583
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1138
Tested-by: jenkins
This makes sure we are using privileged mode when executing any loaders.
Change-Id: I18bf32ec92e1c76a66ab25e3712652bc3650b332
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1108
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Make sure we restore the core mode after executing any algorithm.
We also now check that we actually need to swap the core mode, we may
already be in the correct mode.
Change-Id: Ia48af2c108e0f9868aae241bf25f60323503f092
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1107
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This removes the armv7m::core_cache and uses the generic arm::core_cache.
Change-Id: If854281b31486cea8be005008f6a71a691b4c208
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/968
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This simplifies the armv7m_core_reg structure ready for the move to using
the generic struct arm_reg.
Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/967
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
To simplify things change over to using the generic core_mode struct rather
than maintaining a armv7m specific one.
Change-Id: Ibf32b785d896fef4f33307fabe0d8eb266f7086f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/966
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The makes sure the DWT component is always enabled so that watchpoints
work as expected.
This does need merging into the existing cortex_m logic, however at the
moment this is non trivial.
Change-Id: Ic6cccd1badb51f70a2ca8ea9ab6923788a94c1bf
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1122
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This is only minimal support to enable use to catch a Hard Fault in
the stm32l flash bootloader.
Change-Id: I21d6a11893e2f1d173ebff1a651d6f52bf6eec32
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1103
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: jenkins
Other adapters (TI ICDI) that use this driver can use a larger
read/write buffer size than the original stlink could.
Change-Id: I9beb7748049097cbe29a2340799c450bd74e199d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/948
Tested-by: jenkins
Watchpoints were not being enabled when the hl adapter target was resumed.
This effects both stlink and icdi interfaces.
Change-Id: Ia9f8a9415be97a467cd099b63b6bc9f7f37d0c0d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/931
Tested-by: jenkins
As part of the switch to using the hla for the stlink interface we rename
the cmds to a more generic name.
Update scripts to match new names.
Also add handlers for deprecated names.
Change-Id: I6f00743da746e3aa13ce06acfdc93c8049545e07
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/921
Tested-by: jenkins
This enables us to change the target name without breaking any
target scripts.
Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/919
Tested-by: jenkins
Fix for bug introduced in in mips smp support code
in the resume logic that is checking for wrong return
value.
Change-Id: Ice3e0069f936b556fecc338ccc12ddba38deeaf6
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1048
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If target is disabled at init, then is examined using 'arp_examine', it
can get to cortex_a8_poll with the target state being unknown.
Change-Id: Ifffb345bf971d275d2eb1912648b29f0a75f6ccc
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/954
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This change adds smp debug support for mips platforms. The change
leverages the exiting gdb smp support as mentioned in the OpenOCD
documentation for using gdb in smp environemnt. Added commands
smp_on, smp_off, smp_gdb to control the smp mode. The implementation
also provides a way to send Jc packet and toggle the gdb display core
context as well.
Change-Id: I0835a5aed1844b6ebf8291582912f20695346003
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/937
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is a minor change to log EJTAG version 4.x and 5.x
as valid versions when debug log is enabled.
Change-Id: Ie20458d033c6d22842cb4a31b56765d4ba2ff123
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/936
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Fixes issue with big endian hosts and mis-aligned data on some hosts.
Fixes unaligned access exception on hosts that do not support unaligned
access when debugging some arm targets.
Signed-off-by: Jason Moehlman <jmoehlma@linux-software.com>
Change-Id: I6bc6fb1b3c3565b256674b9ef43ed2afd14f5178
Reviewed-on: http://openocd.zylin.com/996
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
No function writes to MIPS32_PRACC_PARAM_IN addresses and probably has no much sense.
Any attempt to write to those addresses should be an error.
Change-Id: Iebea5fa9954e2cd56ad34976dd7d25009c6e6388
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/975
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Current code needs 101 pracc accesses for this function, this code needs 12 less.
There is a singularity in this code, is the only function that restore
a register from param out instead from pracc stack. Obviously the register
was previously stored at param out. This save 2 pracc accesses.
Change-Id: Ie95b6f983a3198dafc0eab2dd5acc11f871a8d83
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/958
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
All the the loads are done with lui and ori instructions, there is
no need to save any register, they will be overwritten.
Like in the previous patch, for speed optimization in write code,
same instructions can be saved if the lower half word or the upper
half word is 0.
If the lower half word is 0, it can be loaded with only a lui instruction.
If the higher half word is 0 it can be done with an ori instruction with register 0.
This code saves 10 pracc accesses at a minimum, and 40 at a maximum,
obviously if register 2 to 31 are 0 or a half word is 0
Current code needs 91 pracc accesses.
Change-Id: I892c5b440191d0c7a474c96845d41c373b7fc637
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/957
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
All the writes are done by the new function mips32_pracc_write_mem_generic().
The code is similar to the read generic code.
The reuse of register 15 as memory base address saves 3 pracc accesses.
The first write takes 13(12) pracc accesses and for additional writes 3(2).
Loading miniprograms should take 25% less time and loading fastdata transfer
handler code should be over 2x faster.
Change-Id: Ia3b24ba084af33be99da19f00a7fd4d1b291f350
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/956
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Really nothing new that not explained in previous patches.
The code is expanded as needed, there are no loops in pracc code.
For the first value pracc accesses are reduced from 39 to 16
and for aditional values from 10 to 3.
dump_image should work around 3x faster.
Change-Id: I37c9b13395c09eb52a91f10cdb6cbaedef8ab98b
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/955
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This function is highly optimized, there is not much to
improve.
Loading the base address for pracc access with the new
defined MIPS32_PRACC_BASE_ADDR saves one instruction.
The memory address is loaded in too steps. First the upper
address is loaded. The lower address is passed as an offset in
the memory load instruction.
The offset is signed, if the lower address is in the range of
0x8000 to 0xffff the offset is a negative value, and the upper
address must be incremented by 1.
Pracc accesses are now 12 instead of 14.
Change-Id: I286945b240ed5c5d5cc540780a41a8a5fa075da3
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/952
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is
possible to load the base address with a lui instruction and
only one pracc access.
Offsets to the pracc code addresses are defined to simplify the code
and probably make it a bit more readable or self-explained.
Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/951
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
The function mips_ejtag_read_debug() is defined in mips_ejtag.c
and is called only by mips_m4k_debug_entry() for reading the
CP0 debug register. The comment in this function is obviously wrong.
There is a generic function to read CP0 registers with similar code.
A call to mips32_cp0_read() should work in the same way.
The purpose of reading the debug register is to test if the DSS
bit is set and clear the SSt bit.
It is faster and easier if the SSt bit is cleared without any check.
Remark: DSS bit set only means that a debug single-step exception
ocurred, but it is not possible to step over a sdbbp instruction,
in this case DSS will not be set and the SSt bit not cleared by code.
Resume command at another address will step, so really the behavior
is not the same.
Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/950
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The code is a bit large compared to mips_ejtag_step_enable().
With the mips32 xori instruction the code can be
reused.
The number of pracc accesses are reduced from 18 to 7.
Change-Id: If3974ebd64da4461c22b089796646990e68e1b72
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/944
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
An issue was observed when using an async algorithm with a target that had
not been previously reset beforehand. The target would enter a infinite
loop within target_run_flash_async_algorithm.
Add a timeout that will at least prevent this issue from happening. and also
suggest the user resets the target.
Change-Id: I5277e0d64e252d3d353e8d5bc9889a37fdc63060
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/949
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The order of the mrc/mcr command matches the ARM Architecture Reference
Manual. This patch corrects the help information for mrc/mcr.
Change-Id: I1f0e6a628a3644124591a6aa291b8a58cfd93b44
Signed-off-by: Karl Kurbjun <kkurbjun@gmail.com>
Reviewed-on: http://openocd.zylin.com/914
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If we halt due to a breakpoint make sure that we do not remove it during a
step, only remove breakpoints we have created.
Change-Id: I060168e54e53637d4fbf3cbcf62072efdb353807
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/947
Tested-by: jenkins
This occurs when stepping past a breakpoint on a even address with
maskisr option set to auto
With -d3 the following log message appears in this case:
"Debug : Interrupt handlers didn't complete within time,
leaving target running"
Cause : Given a breakpoint is set on the lower half word and the PC is on
the upper half word. When another breakpoint is now set on the current PC
then resuming the core will not result in a break on the newly set
breakpoint. This has been observed on a STM32F1x, STM32F2x (CM3) but not
on a STM32F0x (CM0). It's not clear if this is a STM32F1/F2 only or a
general CM3 problem.
Change-Id: I384813f3bfdf935373b5e23cdb2d7f243c70cc00
Signed-off-by: Peter Horn <peter.horn@bluewin.ch>
Reviewed-on: http://openocd.zylin.com/864
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The stacking of ChibiOS/RT depends on the usage of an FPU. If the
FPU is enabled the FPU registers are also saved on context switch.
This patch adds automatic detection of FPU for armv7m targets.
Note: With this patch, openocd will only output an error message
warning that the FPU is enabled.
For further FPU support, the correct stacking information
also needs to be added.
Change-Id: I0984cbd9180f247ba2fa610e74a6413cc54239ea
Signed-off-by: Matthias Blaicher <matthias@blaicher.com>
Reviewed-on: http://openocd.zylin.com/961
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
All the packets received will be at start of the packet buffer, so use
more efficient strncmp.
Change-Id: Ib9c45d8f53425367006b1f880c1bde27f03a6cf9
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/932
Tested-by: jenkins
Reviewed-by: Matthias Blaicher <matthias@blaicher.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
Seems after a reset the stlink is not clearing the vector catch (VC_CORERESET)
in the Debug Control Register.
This has the side effect if the user presses an external reset the core will
halt, this patch fixes that.
Change-Id: Ic3b2c3991b79cacbbd901c02b79613c2e204e71f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/905
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
If the target does not support SYSRESETREQ we fall back to using VECTRESET.
This however does not reset the peripherals and we issue a warning to the user
to suggest using a reset-init script.
Also suggest that using hardware srst will give them the same functionality
as using SYSRESETREQ.
Change-Id: Ie1781c4b849fed66c52222e6539735537c879fb3
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/802
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Always scan out all bits, but make sure only the allowed number of bytes
end up in the caller-provided buffer. Discard the rest by adding another
scan field when size < 4.
Rewrite the endianness callback to avoid reading outside allocated memory.
Make it directly usable as a callback without the need for a wrapper. Move
the shared callback to a more suitable home in arm7_9_common.
This fixes the regressions introduced in commits
991ed5a2b6cb90d32e38
and
c3074f377c
Change-Id: Ia8bde8c5a9844e89a1d6c0bc8534cd26f02f8d11
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/789
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The function wait_for_pracc_rw() fails if Pracc bit is 0.
The variable ejtag_ctrl is loaded with the content of the
control register in the first scan.
In the second scan Pracc bit is scanned out as 0, letting
the proccesor go. The result is unpredictable.
All the strange data corruption when scanning at certain
frequencies, or the strange delays needed when entering
or leaving fasdata area are retated to this bug.
Now the code works at any scan frequency, tested up to 15000Khz
and indepently of processor speed, tested at 31.25Khz and 4/8Mhz.
Change-Id: Iedfd81d06d6af4bc738a521f720e42323025b268
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/769
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
working_area::user has never been used so lets remove it.
Change-Id: I1200311b34248549c1fe30c9f675e6129b7bebee
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/781
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Check that the target is valid before calling any target functions.
Change-Id: I538fccc79d5ec89976e14beab02cb20490b299bb
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/766
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Not just print it.
This enables scripts to analyze valuable config options of
arm946e-s cores, do internal BIST memory tests and more.
Be careful to flush caches before disabling it.
Do not forget that BIST test overwrites memory.
- cp15 rewritten from COMMAND_HANDLER to jim_handler.
Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb
Signed-off-by: Alexander Osipenko <sipych@gmail.com>
Reviewed-on: http://openocd.zylin.com/694
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Cache type register C0.C is read-only, and display
hard core configuration information.
This information is unlikely be changed in runtime.
- removed C0.C access when result is not used in
arm946e_invalidate_dcache()
- access C0.C only once per target, store result
in cp15_cache_info field of target structure
- fix cache index count calculation
Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a
Signed-off-by: Alexander Osipenko <sipych@gmail.com>
Reviewed-on: http://openocd.zylin.com/693
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Global variables 'dc' 'ic' had been used in the code
to keep target's state of D-cache and I-cache
on debug entry.
This may lead to incorrect operation in configurations
with multiple cores and unequal cache states.
Fix: move cache state to the appropriate bits of the
'cp15_control_reg' field (already present but unused).
Vaule of cp15 control register stored here on
arm946e_post_debug_entry(), and analyzed later
in arm946e_write_memory().
Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe
Signed-off-by: Alexander Osipenko <sipych@gmail.com>
Reviewed-on: http://openocd.zylin.com/692
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
When testing a pic32mx220f032b with different values
for adapter_khz and cpu clocks i was getting a lot of
corrupted data from the chip. From time to time
openocd fails with segmentation faults or is aborted
due to memory corruption.
Change-Id: I134743f75c477b3d55dc74ae4474598e153b4a4a
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/690
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Do not call mips32_cp0_read() if not needed.
This will speed up execution of mips_m4k_write_memory()
by near 2x, with parameter count = 1.
Change-Id: I7829a7802b6475bc6d4ac3f0632d8d239d1072da
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/624
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Purely cosmetic but use the same style as Cortex-A target, this makes
searching refs easier.
Change-Id: I732ad9701f561e2312c5d191f5aaffd3a2f2393d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/731
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add missing arm cmd handlers that enable semi hosting support to work as
expected.
Change-Id: I063d82c48b82b4f6aed4efc4b08ea752d78e9047
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/734
Tested-by: jenkins
Reviewed-by: Alan Bowman <alan.michael.bowman@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The ADIv5 spec guarentees that tar_autoincr_block will be 10bits.
Make this the default for Cortex-M family until we detect a Cortex-M3/M4,
we then change autoincrement to 12bits.
Change-Id: Ie8c89134aa036879bdd8a3c312cee9715dbc6913
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/730
Tested-by: jenkins
Reviewed-by: simon qian <simonqian.openocd@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
jim_target_md is supposed to print out results with command_print in
hexdump format. It was using command_print which appends a newline character
aftre every invocation. Using command_print_sameline instead
Change-Id: Iaff03021acc38d54b5a082cb58b82aa4449c0715
Signed-off-by: Vandra Akos <axos88@gmail.com>
Reviewed-on: http://openocd.zylin.com/669
Tested-by: jenkins
Reviewed-by: Alexander Osipenko <sipych@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
- Added a few lines of comment before the function explaining the usage and the
output generated by the command
- Added a few lines of comment in the body explaining what is happening to improve
code readability
- Renamed a few variables to improve readability:
* a -> addr
* b -> dwidth
* c -> count
- Added a new variable, named byte to contain the number of bytes to read, instead
of overwriting the count parameter, to avoid confusion between the two values.
Change-Id: I5828ec0f5aadaa39becec7b84f198756bb2c3d41
Signed-off-by: Vandra Akos <axos88@gmail.com>
Reviewed-on: http://openocd.zylin.com/665
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Seems I5347352e7595686634bd0de13fcf6de6e55027b0 introduced an issue when
reading 8/16 bit data - the in buffer was always set to 32bits.
Change-Id: Ife2bb6a20fcb3ec0e486655512164f25ae9196b4
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/660
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
These events have been deprecated for a number of years, update any
remaining scripts to the new events.
Change-Id: Ic31ff388545ac8b3a500045699ca92c541b13f12
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/634
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
Reviewed-by: Bill Traynor <wmat@alphatroop.com>
this header is used in numerous files and adding to config.h
simplifies its use globally.
Change-Id: Id724a9950b90504721233022c7fb5768e9bc5548
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/649
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
This enables us to better handle some of the low level functions that the
stlink does not support. It also enables us to share a few more of the
standard cortex_m3 functions if necessary.
Change-Id: I7a2c57450122012ec189245d8879d8967913e00e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/637
Tested-by: jenkins
Some targets support connecting while the target's srst is asserted.
Tested on pic32 family.
Change-Id: I0d20c40af6d031d1306043893e95e61f484c0a87
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/608
Tested-by: jenkins
Some targets support connecting while the target's srst is asserted.
Tested on stm32 family.
Change-Id: I1197dd721a1e1cbf95ee77dfd8e1082b165b22a9
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/607
Tested-by: jenkins
Some targets support connecting while the target's srst is asserted.
Tested on stm32 family.
Change-Id: I9df43623025e37832155aeee7aa099b844b85f16
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/606
Tested-by: jenkins
This makes the code a bit easier to read as arm_algorithm can
refer to other arch's, not just armv4_5.
Change-Id: I78c99d40f34cda04e06f2daee75b48ff40a1d23d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/613
Tested-by: jenkins
Reviewed-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Use loaders that have been built for cortex-m0, making them usable for both
cortex-m0 and cortex-m3 families.
Change-Id: Ifd82be87eaec2cb96464290c80800cec3630d619
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/604
Tested-by: jenkins
This adds the ability to support srst reset for the stlink/v2.
stlink/v1 will fallback to using SYSRESETREQ which is a full reset - including peripherals.
To enable the use of the srst add the following to your cfg:
reset_config srst_only
Change-Id: I570de607c5f370fd6a4abf47360686c9be07bcdd
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/581
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add swd_init_reset and swd_add_reset.
Add adapter_assert_reset and adapter_deassert_reset, and call them instead
of JTAG reset functions.
Change-Id: Ib2551c6fbb45513e0ae0dc331cfe3ee3f922298a
Signed-off-by: Simon Qian <simonqian.openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/526
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This functions are unfinished and work only with parameter count up to 1024.
Commands mdh and mdb from pic32mx context show values not related to memory
content if parameter count is bigger than 1024. Firt 1024 are ok.
Change-Id: Ie3f4d4a0f9d1d1a69bd3a18de2f72dd9249514cb
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/550
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
Now the the "Fast" version for memory blank check in pic32mx.c can be called:
default_flash_blank_check() instead of the "fallback" default_flash_mem_blank_check().
The command "verify_image", without working area, now don't show:
checksum mismatch - attempting binary compare
when there are no real errors in flash.
Change-Id: I256e8ae949289634e1de5c1c2861e4c4c4b7fdce
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/549
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The stlink partially supports the cortex-m4 fp regs and requires these
defines to build.
Change-Id: Id3aa802ecc7006cb6d9f84b79ab3c21af24c1001
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/545
Tested-by: jenkins
This patch fix the register index on read/write register.
Change-Id: I7b52a927a48259d6f497ac0f474aff7ff1529e9a
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/525
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The bug shows up with the command "mdw addres count" and only if count>1024 (count>0x400).
The first 1024 values shows as expected, but the rest of the values are wrong.
Name of variable bytesread" is changed to "wordsread" to reflect what really does.
Change-Id: Iad79393e72da2637551c5ae6e829e3873605c520
Signed-off-by: Salvador <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/527
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The {read,write}_mem32 interface functions was asking a 32 bits buffer
but they don't need 32 bits alignment.
This will change the interface to a 8 bits buffer to remove the
alignment mismatch warning. This was causing build errors on platforms
with strict aliasing rules.
Change-Id: I338be8df5686f07a64ddb4f17c1bb494af583999
Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Reviewed-on: http://openocd.zylin.com/483
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch add floating point register read/write
functionality through the SCS debug interface.
Change-Id: Id20e109dd7cccba00671d55ca8aabeb4936cceb9
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/512
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch determine all cpu types and not only
the cortex M3 and the stm32 target use the common
target examine function from the cortex_m sources.
Change-Id: If689dd994b3855284b927fc4b206f420cf32b6c7
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/511
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
arm7_9_prepare_reset_halt is long since gone and the functionality
is implemented in the target's assert_reset handler.
Change-Id: Ib03c730cb39d68e5e3bb42f92af13daf8074e4e2
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/515
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
even the AT91EB40a's flash is covered by CFI and nobody ever submitted
any other drivers based on eCos code. It's just possible that this
idea was missing documentation and "marketing", but it's in git if
somebody wants to resurrect it.
Change-Id: I66449aa6e0997301f9d67f28098789bfc891d6e9
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/502
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
target_call_event_callbacks needs to be called after debug entry otherwise
we will get a console pc mismatch.
Change-Id: I278137736d5e85ca9662c306f6ac81336d8eb6cf
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/499
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Currently the stm32f1x flash driver uses an asynchronous algorithm
as part of the block flash programming. This greatly speeds up flash
programming as the target is always running.
Moving the async code to the target enable other targets to use this
added functionality.
Change-Id: I8e53f094c2ef7848a7f86ddb9a35b6edbfc8454a
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/402
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is a much cleaner solution to the problem of allocating as much
working area as possible than what is currently being done in most/all flash
drivers (which is: try an arbitrary sized chunk, if it fails, pick a smaller
number, rinse and repeat).
Use this function to find out how much working area is available, limit or
restrict that amount at will and then simply allocate it.
Change-Id: Ib7d5d0b7485aed3e0a4fad60c1bedb7dfd16146f
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/446
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The existing allocator couldn't reuse a freed allocation if the sizes
didn't match exactly. That led to problems when for example a flash write
routine had allocated all of the working area to speed up operation. A
subsequent verify pass couldn't allocate space for the checksum algorithm
even though all previous allocations had been freed.
This allocator is marginally more complex, but solves the above problem by
splitting larger free areas to fulfill smaller requests and by merging
released areas into adjacent free areas.
An initial free area, covering the entire specified address range, is set
up on first allocation, and all allocations are split off from (and
ultimately merged into) that one. It can also easily be adapted to support
several disjoint working areas for the same target, by setting up several
initial free areas and slightly modifying the merge code.
Change-Id: I6faaf9801312bb19a4fa4474694a0cd1c6e0ab54
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/445
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
automake 1.11.2 throws `pkglibdir' is not a legitimate directory for `DATA'
if nobase_dist_pkglib_DATA is used.
We work around this issue by defining our own location.
Change-Id: I3c29e2df0b67e745283c50d358e31699bd60dc74
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/457
Tested-by: jenkins
This adds init_board procedure that behaves exactly the same as
init_targets - it can be overriden by "next level" scripts. This
procedure is executed after init_targets, allowing common stuff (jtag
chain, memory, flash, ...) to be configured in target script (via
init_target) and leaving rest (like additional memory, reset
configuration, reset-init handlers, ...) to be done in init_board.
This makes init_targets scheme more complete and easier to use - current
board scripts will not need new init_targets, because everything can be
"packed" in init_boards. Moreover it solves the problem of variables
being set in init_targets (executed after init), which were not
accessible by "linear" scripts (parsed before init). All that has to be
done is to enclose all code in board config file in init_board
procedure.
Change-Id: I0736b1ff9873a687966407d62b58ccf29a8e597b
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/427
Reviewed-by: Chris Morgan <chmorgan@gmail.com>
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Replace the big stack-allocated buffer with a much bigger heap-allocated.
There was no explanation for the apparently arbitrary chunk size, and
performance was improved by increasing it, leveling out at about 4k.
Change-Id: I3b06d4469092ec8d89d0ce05bff0b7cf213c5062
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/404
Tested-by: jenkins
Reviewed-by: Marti Bolivar <mbolivar@leaflabs.com>
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This patch add jtag support to the stlink driver add
two new transport types, JTAG and SWIM.
Change-Id: I7089d74250330be5c6a01c24066307641df7d11e
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/393
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This makes the stlink target use the std armv7m_arch_state giving
consistent OpenOCD output.
Added debug entry handler so we get debug entry reason.
Change-Id: Ia3c1380fd5033a8e541b0d45a7c3559f1b05957d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/379
Tested-by: jenkins
Nothing more than a name change, just to make reading
the code a bit simpler.
Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/390
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This move will enable use to share with regmaps with the stlink target.
Change-Id: If8f41c7c53323d5074cb22ec3440530c1e402004
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/377
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
we should have caught them all - hopefully.
Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/381
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
On wrong parameters a error is signalized to the calling function.
Change-Id: I484443fdb39938e20382edc9246d5ec546a5c960
Signed-off-by: Mathias K <kesmtp@freenet.de>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/282
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
These error messages will prompt patches to be submitted for missing
.usage or empty fields. All of the below must be resolved before next
release.
The Jim defined commands are excluded from this checklist because the
help text can be set later than during command registration.
strlen(.usage) == 0 means that the command expects no arguments.
Updates to this patch in Gerrit to fix problems below are most
welcome. Anyone can push updated versions of a patch to Gerrit. If
there are no further updates to this patch within a week, it will be
pushed to the master branch to prompt more fixes.
These were caught by launching OpenOCD.
Error: BUG: command 'command' does not have the '.usage' field filled out
Error: BUG: command 'script' does not have the '.usage' field filled out
Error: BUG: command 'power_restore' does not have the '.usage' field filled out
Error: BUG: command 'srst_deasserted' does not have the '.usage' field filled out
Error: BUG: command 'measure_clk' does not have the '.usage' field filled out
Error: BUG: command 'exit' does not have the '.usage' field filled out
Error: BUG: command 'shutdown' does not have the '.usage' field filled out
Error: BUG: command 'gdb_sync' does not have the '.usage' field filled out
Error: BUG: command 'interface_list' does not have the '.usage' field filled out
Error: BUG: command 'target' does not have the '.usage' field filled out
Error: BUG: command 'target init' does not have the '.usage' field filled out
Error: BUG: command 'flash' does not have the '.usage' field filled out
Error: BUG: command 'flash init' does not have the '.usage' field filled out
Error: BUG: command 'flash banks' does not have the '.usage' field filled out
Error: BUG: command 'nand' does not have the '.usage' field filled out
Error: BUG: command 'nand drivers' does not have the '.usage' field filled out
Error: BUG: command 'nand init' does not have the '.usage' field filled out
Error: BUG: command 'pld' does not have the '.usage' field filled out
Error: BUG: command 'pld init' does not have the '.usage' field filled out
Error: BUG: command 'mflash' does not have the '.usage' field filled out
Error: BUG: command 'mflash init' does not have the '.usage' field filled out
Error: BUG: command 'dummy' does not have the '.usage' field filled out
Error: BUG: command 'dummy foo' does not have the '.usage' field filled out
Error: BUG: command 'scan_chain' does not have the '.usage' field filled out
Error: BUG: command 'jtag' does not have the '.usage' field filled out
Error: BUG: command 'jtag init' does not have the '.usage' field filled out
Error: BUG: command 'arm' does not have the '.usage' field filled out
Error: BUG: command 'arm reg' does not have the '.usage' field filled out
Error: BUG: command 'etm' does not have the '.usage' field filled out
Error: BUG: command 'arm7_9' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu arm' does not have the '.usage' field filled out
Error: BUG: command 'arm reg' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu etm' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu arm7_9' does not have the '.usage' field filled out
Error: BUG: command 'target_request' does not have the '.usage' field filled out
^C
oyvind@fierce:~/openocd$ openocd -c "interface dummy" -f board/at91eb40a.cfg 2>&1 | grep -w BUG
Error: BUG: command 'command' does not have the '.usage' field filled out
Error: BUG: command 'script' does not have the '.usage' field filled out
Error: BUG: command 'power_restore' does not have the '.usage' field filled out
Error: BUG: command 'srst_deasserted' does not have the '.usage' field filled out
Error: BUG: command 'measure_clk' does not have the '.usage' field filled out
Error: BUG: command 'exit' does not have the '.usage' field filled out
Error: BUG: command 'shutdown' does not have the '.usage' field filled out
Error: BUG: command 'gdb_sync' does not have the '.usage' field filled out
Error: BUG: command 'interface_list' does not have the '.usage' field filled out
Error: BUG: command 'target' does not have the '.usage' field filled out
Error: BUG: command 'target init' does not have the '.usage' field filled out
Error: BUG: command 'flash' does not have the '.usage' field filled out
Error: BUG: command 'flash init' does not have the '.usage' field filled out
Error: BUG: command 'flash banks' does not have the '.usage' field filled out
Error: BUG: command 'nand' does not have the '.usage' field filled out
Error: BUG: command 'nand drivers' does not have the '.usage' field filled out
Error: BUG: command 'nand init' does not have the '.usage' field filled out
Error: BUG: command 'pld' does not have the '.usage' field filled out
Error: BUG: command 'pld init' does not have the '.usage' field filled out
Error: BUG: command 'mflash' does not have the '.usage' field filled out
Error: BUG: command 'mflash init' does not have the '.usage' field filled out
Error: BUG: command 'dummy' does not have the '.usage' field filled out
Error: BUG: command 'dummy foo' does not have the '.usage' field filled out
Error: BUG: command 'scan_chain' does not have the '.usage' field filled out
Error: BUG: command 'jtag' does not have the '.usage' field filled out
Error: BUG: command 'jtag init' does not have the '.usage' field filled out
Error: BUG: command 'arm' does not have the '.usage' field filled out
Error: BUG: command 'arm reg' does not have the '.usage' field filled out
Error: BUG: command 'etm' does not have the '.usage' field filled out
Error: BUG: command 'arm7_9' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu arm' does not have the '.usage' field filled out
Error: BUG: command 'arm reg' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu etm' does not have the '.usage' field filled out
Error: BUG: command 'at91eb40a.cpu arm7_9' does not have the '.usage' field filled out
Error: BUG: command 'target_request' does not have the '.usage' field filled out
Change-Id: I2c3e529530a15d2295a1950ffc59e8f2fc661012
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/299
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Change this functions to make it accessible for other
target implementations.
Change-Id: Ib41fc793cfb4de5439af026c2e8b52e7a9507c85
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/278
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
this particular edge case of the JTAG API will no
longer be supported.
the in_value buffer must be provided by the caller when
the callback needs the buffer.
Change-Id: I552c72a64af6875f4aa4fa9b923194dcf3b57b64
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/265
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
not needed, reduce area of interface and sharp edges to
API.
Change-Id: I5347352e7595686634bd0de13fcf6de6e55027b0
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/262
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add a test if the pointer to the target_init function in the target struct
is set before the function pointer is used.
Change-Id: Ie4ea542f64f35efce8c5bce2ced9b881bf283ec1
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/241
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
the flash module clock was set according to a spreadsheet from freescale, now it's set according to the configuration file used by the Freescale Flash Programmer.
both work, but i think it's better to use the one used by a software that's made by Freescale (should be correct...)
Change-Id: I382197a3eb43dd47ff4b9b83d5e05008d5613fc6
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/223
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
the unlocking procedure erases the flash mem (even if it wasn't locked), so it should be marked as erased after unlocking.
Change-Id: I5cc6a1e1d6cf4e1f243de532eff54111ffd66187
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/222
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
if JTAG debug request fails then halting with a reset should be attempted.
the failure was ignored previously.
Change-Id: Ibec08e2e97f962d164a110c21aaa80bfc17b7f1a
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/221
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
i had assumed two possible halt/debug states:
- halted + debug mode
- running + not debug mode
turns out this one also exists
- halted + NOT in debug mode
added code to handle this in an appropiate way.
Change-Id: Ia0ddcd55d1890c90d100a9e6f5e84ed8dda812a3
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/220
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
now the flash algorithm running on the 568013 checks the buffer_empty bit (instead of the command_finished bit) before trying to write a new word to the flash mem.
this should speed up the flashing procedure. since it is open loop, this change may reduce the risk of failure. flashing will fail if JTAG speed is such that the flash module cannot keep up.
also, the USTAT register is only read once, as suggested in the flow chart provided by freescale (per. ref. manual @ 6-11)
the last step of the flow chart, exiting after commands are complete, is not implemented.
the algorithm will stay waiting for more data. it is up to the PC side to *not* send more data.
Change-Id: I47fe4b50de7da85f80868f5986a89a7e2152616c
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/219
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
moved reset_jtag to the top, since it will be needed in future changes.
also send a define to the .h
Change-Id: I53ef9c02ffa70e7d0416364525a6fbfef855e222
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/216
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
added logging of target error codes to enable automatic error handling from tcl.
the plan is to use a computer to execute a series of tcl commands, the changes allow simple parsing of return messages to detect errors.
Change-Id: Ia98d3bd036e1b6065b475ffff6c1d30baeaf7417
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/215
Tested-by: jenkins
Tested-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This fixes an issue when init is called before init_targets has been
executed.
Make sure init_targets is called before init.
Change-Id: Icd5bd4c2a8eea2e399d9de4e331a77560e9672ac
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/235
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
there are no comments about what the rules w.r.t. null pointers
are and it is inconsistent.
It's simply a bug in the app if we ask about the properties of a null
pointer w.r.t. what kind of target it is. It's equally wrong to say
that it is an arm target as that it isn't an arm target.
Change-Id: I0925a6a5c8b38e594ffa7c3ca4390487b5e9b718
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/168
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
fixes clang warning. Basically the next address pointer is not
used for anything in the fn, except to be examined in debug.
Change-Id: I253519b8e49e54490bbe7da8ec3d2dd31f49052a
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/155
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
check if no target is selected and return error.
Change-Id: Ie8abb63c708d09572b45e88fc6766af108715077
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/148
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This rename is in preparation for cortex_m4 support.
Change-Id: Ic08c298ec6ed2aabc2c39db67191f68b3a51f550
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/147
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
return error when target can not be found instead of ERROR_OK,
split fn.
Change-Id: Iba5232d3862a490d0995c3bfece23685bd6856e3
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/131
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
this was a false positive, silence it.
Change-Id: I432e0c466c94cf8fd6bbf0ea153c8501a8a261eb
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/126
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
"Value stored to 'retval' is never read": Check and propagate error
"Dereference of null pointer": Probably bogus, maybe triggered by the null
check on armv7a, so remove the check since it can't be null anyway.
Change-Id: I3bc44e52af1589ff40e6a42deda0ce7f3a25e397
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/119
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Also fix a spelling error and remove the declaration for a non-existent
function from the header.
Change-Id: I13177e2d81aa167c05c1cc766f06924211e6d735
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/118
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Propagate errors unchanged.
Free allocated working area in the error return path.
Remove duplicated cleanup code by rewriting the logic.
As a side-effect, fixes a scan-build warning.
Change-Id: I80e3c0015be672778f916e998c8c2e4f23d7588c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/117
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
GCC doesn't understand that these are in fact initialized if they are
used.
Change-Id: I01988adb0547f785b48d869ddbe44cc17dca4739
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/116
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Fix a few errors with set and unused variables detected by GCC 4.7.0
Change-Id: I59b748e18e514ee9f0cde7883b4ed5116198bd4a
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/36
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The code in xscale_receive() that tries to skip invalid reads (i.e.
reads that don't have the DBG_SR[0] 'valid' bit set) seems to be
wrong, as it only looks at the first word's valid flag rather than
each word's own valid flag. Am I reading the code correctly? If so,
the attached patch should fix it.
If this looks correct, I'll generate a proper patch and commit message.
Matt
Change-Id: I74ebe2ad7a36d340a9dd3b8487578b6ea7f3cf1e
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/32
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Change-Id: I1453f4f3dc0add529da20577e38b8b82d7d00366
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Reviewed-on: http://openocd.zylin.com/18
Reviewed-by: Alex Austin <alex.austin@spectrumdsi.com>
Tested-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Split armv7m_run_algorithm into two pieces and use them to reimplement it.
The arch_info parameter is used to keep context between the two calls, so
both calls must refer to the same armv7m_algorithm struct. Ugly but works
for a proof-of-concept.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
On supported targets, this may be used to start a long running algorithm in
the background so the target may be interacted with during execution and
later wait for its completion.
The most obvious use case is a double buffered flash algorithm that can
upload the next block of data while the algorithm is flashing the current.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Target events are added to get better gdb support. The run
algorithm functionality are implemented to support feature
fast flash write functionality. The new r/w buffer api is now
used to support the special memory address handling. The output
of the md command was fixed.
This is a proof of concept to get access to the debug port of a
secured kinetis cpu. On full flash erase the cpu is automatically
secured and the debug port is not accessible.
To get this to work the srst line is needed and the necessary
configuration should be added to the configuration file.
added an attempt to use the non-reseting halting sequence. if it fails, then the full sequence will be attempted. this makes things a bit faster most of the time.
changed the location of a function, avoiding a forward def
added an alternative way to enter debug mode, which does not require restarting the chip.
this will not always work, but in general it will (failure 0.3%), and failure is not a dramatic issue, simply have to use the full sequence.
the user can only access "halt", which uses the full sequence, so the user should not have any problems.
restarting the chip requires reconfiguring the flash module. the doc is very poor, so i'd rather have the two methods, and live with the 0.3%.
sometimes the master tap will be enabled, since tap switching is required during halt/lock/unlocking procedures.
now irscan handles this, avoiding unnecessary warnings and preventing errors.
got new info regarding setting the chip to debug mode, and locking/unlocking flash memory.
the newer implementation is a bit slower, but always works.
the previous implementation would randomly (as once every 25k-70k times) get the chip into a state where the freescale tool would be necessary. this is fixed now.
added functions to play around with the jtag state machine. they are not the happiest, but are necessary to be able to execute the halting/locking/unlocking sequences.
Conflicts:
src/target/dsp5680xx.c
the user can execute halt, but no enter_debug_mode. modified the error handling to suite this.
the new implementation of unlocking will use enter_debug_mode, and should not get the same errors as the user would, because not being able to enter debug mode is actually success when checking for locked flash.
crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
i had started my code from dsp5683xx, i renamed a bunch of stuff to names i consider to be better.
i believe no one is using this code, so nobody should be affected. (it's not too late to do this change)
Function mips_m4k_write_memory() does endianess byte swap,
but this procedure break one byte access (temporary array
overwrites content in buffer).
As a fix, this endianess swap and buffer affecting
is preformed only on hword and word accesses (not on byte access).
Pprogram that loads another program into memory is actually writing the
D- side cache.
The instructions it has loaded can't be executed until they reach the
I-cache.
After the instructions have been written, the loader should arrange to
write back any containing D-cache line and invalidate any locations
already in the I-cache.
For the MIPS Architecture Release2 cores, we can use synci command
that does this job.
For Release1 we must use "cache" instruction.
This patch adds MIPS32 CP0 coprocessor R/W routines,
as well as adequate commands to use these routines via
telnet interface.
Now is becomes possible to affect CP0 internal registers
and configure CPU directly from OpenOCD.
For all architectures we use distinct common magic number,
and this should be a uint32_t type.
Otherwise, comparison with macros will yield compilation
warning.
before doing anything with the flash module (FM) the clock divider must be set.
if erase_check was the first thing done with the FM after reset then an error would be generated because the clk divider was not set.
now erase_check sets the clk divider.
reorganized code to get rid of compiler warnings
the warning were related to allignment, i do not get these warning on my build system (i've tried setting the compiler flag but it doesn't work, still working on why) so i cannot detect them (yet.)
This corrects two issues found with openocd.
d7f71e7fe9 removed some code that was
being used.
The above then caused even more code to get removed by commit 1cfb2287a6.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
This patch extends the cortex_m3 maskisr command by a new option 'auto'.
The 'auto' option handles interrupts during stepping in a way they are
processed but don't disturb the program flow during debugging.
Before one had to choose to either enable or disable interrupts. The former
steps into interrupt handlers when they trigger. This disturbs the flow during
debugging, making it hard to follow some piece of code when interrupts occur
often.
When interrupts are disabled, the flow isn't disturbed but code relying on
interrupt handlers to be processed will stop working. For example a delay
function counting the number of timer interrupts will never complete, RTOS
task switching will not occur and output I/O queues of interrupt driven
I/O will stall or overflow.
Using the 'maskisr' command also typically requires gdb hooks to be supplied
by the user to switch interrupts off during the step and to enable them again
afterward.
The new 'auto' option of the 'maskisr' command solves the above problems. When
set, the step command allows pending interrupt handlers to be executed before
the step, then the step is taken with interrupts disabled and finally interrupts
are enabled again. This way interrupt processing stays in the background without
disturbing the flow of debugging. No gdb hooks are required. The 'auto'
option is the default, since it's believed that handling interrupts in this
way is suitable for most users.
The principle used for interrupt handling could probably be used for other
targets too.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
In order to compare data read from the target with some marcros or data
defined on the host, we must transform this read data from target
endianess to host endianess.
target_read_memory() gets bytes from target to the host, but keeps them in _target_
endianess. This is OK if we just want to temporary keep this data on the
host, like keeping breakpoint->orig_instr. But if we want to use this
data for any ispections and comparisons on the host side, we must
transform it to _host_ endianess, by using target_buffer_get_u32()
function.
Currently this transformation is missing, and check current_instr ==
MIPS32_SDBBP will never pass if target and host endianess differ,
because current_instr will be kept in _target_ endianess and
MIPS32_SDBBP will be kept in _host_ endianess,
The patch fix this issue by using target_buffer_get_u32() to transform current_instr to
_host_ endianess before comparison.
Use "git revert <commit>" to revert this commit, then build and
repair and post patch to the mailing list.
Warnings generated with:
nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222)
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data':
openocd/src/target/dsp5680xx.c:252: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data':
openocd/src/target/dsp5680xx.c:268: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store':
openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned
pointer will break strict-aliasing rules
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read':
openocd/src/target/dsp5680xx.c:736: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:737: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8':
openocd/src/target/dsp5680xx.c:823: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write':
openocd/src/target/dsp5680xx.c:938: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:941: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr':
openocd/src/target/dsp5680xx.c:1355: warning: cast increases required
alignment of target type
This patch extends the cortex_m3 maskisr command by a new option 'auto'.
The 'auto' option handles interrupts during stepping in a way they are
processed but don't disturb the program flow during debugging.
Before one had to choose to either enable or disable interrupts. The former
steps into interrupt handlers when they trigger. This disturbs the flow during
debugging, making it hard to follow some piece of code when interrupts occur
often.
When interrupts are disabled, the flow isn't disturbed but code relying on
interrupt handlers to be processed will stop working. For example a delay
function counting the number of timer interrupts will never complete, RTOS
task switching will not occur and output I/O queues of interrupt driven
I/O will stall or overflow.
Using the 'maskisr' command also typically requires gdb hooks to be supplied
by the user to switch interrupts off during the step and to enable them again
afterward.
The new 'auto' option of the 'maskisr' command solves the above problems. When
set, the step command allows pending interrupt handlers to be executed before
the step, then the step is taken with interrupts disabled and finally interrupts
are enabled again. This way interrupt processing stays in the background without
disturbing the flow of debugging. No gdb hooks are required. The 'auto'
option is the default, since it's believed that handling interrupts in this
way is suitable for most users.
The principle used for interrupt handling could probably be used for other
targets too.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
So far image_load command tries to load ELF binaries to address
discovered by reading p_paddr member of a Program header of an ELF
segment.
However, ELF specifications says for p_paddr : ...Because System V
ignores physical addressing for application programs, this member has
unspecified contents for executable files and shared objects.
ARM ELF specifiaction goes even further, demanding that this member
be set to zero, using the p_vaddr as a segment load address.
To avoid the cases to wrong addr where p_paddr is zero,
we are now using p_vaddr to as a load destination in case that *all*
p_paddr == 0. Basically, this patch re-implements the approach present in
BDF's elf.c, which is used by GDB also (so that we can be consistent).
cygwin does not define sleep, so use our internal win32 version.
caused by commit 9d4aec6bda
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
- works on Cortex-M3 with ThreadX and FreeRTOS
Compared to original patch a few nits were fixed:
- remove stricmp usage
- unsigned compare fix
- printf formatting fixes
- fixed a bug with overrunning a memory buffer allocated with malloc.
Freescale iMX53 doesn't seem to like unaligned accesses to his memory
mapped registers.
Anyway this patch makes dump_image/load_image 4X faster for every
access through APB.
Signed-off-by: Luca Ellero <lroluk@gmail.com>
accidentally invoked return jtag_execute_queue() in the
middle of a fn. Hmm.... I would have expected gcc or
at least lint to catch this.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
the patchup code would get false positives when checking
whether a dbgbase had to be corrected.
The solution is to have autodetect default, with manual override
in scripts.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Could this cause confusion as data sent to write would be flipped
and then if the caller subsequently used the data, e.g. a
compare mismatch might happen?
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Really a Cortex-A specific option, but there is no
system in place to support target specific options
currently and there has been no need for such a system
until now.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
The patch below fixes step <address> on mips_m4k.
Spencer Oliver <spen@spen-soft.co.uk>:
The current code is used on all other arch's - is
there a underlying issue with those aswell ?
I don't think dsp563xx_once_read_register() would ever
be called with len==0, but it would have been broken in
that case.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Problem is, trying to print "Hello, world!\n" just prints endless H's, because r1 is never incremented.
One way to fix it would be to add a "++" after "r1".
Fix a bunch of typos.
Most are in code comments, so nothing should break. UNKOWN_COMMAND and
CMD_UNKOWN are not used elsewhere, so correcting the spelling should
also not break anything.
This patch add rudimentary gdb support. The gdb register list
order is corrected. All registers are now 32bit width. Events are
send to signalize gdb the current target status. Resume and step
function was corrected to consider a modified pc register. Read/write
memory now support L memory type, this means a memory with alternating
y/x memory words. The memspace variable, used by gdb, is now observed
before a default memory access is initiated. Dummy functions for breakpoint
and watchpoint are added.
This patch tries to make some order in "apsel" mess.
"dap apsel" command was quite useless (and broken) by itself.
With this patch we can use it to select between AHB or APB memory access
(previous patch 05ab8bdb81 was somehow broken).
- moves member apsel (in struct adiv5_dap) to ap_current
- adds apsel member
this strange choice is made trying to keep coherence in "dap apsel" command
and to keep compatibility with other code (for example cortex_a8).
Signed-off-by: Luca Ellero <lroluk@gmail.com>
This patch move the dsp563xx_target_create function to the
related code block. Also the target examine function was added
and the register cache is initialized in a separate function. The
missing functionality to invalidate the x memory context on memory
writes was also added.
This patch change the return value on a jtag communication error
to TARGET_UNKNOWN because this function should return the current
target status and not a error code from the underlying api call.
Also the validity of the jtag_status is extended to all static
bits in this value.
I've been working on Rodrigo on adding support to flash
Freescale dsp56800e devices and have been looking at the
dsp563xx code. I think the define for the JTAG CLAMP
instruction in dsp563xx_once.c is incorrect. It should
be 0x05 according the Freescale AN2074 (and is also
0x05 in the dsp568xx according to AN1935). It won't
actually change anything in OpenOCD since this define
is not used anywhere (as far as I can tell).
dap_ap_select was used in the code at various points, but that can lead to
confusion, without any knowledge of what AP is really selected at some
points.
Some bugs derive from this (for example md/mw doesn't work well after
issueing "dap apsel" command).
Moving it to arm_adi_v5.c (using mem_ap_sel* functions instead of mem_ap_*)
make the code more clear and more easier to maintain.
In the future it should be made "static" to avoid its use outside arm_adi_v5
One further benefit is the various goto has been removed as well
Signed-off-by: Luca Ellero <lroluk@gmail.com>
This patch adds read/write capability to memory addresses not
accessible through AHB-AP (for example "boot ROM code").
To select AHB or APB, a "dap apsel" command must be issued:
dap apsel 0 -> following memory accesses are through AHB
dap apsel 1 -> following memory accesses are through APB
NOTE: at the moment APB memory accesses are very slow, compared
to AHB accesses. Work has to be done to get it faster (for
example LDR/STR instead od LDRB/STRB)
Signed-off-by: Luca Ellero <lroluk@gmail.com>
Save, select and restore AP in cortex_a9_step and cortex_a9_init_debug_access.
Fixes a bug where the wrong AP is selected after a reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
Hello,
this patch add commands to access to x,y and p memory. For run time optimization some local jtag
function was changed to static inline.
Regards,
Mathias
Hello,
this patch adds the missing cpu registers and the correct read/write register functions and fixed
most of the halt/step/resume issues. The complete missing error propagation was added.
+ fix tab/spaces
Regards,
Mathias
If a handler for the reset-assert event it present, skip the usual reset
handling. This is needed, for example, for board-level resets.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
ARM Cortex-A9 multi-core chips expose a single TAP/DAP which connects
to both cores. The '-coreid' option selects which core the target
should connect to.
Note that at present, OpenOCD can connect to either core, but not both
simulatenously, until ADI contexts can be shared.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
ahbap_debugport_init was queueing reads to a local stack variable but
didn't execute the queue before returning. Since the result of the reads
are not used anyway, it's better to pass NULL as the destination instead of
a dummy variable. I changed this throughout the function, even for the
reads that were actually executed.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages
Remove LOG_INFO_N
LOG_INFO_N was only used once and had a \n at the end
Change LOG_USER_N calls that end with \n to LOG_USER
Add a working area that is preserved between calls to
mips_m4k_bulk_write_memory - this gives us a speed increase
of approx 3kb/sec during flash writes to the pic32mx.
This area is released during a resume/reset.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
We only use the struct working_area member 'free' as a
true/false type so might as well use a bool data type.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Do not propagate error number to user. This is for internal
programming purposes only. Error messages to the user is
reported as text via LOG_ERROR().
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This patch fixes the issue where the OMAP CPU (and possibly others) was mistaken
for iMX51 and therefore had misadjusted debug base.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
I received a number of "-Wshadow" related warnings (treated as errors) while
trying to build on OS X Leopard. In addition, there were two miscellaneous
other warnings in the flash drivers. Attached are two patches which correct
these issues and the commit messages to accompany them.
My system has the following configuration (taken from uname -a):
Darwin 9.8.0 Darwin Kernel Version 9.8.0: Wed Jul 15 16:55:01 PDT 2009;
root:xnu-1228.15.4~1/RELEASE_I386 i386
=== Werror_patch.txt Commit Message ===
compilation: fixes for -Wshadow warnings on OS X
These changes fix -Wshadow compilation warnings on OS X 10.5.8
Compiled with the following configure command:
../configure --prefix=/usr/local --enable-maintainer-mode --enable-jlink
--enable-ft2232_libftdi
=== flash_patch.txt Commit Message ===
compilation: fixes for flash driver warnings on OS X
These changes fix two compilation warnings on OS X 10.5.8:
../../../../src/flash/nor/at91sam3.c:2767: warning: redundant redeclaration
of 'at91sam3_flash'
../../../../src/flash/nor/at91sam3.c:101: warning: previous declaration of
'at91sam3_flash' was here
and
../../../../src/flash/nor/stmsmi.c:205: warning: format not a string literal
and no format arguments
Compiled with the following configure command:
../configure --prefix=/usr/local --enable-maintainer-mode --enable-jlink
--enable-ft2232_libftdi
===
Andrew
error numbers are only reported at DEBUG log levels and
used internally, they are not part of the user interface.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This piggy backs on JTAG so it's not yet pretty, but that
seems unavoidable so far given today's OpenOCD internals.
SWD init and data transfer are unfinished and untested, but
that should cause no regressions, and will be addressed by
the time drivers start using this infrastructure. Checking
in whould get the code working better sooner, and turn up any
structural/architectural issues while they're easier to fix.
The debug adapter drivers will provide simple SWD driver
structs with methods that kick in as needed (instead of JTAG).
So far just one adapter driver has been updated (not yet
ready to use or circulate).
The biggest issues are probably
- fault handling, where the ARM Debug Interface V5 pipelining
needs work in both JTAG and SWD modes and
- missing rewrite of block I/O code to work on both of our
Cortex-ready transports (Current code is hard-wired to JTAG);
relates also to the pipelining issue.
- omitted support to activate/deactivate SWO/SWV trace (this is
technically trivial, but configuring what to trace is NOT.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
----
doc/openocd.texi | 17 ++
src/jtag/core.c | 3
src/jtag/interface.h | 4
src/jtag/jtag.h | 2
src/jtag/swd.h | 114 +++++++++++++++++++
src/jtag/tcl.c | 2
src/target/adi_v5_swd.c | 281 ++++++++++++++++++++++++++++++++++++++++++++++--
src/target/arm_adi_v5.c | 8 +
src/target/arm_adi_v5.h | 3
9 files changed, 425 insertions(+), 9 deletions(-)
this allows configuration scripts to export a init_targets proc
rather than setting up the target directly.
This allows for new conventions in how to set up target vs. board
script and how to transfer default settings between board and
target scripts.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
Since a call went out for patches... been sitting on this for months. For some
reason, the xscale trace buffer is automatically disabled as soon as a break
occurs and the trace data is collected. This patch was a result of the
frustration of always re-enabling it, or else hitting a breakpoint and checking
the trace data, only to discover that I forgot to re-enable it before resuming.
Don't see why it should work this way. There is no run-time penalty, AFAIK.
Along the way, I also cleaned up a little by removing the ugly practice of
recording wrap mode by setting the fill count variable to "-1", replacing it
with an enum that records the trace mode.
I've been using this for months. Comments, criticisms gratefully received.
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Currently the cmd 'cortex_m3 reset_config' will overide the default
target's 'reset_config'.
Chnage the behaviour to use the target 'reset_config' if configured and
fallback if not.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
it's a lie that is somewhere in the vicinity of the
truth. Certainly 64MHz confuses gprof and produces
zero output and no error messages.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
If the CPU crashed at some point, poll will discover this.
Previously the poll fn would clear the error and print a warning,
rather than propagating the error.
The new behavior is to report the error back up, but still
clear the error.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Implement autodetection of debug base. Also, implement a function solving
various hardware quirks (like iMX51 ROM Table location bug).
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This patch implements "dap_lookup_cs_component()", which allows to lookup CS
component by it's identification.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This patch adds function called "dap_detect_debug_base()", which should be
called to get location of the ROM Table. By walking ROM Table, it's possible to
discover the location of DAP.
Sadly, some CPUs misreport this value, therefore I had to introduce an fixup
table, which will be used in case such CPU is detected.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
So far most of the people have been using existing ARM966E in the
place of ARM946E, because they have practically the same scan chains.
However, ARM946E has caches, which further complicates JATG handling
via scan-chain. this was preventing single-stepping for ARM946E when
SW breakpoints are used.
This patch thus introduces :
1) Correct cache handling on memory write
2) Possibility to flush whole cache and turn it off during debug, or
just to flush affected lines (faster and better)
3) Correct SW breakpoint handling and correct single-stepping
4) Corrects the bug on CP15 read and write, so CP15 values
are now correctly R/W
Collect variable definitions.
Report syntax error to command dispatcher.
Propagate error when unable to open file.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
short story: if the JTAG clock is too high, then the
behavior will be flaky and kludging the code may
seem to make things beter, but really it's just a red
herring.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
A while back I sent in a patch that adds support for watchpoint lengths greater
than four on xscale. It's been working well, until the other day, when it
caused an unexpected debug exception. Looking into this I realized there is a
case where it breaks: when the length arg is greater than the base address.
This is a consequence of the way the hardware works. Don't see a work-around,
so I added code to xscale_add_watchpoint() to check for and disallow this
combination.
Some more detail... xscale watchpoint hardware does not support a length
directly. Instead, a mask value can be specified (not to be confused with the
optional mask arg to the wp command, which xscale does not support). Any bits
set in the mask are ignored when the watchpoint hardware compares the access
address to the watchpoint address. So as long as the length is a power of two,
setting the mask to length-1 effectively specifies the length. Or so I thought,
until I realized that if the length exceeds the base address, *all* bits of the
base address are ignored by the comaparator, and the watchpoint range
effectively becomes 0 .. length.
Questions, comments, criticisms gratefully received.
Thanks,
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Hi everyone,
Added more LOG_ERROR messsages to watchpoint and breakpoint code, given that the
infrastructure no longer interprets returned error codes. Also changed
existing LOG_INFO and LOG_WARNING to LOG_ERROR for cases where an error is
returned.
Note that the check of the target state is superflous, since the infrastruture
code currently checks this before calling target code. Is this being
reconsidered as well? Also, should we stop returning anything other than
ERROR_OK and ERROR_FAIL?
Comments gratefully received.
Thanks,
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
do not try to interpret "retval" into a string, just
amend a bit about the context of the already reported
error.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
Version 2 of this patch. Code added to breakpoints.c was removed from previous
patch, and item 3 added, per discussion with Øyvind regarding error reporting.
Item 4 added, which I just noticed.
I tried to use a software breakpoint in thumb code on the xscale for the first
time recently, and was surprised to find that it didn't work. The result was
this patch, which does four things:
1): fix trivial cut-n-paste error that caused thumb breakpoints to not work
2): call xscale_set_breakpoint() from xscale_add_breakpoint()
3): log error on data abort in xscale_write_memory()
4): fixed incorrect error code returned by xscale_set_breakpoint() when no
breakpoint register is available; added comment
Item 2 not only makes the xscale breakpoint code consistent with other targets,
but also alerts the user immediately if an error occurs when writing the
breakpoint instruction to target memory (previously, xscale_set_breakpoint() was
not called until execution resumed). Also, calling xscale_breakpoint_set() as
part of the call chain starting with handle_bp_command() and propagating the
return status back up the chain avoids the situation where OpenOCD "thinks" the
breakpoint is set when in reality an error ocurred.
Item 3 provides a helpful message for a common reason for failure to set sw
breakpoint.
This was thoroughly tested, mindful of the fact that breakpoint management is
somewhat dicey during single-stepping.
Comments and criticisms of course gratefully received.
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
I figured since I was poking around in the breakpoint code on other arches, I'd
add this change to those arches that don't do it already. This patch propagates
the return code of <arch>_set_breakpoint() up the call stack. This ensures that
the higher layer breakpoint infrastructure is aware that an error ocurred, in
which case the breakpoint is not recorded.
Normally I wouldn't touch code that I can't test, but the code is very
uniform across architectures, and the change is rather benign, so I figured
after careful inspection that it is safe. If the maintainers or others think
this is imprudent, the patch can be dropped.
Also changed the error code to something more appropriate in two cases where
hardware resources are unavailable.
Comments and criticisms of course gratefully received.
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
This simple patch fixes a problem I noticed on the xscale where incorrect values
are sometimes reported by the reg command. The problem can occur when
requesting the value of registers in the xscale-specific register cache. With a
couple of exceptions, none of the registers in the xscale register cache are
automatically retrieved on debug entry. This is probably fine, as they are
unlikely to be needed on a regular basis during a typical debug session, and
they can be retrieved when explicitly requested by name using the reg command.
The problem is that once this is done, the register remains marked as valid for
the remainder of the OpenOCD session, and the reg command will henceforth always
report the same value because it is obtained from the cache and is never again
retrieved from the debug handler on the target.
The fix is to mark all registers in the xscale register cache as invalid on
debug entry (before the two exceptions are retrieved), thus forcing retrieval
(when requested) from the target across resumptions in execution, and avoiding
the reporting of stale values.
Small addition change by Øyvind: change 'i' to unsigned to fix compiler
warning for xscale_debug_entry() fn.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This new cmd adds the ability to choose the Cortex-M3
reset method used.
It defaults to using SRST for reset if available otherwise
it falls back to using NVIC VECTRESET. This is known to work
on all cores.
Move any luminary specific reset handling to the stellaris cfg file.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
committed so as to ease cooperation and to let it be improved
over time.
So far it supports:
- halt/resume
- registers inspection
- memory inspection/modification
I'm still getting up to speed with OpenOCD internals and AVR32 so code is a little
bit messy and I'd appreciate any feedback.
ocd_ prefix is used internally in OpenOCD as a kludge more
or less to deal with the two kinds of commands that OpenOCD
has.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
if polling is off, then "reset run + halt" would fail
since halt incorrectly assumed the target was in the
reset state as it is the internal poll implementation
that moves the sw tracking of the target state out
of the reset state.
To reproduce:
> reset run; halt
JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
back-off algorithm for polling. Double polling
interval up to 5000ms when it fails.
when polling succeeds, reset backoff.
This avoids flooding logs(as much) when working
with conditions where the target polling will fail.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
It is useful to know that the printed errors are *all* the
errors there were.
Added missing error handling(found by inspection).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
As the mips32 uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm codebase.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
As the armv7m uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm4_5 codebase.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Update the arm_checksum_memory and arm_blank_check_memory
algorithms to use a breakpoint instruction on v5 arch.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Paul Fertser
Luca BRUNO
Andreas Fritiofson
Spencer Oliver
Hsiangkai Wang
Franck Jullien
Per Ekman
Sergio Chico
Dongxue Zhang
Mathias K
Sergey A. Borshch
Andrey Yurovsky
Oleksij Rempel
Oleksij Rempel
Bernhard Kiesbauer
Robert Jarzmik
Brent Roman
Jim Norris
Brandon Warhurst
Salvador Arroyo
Michel JAOUEN
Evan Hunter
mike brown
Kamal Dasu
Jason Moehlman
Karl Kurbjun
Peter Horn
Matthias Blaicher
Martin Nowak
Alexander Osipenko
Vandra Akos
Simon Qian
Alexandre Pereira da Silva
Drasko DRASKOVIC
Øyvind Harboe
Freddie Chopin
rodrigo_l_rosa
Matt Reimer
Spencer Oliver
Heythem Bouhaja
Jie Zhang
Stefan Mahr
Jie Zhang
Freddie Chopin
Luca Ellero
Andrew Lyon
John and Tina Peterson
Uwe Hermann
Phil Fong
Aaron Carroll
Eric Wetzel
Marek Vasut
Andrew MacIsaac
David Brownell
Mike Dunn
ddraskovic
Peter Stuge
Antonio Borneo
Oleksandr Tymoshenko