mips: add nor flash write from memory block
This commit is contained in:
Stefan Mahr
Øyvind Harboe
parent
c989de0cea
commit
5d9b7cdd2b
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@ -31,6 +31,7 @@
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#include <target/arm.h>
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#include <target/arm7_9_common.h>
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#include <target/armv7m.h>
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#include <target/mips32.h>
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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@ -1278,6 +1279,12 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
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uint32_t target_code_size;
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int retval = ERROR_OK;
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/* todo: if ( (!is_armv7m(target_to_armv7m(target)) && (!is_arm(target_to_arm(target)) ) */
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if (strncmp(target_type_name(target),"mips_m4k",8) == 0)
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{
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LOG_ERROR("Your target has no flash block write support yet.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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cfi_intel_clear_status_register(bank);
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@ -1454,6 +1461,234 @@ cleanup:
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return retval;
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}
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static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffer,
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uint32_t address, uint32_t count)
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{
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struct cfi_flash_bank *cfi_info = bank->driver_priv;
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struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
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struct target *target = bank->target;
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struct reg_param reg_params[10];
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struct mips32_algorithm mips32_info;
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struct working_area *source;
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uint32_t buffer_size = 32768;
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uint32_t status;
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int retval = ERROR_OK;
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/* input parameters - */
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/* 4 A0 = source address */
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/* 5 A1 = destination address */
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/* 6 A2 = number of writes */
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/* 7 A3 = flash write command */
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/* 8 T0 = constant to mask DQ7 bits (also used for Dq5 with shift) */
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/* output parameters - */
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/* 9 T1 = 0x80 ok 0x00 bad */
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/* temp registers - */
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/* 10 T2 = value read from flash to test status */
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/* 11 T3 = holding register */
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/* unlock registers - */
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/* 12 T4 = unlock1_addr */
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/* 13 T5 = unlock1_cmd */
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/* 14 T6 = unlock2_addr */
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/* 15 T7 = unlock2_cmd */
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static const uint32_t mips_word_16_code[] = {
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/* start: */
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MIPS32_LHU(9,0,4), /* lhu $t1, ($a0) ; out = &saddr */
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MIPS32_ADDI(4,4,2), /* addi $a0, $a0, 2 ; saddr += 2 */
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MIPS32_SH(13,0,12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */
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MIPS32_SH(15,0,14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */
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MIPS32_SH(7,0,12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */
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MIPS32_SH(9,0,5), /* sh $t1, ($a1) ; *daddr = out */
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MIPS32_NOP, /* nop */
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/* busy: */
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MIPS32_LHU(10,0,5), /* lhu $t2, ($a1) ; temp1 = *daddr */
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MIPS32_XOR(11,9,10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
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MIPS32_AND(11,8,11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
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MIPS32_BNE(11,8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
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MIPS32_NOP, /* nop */
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MIPS32_SRL(10,8,2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */
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MIPS32_AND(11,10,11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */
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MIPS32_BNE(11,10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */
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MIPS32_NOP, /* nop */
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MIPS32_LHU(10,0,5), /* lhu $t2, ($a1) ; temp1 = *daddr */
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MIPS32_XOR(11,9,10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
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MIPS32_AND(11,8,11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
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MIPS32_BNE(11,8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
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MIPS32_NOP, /* nop */
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MIPS32_XOR(9,9,9), /* xor $t1, $t1, $t1 ; out = 0 */
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MIPS32_BEQ(9,0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */
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MIPS32_NOP, /* nop */
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/* cont: */
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MIPS32_ADDI(6,6,NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */
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MIPS32_BNE(6,0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */
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MIPS32_NOP, /* nop */
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MIPS32_LUI(9,0), /* lui $t1, 0 */
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MIPS32_ORI(9,9,0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */
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MIPS32_B(4), /* b done ; goto done */
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MIPS32_NOP, /* nop */
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/* cont2: */
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MIPS32_ADDI(5,5,2), /* addi $a0, $a0, 2 ; daddr += 2 */
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MIPS32_B(NEG16(33)), /* b start ; goto start */
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MIPS32_NOP, /* nop */
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/* done: */
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/*MIPS32_B(NEG16(1)), */ /* b done ; goto done */
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MIPS32_SDBBP, /* sdbbp ; break(); */
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/*MIPS32_B(NEG16(33)), */ /* b start ; goto start */
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/* MIPS32_NOP, */
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};
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mips32_info.common_magic = MIPS32_COMMON_MAGIC;
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mips32_info.isa_mode = MIPS32_ISA_MIPS32;
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int target_code_size = 0;
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const uint32_t *target_code_src = NULL;
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switch (bank->bus_width)
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{
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case 2 :
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/* Check for DQ5 support */
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if( cfi_info->status_poll_mask & (1 << 5) )
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{
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target_code_src = mips_word_16_code;
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target_code_size = sizeof(mips_word_16_code);
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}
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else
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{
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LOG_ERROR("Need DQ5 support");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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//target_code_src = mips_word_16_code_dq7only;
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//target_code_size = sizeof(mips_word_16_code_dq7only);
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}
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break;
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default:
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LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* flash write code */
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if (!cfi_info->write_algorithm)
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{
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uint8_t *target_code;
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/* convert bus-width dependent algorithm code to correct endiannes */
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target_code = malloc(target_code_size);
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if (target_code == NULL)
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{
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LOG_ERROR("Out of memory");
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return ERROR_FAIL;
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}
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cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
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/* allocate working area */
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retval = target_alloc_working_area(target, target_code_size,
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&cfi_info->write_algorithm);
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if (retval != ERROR_OK)
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{
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free(target_code);
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return retval;
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}
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/* write algorithm code to working area */
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if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
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target_code_size, target_code)) != ERROR_OK)
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{
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free(target_code);
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return retval;
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}
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free(target_code);
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}
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/* the following code still assumes target code is fixed 24*4 bytes */
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while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
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{
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buffer_size /= 2;
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if (buffer_size <= 256)
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{
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/* if we already allocated the writing code, but failed to get a
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* buffer, free the algorithm */
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if (cfi_info->write_algorithm)
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target_free_working_area(target, cfi_info->write_algorithm);
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LOG_WARNING("not enough working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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};
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init_reg_param(®_params[0], "a0", 32, PARAM_OUT);
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init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
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init_reg_param(®_params[2], "a2", 32, PARAM_OUT);
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init_reg_param(®_params[3], "a3", 32, PARAM_OUT);
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init_reg_param(®_params[4], "t0", 32, PARAM_OUT);
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init_reg_param(®_params[5], "t1", 32, PARAM_IN);
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init_reg_param(®_params[6], "t4", 32, PARAM_OUT);
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init_reg_param(®_params[7], "t5", 32, PARAM_OUT);
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init_reg_param(®_params[8], "t6", 32, PARAM_OUT);
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init_reg_param(®_params[9], "t7", 32, PARAM_OUT);
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while (count > 0)
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{
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uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
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retval = target_write_buffer(target, source->address, thisrun_count, buffer);
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if (retval != ERROR_OK)
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{
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break;
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}
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buf_set_u32(reg_params[0].value, 0, 32, source->address);
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buf_set_u32(reg_params[1].value, 0, 32, address);
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buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
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buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
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buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
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buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
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buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
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buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
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buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
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retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
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cfi_info->write_algorithm->address,
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cfi_info->write_algorithm->address + ((target_code_size) - 4),
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10000, &mips32_info);
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if (retval != ERROR_OK)
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{
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break;
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}
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status = buf_get_u32(reg_params[5].value, 0, 32);
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if (status != 0x80)
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{
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LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
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retval = ERROR_FLASH_OPERATION_FAILED;
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break;
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}
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buffer += thisrun_count;
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address += thisrun_count;
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count -= thisrun_count;
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}
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target_free_all_working_areas(target);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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destroy_reg_param(®_params[3]);
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destroy_reg_param(®_params[4]);
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destroy_reg_param(®_params[5]);
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destroy_reg_param(®_params[6]);
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destroy_reg_param(®_params[7]);
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destroy_reg_param(®_params[8]);
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destroy_reg_param(®_params[9]);
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return retval;
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}
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static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
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uint32_t address, uint32_t count)
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{
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@ -1637,6 +1872,11 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
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0xeafffffe /* b 8204 <sp_8_done> */
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};
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if (strncmp(target_type_name(target),"mips_m4k",8) == 0)
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{
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return cfi_spansion_write_block_mips(bank,buffer,address,count);
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}
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if (is_armv7m(target_to_armv7m(target))) /* Cortex-M3 target */
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{
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armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC;
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@ -110,6 +110,8 @@ struct mips32_algorithm
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#define MIPS32_OP_SH 0x29
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#define MIPS32_OP_SW 0x2B
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#define MIPS32_OP_ORI 0x0D
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#define MIPS32_OP_XOR 0x26
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#define MIPS32_OP_SRL 0x03
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#define MIPS32_COP0_MF 0x00
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#define MIPS32_COP0_MT 0x04
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@ -135,10 +137,12 @@ struct mips32_algorithm
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#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
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#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
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#define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
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#define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
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#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
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#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
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#define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
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#define MIPS32_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
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#define MIPS32_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
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/* ejtag specific instructions */
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#define MIPS32_DRET 0x4200001F
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