interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

clang: fix warning about use of unitialized variable 

this was a false positive, silence it.

Change-Id: I432e0c466c94cf8fd6bbf0ea153c8501a8a261eb
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/126
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Øyvind Harboe 2011-10-26 22:26:44 +02:00 committed by Spencer Oliver
parent 2036c2aaae
commit e6d979eefc
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/arm_simulator.c
View File

@ -519,7 +519,7 @@ static int arm_simulate_step_core(struct target *target,
/* load register instructions */
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
{
uint32_t load_address = 0, modified_address = 0, load_value;
uint32_t load_address = 0, modified_address = 0, load_value = 0;
uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
/* adjust Rn in case the PC is being read */