stlink: better handle target reset/events
This makes the stlink target use the std armv7m_arch_state giving consistent OpenOCD output. Added debug entry handler so we get debug entry reason. Change-Id: Ia3c1380fd5033a8e541b0d45a7c3559f1b05957d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/379 Tested-by: jenkins
This commit is contained in:
Spencer Oliver
parent
c527882121
commit
7f1ab30b88
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@ -2,6 +2,9 @@
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* Copyright (C) 2011 by Mathias Kuester *
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* Mathias Kuester <kesmtp@freenet.de> *
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* *
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* Copyright (C) 2011 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -187,6 +190,16 @@ static int stm32_stlink_store_core_reg_u32(struct target *target,
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return ERROR_OK;
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}
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static int stm32_stlink_examine_debug_reason(struct target *target)
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{
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP)) {
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target->debug_reason = DBG_REASON_BREAKPOINT;
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}
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return ERROR_OK;
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}
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static int stm32_stlink_init_arch_info(struct target *target,
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struct cortex_m3_common *cortex_m3,
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struct jtag_tap *tap)
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@ -201,6 +214,8 @@ static int stm32_stlink_init_arch_info(struct target *target,
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armv7m->load_core_reg_u32 = stm32_stlink_load_core_reg_u32;
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armv7m->store_core_reg_u32 = stm32_stlink_store_core_reg_u32;
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armv7m->examine_debug_reason = stm32_stlink_examine_debug_reason;
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return ERROR_OK;
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}
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@ -229,8 +244,6 @@ static int stm32_stlink_target_create(struct target *target,
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return ERROR_OK;
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}
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static int stm32_stlink_poll(struct target *target);
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static int stm32_stlink_examine(struct target *target)
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{
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int retval, i;
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@ -248,8 +261,6 @@ static int stm32_stlink_examine(struct target *target)
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if (!target_was_examined(target)) {
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target_set_examined(target);
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stm32_stlink_poll(target);
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LOG_INFO("IDCODE %x", target->tap->idcode);
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/* Read from Device Identification Registers */
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@ -296,8 +307,9 @@ static int stm32_stlink_examine(struct target *target)
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static int stm32_stlink_load_context(struct target *target)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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int num_regs = armv7m->core_cache->num_regs;
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for (unsigned i = 0; i < 23; i++) {
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for (int i = 0; i < num_regs; i++) {
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if (!armv7m->core_cache->reg_list[i].valid)
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armv7m->read_core_reg(target, i);
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}
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@ -305,6 +317,57 @@ static int stm32_stlink_load_context(struct target *target)
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return ERROR_OK;
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}
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static int stlink_debug_entry(struct target *target)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct arm *arm = &armv7m->arm;
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struct reg *r;
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uint32_t xPSR;
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int retval;
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retval = armv7m->examine_debug_reason(target);
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if (retval != ERROR_OK)
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return retval;
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stm32_stlink_load_context(target);
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r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
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xPSR = buf_get_u32(r->value, 0, 32);
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/* Are we in an exception handler */
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if (xPSR & 0x1FF) {
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armv7m->core_mode = ARMV7M_MODE_HANDLER;
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armv7m->exception_number = (xPSR & 0x1FF);
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arm->core_mode = ARM_MODE_HANDLER;
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arm->map = armv7m_msp_reg_map;
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} else {
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unsigned control = buf_get_u32(armv7m->core_cache
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->reg_list[ARMV7M_CONTROL].value, 0, 2);
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/* is this thread privileged? */
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armv7m->core_mode = control & 1;
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arm->core_mode = armv7m->core_mode
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? ARM_MODE_USER_THREAD
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: ARM_MODE_THREAD;
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/* which stack is it using? */
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if (control & 2)
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arm->map = armv7m_psp_reg_map;
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else
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arm->map = armv7m_msp_reg_map;
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armv7m->exception_number = 0;
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}
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LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
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armv7m_mode_strings[armv7m->core_mode],
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*(uint32_t *)(arm->pc->value),
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target_state_name(target));
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return retval;
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}
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static int stm32_stlink_poll(struct target *target)
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{
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enum target_state state;
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@ -314,8 +377,7 @@ static int stm32_stlink_poll(struct target *target)
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state = stlink_if->layout->api->state(stlink_if->fd);
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if (state == TARGET_UNKNOWN) {
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LOG_ERROR
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("jtag status contains invalid mode value - communication failure");
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LOG_ERROR("jtag status contains invalid mode value - communication failure");
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return ERROR_TARGET_FAILURE;
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}
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@ -323,23 +385,17 @@ static int stm32_stlink_poll(struct target *target)
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return ERROR_OK;
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if (state == TARGET_HALTED) {
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
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target->state = state;
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stm32_stlink_load_context(target);
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stlink_debug_entry(target);
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LOG_INFO("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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LOG_DEBUG("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
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}
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return ERROR_OK;
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}
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static int stm32_stlink_arch_state(struct target *target)
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{
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int stm32_stlink_assert_reset(struct target *target)
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{
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int res;
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@ -361,9 +417,12 @@ static int stm32_stlink_assert_reset(struct target *target)
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/* registers are now invalid */
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register_cache_invalidate(armv7m->core_cache);
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stm32_stlink_load_context(target);
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target->state = TARGET_HALTED;
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if (target->reset_halt) {
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target->state = TARGET_RESET;
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target->debug_reason = DBG_REASON_DBGRQ;
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} else {
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target->state = TARGET_HALTED;
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}
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return ERROR_OK;
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}
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@ -486,7 +545,7 @@ static int stm32_stlink_resume(struct target *target, int current,
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target->state = TARGET_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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return ERROR_OK;
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}
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@ -545,7 +604,7 @@ static int stm32_stlink_step(struct target *target, int current,
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target->debug_reason = DBG_REASON_SINGLESTEP;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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stm32_stlink_load_context(target);
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stlink_debug_entry(target);
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LOG_INFO("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
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@ -669,7 +728,7 @@ struct target_type stm32_stlink_target = {
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.examine = stm32_stlink_examine,
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.poll = stm32_stlink_poll,
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.arch_state = stm32_stlink_arch_state,
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.arch_state = armv7m_arch_state,
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.assert_reset = stm32_stlink_assert_reset,
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.deassert_reset = stm32_stlink_deassert_reset,
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