cleanup trailing whitespaces
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@ -3,7 +3,7 @@
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* rodrigorosa.LG@gmail.com *
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* *
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* Based on a file written by: *
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* Kevin McGuire *
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* Kevin McGuire *
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* Marcel Wijlaars *
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* Michael Ashton *
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* *
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@ -102,7 +102,7 @@ static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first,
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for(int i = first;i<last;i++)
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bank->sectors[i].is_protected = 1;
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}
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}else{
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}else{
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retval = dsp5680xx_f_unlock(bank->target);
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if(retval == ERROR_OK)
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for(int i = first;i<last;i++)
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@ -2935,7 +2935,7 @@ static int minimodule_init(void)
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LOG_ERROR("couldn't initialize FT2232 with 'minimodule' layout");
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return ERROR_JTAG_INIT_FAILED;
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}
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nSRST = 0x20;
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@ -726,11 +726,11 @@ static int dsp5680xx_read(struct target * target, uint32_t address, unsigned siz
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err_check_propagate(retval);
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context.flush = 0;
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}
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context.flush = 1;
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retval = dsp5680xx_execute_queue();
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err_check_propagate(retval);
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return retval;
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}
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@ -913,7 +913,7 @@ static int dsp5680xx_read_buffer(struct target * target, uint32_t address, uint3
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return ERROR_OK;
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}
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// read_buffer is called when the verify_image command is executed.
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// The "/2" solves the byte/word addressing issue.
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// The "/2" solves the byte/word addressing issue.
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return dsp5680xx_read(target,address,2,size/2,buffer);
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}
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@ -1120,14 +1120,14 @@ int dsp5680xx_f_erase_check(struct target * target, uint8_t * erased,uint32_t se
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*erased = (uint8_t)(hfm_ustat&HFM_USTAT_MASK_BLANK);
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return retval;
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}
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static int erase_sector(struct target * target, int sector, uint16_t * hfm_ustat){
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int retval;
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retval = dsp5680xx_f_execute_command(target,HFM_PAGE_ERASE,HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2,0,hfm_ustat,1);
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err_check_propagate(retval);
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return retval;
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}
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static int mass_erase(struct target * target, uint16_t * hfm_ustat){
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int retval;
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retval = dsp5680xx_f_execute_command(target,HFM_MASS_ERASE,0,0,hfm_ustat,1);
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@ -114,13 +114,13 @@
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#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
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#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
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#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
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#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
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#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
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#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
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#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
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#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
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#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
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#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
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#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
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#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
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#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
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//----------------------------------------------------------------
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@ -179,7 +179,7 @@
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//----------------------------------------------------------------
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#define MC568013_EONCE_OBASE_ADDR 0xFF
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// The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
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#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
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#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
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#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR
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#define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
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//----------------------------------------------------------------
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