Add GDB remote target description support for ARM4
This commit adds support for passing the ARM4 target description to GDB when enabling gdb_target_description, in order to expose all banked registers. Change-Id: Id618bc6226f00fe83397ea28888a84b64b09cafd Signed-off-by: Luca BRUNO <lucab@debian.org> Reviewed-on: http://openocd.zylin.com/1810 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Luca BRUNO
Spencer Oliver
parent
3271e6d4d5
commit
2efb1f14f6
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@ -45,7 +45,7 @@ enum {
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ARMV4_5_SPSR_SVC = 34,
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ARMV4_5_SPSR_ABT = 35,
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ARMV4_5_SPSR_UND = 36,
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ARM_SPSR_MON = 39,
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ARM_SPSR_MON = 41,
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};
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static const uint8_t arm_usr_indices[17] = {
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@ -73,7 +73,7 @@ static const uint8_t arm_und_indices[3] = {
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};
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static const uint8_t arm_mon_indices[3] = {
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37, 38, ARM_SPSR_MON,
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39, 40, ARM_SPSR_MON,
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};
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static const struct {
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@ -258,69 +258,81 @@ static const struct {
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* (Exception modes have both CPSR and SPSR registers ...)
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*/
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unsigned cookie;
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unsigned gdb_index;
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enum arm_mode mode;
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} arm_core_regs[] = {
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/* IMPORTANT: we guarantee that the first eight cached registers
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* correspond to r0..r7, and the fifteenth to PC, so that callers
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* don't need to map them.
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*/
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{ .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
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{ .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
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{ .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
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{ .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
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{ .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
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{ .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
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{ .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
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{ .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
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{ .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
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{ .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
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{ .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
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{ .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
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{ .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
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{ .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
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{ .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
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{ .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
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/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
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* them as MODE_ANY creates special cases. (ANY means
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* "not mapped" elsewhere; here it's "everything but FIQ".)
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*/
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{ .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
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{ .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
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{ .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
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{ .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
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{ .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
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{ .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
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{ .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
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{ .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
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{ .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
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{ .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
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/* Historical GDB mapping of indices:
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* - 13-14 are sp and lr, but banked counterparts are used
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* - 16-24 are left for deprecated 8 FPA + 1 FPS
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* - 25 is the cpsr
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*/
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/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
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{ .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
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{ .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
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{ .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
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{ .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
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/* guaranteed to be at index 15 */
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{ .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
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{ .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
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{ .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
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{ .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
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{ .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
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{ .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
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{ .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
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{ .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
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{ .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
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{ .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
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{ .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
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{ .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
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{ .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
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{ .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
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{ .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
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{ .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
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{ .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
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{ .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
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{ .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
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{ .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
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{ .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
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{ .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
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{ .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
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{ .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
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{ .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
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{ .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
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{ .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
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{ .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
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{ .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
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{ .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
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{ .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
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{ .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
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{ .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
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{ .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
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{ .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
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{ .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
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{ .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
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{ .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
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{ .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
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{ .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
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{ .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
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{ .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
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{ .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
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{ .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
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/* These are only used for GDB target description, banked registers are accessed instead */
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{ .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
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{ .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
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/* These exist only when the Security Extension (TrustZone) is present */
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{ .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
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{ .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
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{ .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
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{ .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
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{ .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
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{ .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
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};
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/* map core mode (USR, FIQ, ...) and register number to
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@ -448,6 +460,10 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
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static const uint8_t arm_gdb_dummy_fp_value[12];
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static struct reg_feature arm_gdb_dummy_fp_features = {
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.name = "net.sourceforge.openocd.fake_fpa"
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};
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/**
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* Dummy FPA registers are required to support GDB on ARM.
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* Register packets require eight obsolete FPA register values.
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@ -459,6 +475,10 @@ struct reg arm_gdb_dummy_fp_reg = {
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.value = (uint8_t *) arm_gdb_dummy_fp_value,
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.valid = 1,
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.size = 96,
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.exist = false,
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.number = 16,
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.feature = &arm_gdb_dummy_fp_features,
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.group = "fake_fpa",
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};
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static const uint8_t arm_gdb_dummy_fps_value[4];
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@ -472,6 +492,10 @@ struct reg arm_gdb_dummy_fps_reg = {
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.value = (uint8_t *) arm_gdb_dummy_fps_value,
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.valid = 1,
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.size = 32,
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.exist = false,
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.number = 24,
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.feature = &arm_gdb_dummy_fp_features,
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.group = "fake_fpa",
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};
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static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
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@ -582,10 +606,40 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
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reg_arch_info[i].arm = arm;
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reg_list[i].name = (char *) arm_core_regs[i].name;
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reg_list[i].number = arm_core_regs[i].gdb_index;
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reg_list[i].size = 32;
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reg_list[i].value = ®_arch_info[i].value;
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reg_list[i].type = &arm_reg_type;
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reg_list[i].arch_info = ®_arch_info[i];
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reg_list[i].exist = true;
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/* This really depends on the calling convention in use */
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reg_list[i].caller_save = false;
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/* Registers data type, as used by GDB target description */
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reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
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switch (arm_core_regs[i].cookie) {
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case 13:
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reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
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break;
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case 14:
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case 15:
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reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
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break;
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default:
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reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
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break;
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}
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/* let GDB shows banked registers only in "info all-reg" */
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reg_list[i].feature = malloc(sizeof(struct reg_feature));
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if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
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reg_list[i].feature->name = "org.gnu.gdb.arm.core";
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reg_list[i].group = "general";
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} else {
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reg_list[i].feature->name = "net.sourceforge.openocd.banked";
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reg_list[i].group = "banked";
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}
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cache->num_regs++;
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}
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@ -1055,26 +1109,61 @@ int arm_get_gdb_reg_list(struct target *target,
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enum target_register_class reg_class)
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{
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struct arm *arm = target_to_arm(target);
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int i;
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unsigned int i;
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if (!is_arm_mode(arm->core_mode)) {
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LOG_ERROR("not a valid arm core mode - communication failure?");
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return ERROR_FAIL;
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}
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*reg_list_size = 26;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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switch (reg_class) {
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case REG_CLASS_GENERAL:
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*reg_list_size = 26;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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for (i = 0; i < 16; i++)
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(*reg_list)[i] = arm_reg_current(arm, i);
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for (i = 0; i < 16; i++)
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(*reg_list)[i] = arm_reg_current(arm, i);
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for (i = 16; i < 24; i++)
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(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
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/* For GDB compatibility, take FPA registers size into account and zero-fill it*/
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for (i = 16; i < 24; i++)
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(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
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(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
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(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
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(*reg_list)[25] = arm->cpsr;
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(*reg_list)[25] = arm->cpsr;
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return ERROR_OK;
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return ERROR_OK;
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break;
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case REG_CLASS_ALL:
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*reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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for (i = 0; i < 16; i++)
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(*reg_list)[i] = arm_reg_current(arm, i);
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for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
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int reg_index = arm->core_cache->reg_list[i].number;
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if (!(arm_core_regs[i].mode == ARM_MODE_MON
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&& arm->core_type != ARM_MODE_MON))
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(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
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}
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/* When we supply the target description, there is no need for fake FPA */
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for (i = 16; i < 24; i++) {
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(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
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(*reg_list)[i]->size = 0;
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}
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(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
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(*reg_list)[24]->size = 0;
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return ERROR_OK;
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break;
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default:
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LOG_ERROR("not a valid register class type in query.");
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return ERROR_FAIL;
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break;
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}
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}
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/* wait for execution to complete and check exit point */
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