interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

pic32mx: false pending at low core clock 

To show up the fail try to step with the core clock set to 31.25Khz
and with a ftdi/hs adapter or with a wiggler, -not with ft2232-.
The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail.

The code exits with error because the pracc address is at 0x0.

It also fails when using the "all" register, but in this case the code works without any message because the
pracc address is at 0xff202004 when it fails.

I never saw this fail with the core clock set to 500Khz or higher, but ...

The workaround simply puts a 1 ms delay after the execution of the DERET instruction.

Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1139
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Salvador Arroyo 2013-02-17 19:23:16 +01:00 committed by Spencer Oliver
parent 70fb53f90b
commit c185a5b724
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/target/mips_ejtag.c
View File

@ -245,7 +245,12 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
inst = MIPS32_DRET;
/* execute our dret instruction */
return mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
int retval = mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
/* pic32mx workaround, false pending at low core clock */
jtag_add_sleep(1000);
return retval;
}
int mips_ejtag_init(struct mips_ejtag *ejtag_info)