Added support for ARMv7-M in arm io.
Added support for ARMv7-M targets in arm_nandwrite and arm_nandread. Change-Id: Iab1d78d401f735e191c6a8519f3619035a300fae Signed-off-by: Henrik Nilsson <henrik.nilsson@bytequest.se> Reviewed-on: http://openocd.zylin.com/1188 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Henrik Nilsson
Spencer Oliver
parent
704fc7eb3d
commit
70fb53f90b
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@ -0,0 +1,60 @@
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/***************************************************************************
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* Copyright (C) 2013 by Henrik Nilsson *
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* henrik.nilsson@bytequest.se *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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.text
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.syntax unified
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.arch armv7-m
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.thumb
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.thumb_func
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.align 4
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/* Inputs:
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* r0 buffer address
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* r1 NAND data address (byte wide)
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* r2 buffer length
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*/
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read:
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ldrb r3, [r1]
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strb r3, [r0], #1
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subs r2, r2, #1
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bne read
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done_read:
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bkpt #0
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.align 4
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/* Inputs:
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* r0 NAND data address (byte wide)
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* r1 buffer address
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* r2 buffer length
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*/
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write:
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ldrb r3, [r1], #1
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strb r3, [r0]
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subs r2, r2, #1
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bne write
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done_write:
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bkpt #0
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.end
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@ -28,6 +28,7 @@
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#include "arm_io.h"
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#include <helper/binarybuffer.h>
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#include <target/arm.h>
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#include <target/armv7m.h>
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#include <target/algorithm.h>
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/**
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@ -78,14 +79,13 @@ static int arm_code_to_working_area(struct target *target,
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/**
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* ARM-specific bulk write from buffer to address of 8-bit wide NAND.
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* For now this only supports ARMv4 and ARMv5 cores.
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* For now this supports ARMv4,ARMv5 and ARMv7-M cores.
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*
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* Enhancements to target_run_algorithm() could enable:
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* - ARMv6 and ARMv7 cores in ARM mode
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*
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* Different code fragments could handle:
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* - Thumb2 cores like Cortex-M (needs different byteswapping)
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* - 16-bit wide data (needs different setup too)
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* - 16-bit wide data (needs different setup)
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*
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* @param nand Pointer to the arm_nand_data struct that defines the I/O
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* @param data Pointer to the data to be copied to flash
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@ -95,7 +95,9 @@ static int arm_code_to_working_area(struct target *target,
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int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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{
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struct target *target = nand->target;
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struct arm_algorithm algo;
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struct arm_algorithm armv4_5_algo;
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struct armv7m_algorithm armv7m_algo;
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void *arm_algo;
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struct arm *arm = target->arch_info;
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struct reg_param reg_params[3];
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uint32_t target_buf;
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@ -107,7 +109,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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* r1 buffer address
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* r2 buffer length
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*/
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static const uint32_t code[] = {
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static const uint32_t code_armv4_5[] = {
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0xe4d13001, /* s: ldrb r3, [r1], #1 */
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0xe5c03000, /* strb r3, [r0] */
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0xe2522001, /* subs r2, r2, #1 */
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@ -117,8 +119,41 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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0xe1200070, /* e: bkpt #0 */
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};
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/* Inputs:
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* r0 NAND data address (byte wide)
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* r1 buffer address
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* r2 buffer length
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*
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* see contrib/loaders/flash/armv7m_io.s for src
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*/
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static const uint32_t code_armv7m[] = {
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0x3b01f811,
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0x3a017003,
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0xaffaf47f,
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0xbf00be00,
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};
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int target_code_size = 0;
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const uint32_t *target_code_src = NULL;
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/* set up algorithm */
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if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */
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armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
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armv7m_algo.core_mode = ARM_MODE_THREAD;
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arm_algo = &armv7m_algo;
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target_code_size = sizeof(code_armv7m);
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target_code_src = code_armv7m;
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} else {
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armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
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armv4_5_algo.core_mode = ARM_MODE_SVC;
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armv4_5_algo.core_state = ARM_STATE_ARM;
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arm_algo = &armv4_5_algo;
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target_code_size = sizeof(code_armv4_5);
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target_code_src = code_armv4_5;
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}
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if (nand->op != ARM_NAND_WRITE || !nand->copy_area) {
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retval = arm_code_to_working_area(target, code, sizeof(code),
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retval = arm_code_to_working_area(target, target_code_src, target_code_size,
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nand->chunk_size, &nand->copy_area);
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if (retval != ERROR_OK)
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return retval;
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@ -127,16 +162,12 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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nand->op = ARM_NAND_WRITE;
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/* copy data to work area */
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target_buf = nand->copy_area->address + sizeof(code);
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target_buf = nand->copy_area->address + target_code_size;
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retval = target_write_buffer(target, target_buf, size, data);
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if (retval != ERROR_OK)
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return retval;
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/* set up algorithm and parameters */
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algo.common_magic = ARM_COMMON_MAGIC;
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algo.core_mode = ARM_MODE_SVC;
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algo.core_state = ARM_STATE_ARM;
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/* set up parameters */
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init_reg_param(®_params[0], "r0", 32, PARAM_IN);
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init_reg_param(®_params[1], "r1", 32, PARAM_IN);
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init_reg_param(®_params[2], "r2", 32, PARAM_IN);
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@ -147,11 +178,11 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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/* armv4 must exit using a hardware breakpoint */
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if (arm->is_armv4)
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exit_var = nand->copy_area->address + sizeof(code) - 4;
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exit_var = nand->copy_area->address + target_code_size - 4;
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/* use alg to write data from work area to NAND chip */
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retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
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nand->copy_area->address, exit_var, 1000, &algo);
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nand->copy_area->address, exit_var, 1000, arm_algo);
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if (retval != ERROR_OK)
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LOG_ERROR("error executing hosted NAND write");
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@ -174,7 +205,9 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
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{
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struct target *target = nand->target;
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struct arm_algorithm algo;
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struct arm_algorithm armv4_5_algo;
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struct armv7m_algorithm armv7m_algo;
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void *arm_algo;
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struct arm *arm = target->arch_info;
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struct reg_param reg_params[3];
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uint32_t target_buf;
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@ -186,7 +219,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
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* r1 NAND data address (byte wide)
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* r2 buffer length
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*/
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static const uint32_t code[] = {
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static const uint32_t code_armv4_5[] = {
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0xe5d13000, /* s: ldrb r3, [r1] */
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0xe4c03001, /* strb r3, [r0], #1 */
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0xe2522001, /* subs r2, r2, #1 */
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@ -196,22 +229,51 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
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0xe1200070, /* e: bkpt #0 */
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};
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/* Inputs:
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* r0 buffer address
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* r1 NAND data address (byte wide)
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* r2 buffer length
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*
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* see contrib/loaders/flash/armv7m_io.s for src
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*/
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static const uint32_t code_armv7m[] = {
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0xf800780b,
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0x3a013b01,
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0xaffaf47f,
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0xbf00be00,
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};
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int target_code_size = 0;
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const uint32_t *target_code_src = NULL;
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/* set up algorithm */
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if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */
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armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
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armv7m_algo.core_mode = ARM_MODE_THREAD;
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arm_algo = &armv7m_algo;
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target_code_size = sizeof(code_armv7m);
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target_code_src = code_armv7m;
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} else {
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armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
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armv4_5_algo.core_mode = ARM_MODE_SVC;
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armv4_5_algo.core_state = ARM_STATE_ARM;
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arm_algo = &armv4_5_algo;
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target_code_size = sizeof(code_armv4_5);
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target_code_src = code_armv4_5;
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}
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/* create the copy area if not yet available */
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if (nand->op != ARM_NAND_READ || !nand->copy_area) {
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retval = arm_code_to_working_area(target, code, sizeof(code),
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retval = arm_code_to_working_area(target, target_code_src, target_code_size,
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nand->chunk_size, &nand->copy_area);
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if (retval != ERROR_OK)
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return retval;
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}
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nand->op = ARM_NAND_READ;
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target_buf = nand->copy_area->address + sizeof(code);
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/* set up algorithm and parameters */
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algo.common_magic = ARM_COMMON_MAGIC;
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algo.core_mode = ARM_MODE_SVC;
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algo.core_state = ARM_STATE_ARM;
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target_buf = nand->copy_area->address + target_code_size;
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/* set up parameters */
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init_reg_param(®_params[0], "r0", 32, PARAM_IN);
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init_reg_param(®_params[1], "r1", 32, PARAM_IN);
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init_reg_param(®_params[2], "r2", 32, PARAM_IN);
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@ -222,11 +284,11 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
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/* armv4 must exit using a hardware breakpoint */
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if (arm->is_armv4)
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exit_var = nand->copy_area->address + sizeof(code) - 4;
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exit_var = nand->copy_area->address + target_code_size - 4;
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/* use alg to write data from NAND chip to work area */
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retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
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nand->copy_area->address, exit_var, 1000, &algo);
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nand->copy_area->address, exit_var, 1000, arm_algo);
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if (retval != ERROR_OK)
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LOG_ERROR("error executing hosted NAND read");
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