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riscv-openocd
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Merge remote branch 'origin/master' into HEAD

This commit is contained in:
Øyvind Harboe 2011-04-01 13:02:24 +02:00
parent a0b83e82f7 977df18f50
commit 3b7c9585db
36 changed files with 200 additions and 203 deletions
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6
doc/openocd.texi
View File

@ -5788,7 +5788,7 @@ Loads an image stored in memory by @command{fast_load_image} to the
current target. Must be preceeded by fast_load_image.
@end deffn
@deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
@deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
Normally you should be using @command{load_image} or GDB load. However, for
testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
host), storing the image in memory and uploading the image to the target
@ -5800,10 +5800,10 @@ separately.
@end deffn
@anchor{load_image}
@deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}] @option{min_addr} @option{max_length}]
@deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
Load image from file @var{filename} to target memory offset by @var{address} from its load address.
The file format may optionally be specified
(@option{bin}, @option{ihex}, or @option{elf}).
(@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
In addition the following arguments may be specifed:
@var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
@var{max_length} - maximum number of bytes to load.

9
src/flash/nor/pic32mx.c
View File

@ -774,11 +774,9 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
}
/* unlock/erase device */
mchip_cmd = MCHP_ASERT_RST;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
mchip_cmd = MCHP_ERASE;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_ERASE);
do {
mchip_cmd = MCHP_STATUS;
@ -791,8 +789,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
alive_sleep(1);
} while ((mchip_cmd & (1 << 2)) || (!(mchip_cmd & (1 << 3))));
mchip_cmd = MCHP_DE_ASSERT_RST;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
/* select ejtag tap */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);

2
src/jtag/minidummy/minidummy.c
View File

@ -154,7 +154,7 @@ int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state
return ERROR_OK;
}
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, int little, int count)
{
int i;
for (i = 0; i < count; i++)

6
src/jtag/zy1000/zy1000.c
View File

@ -853,7 +853,7 @@ static void jtag_pre_post_bits(struct jtag_tap *tap, int *pre, int *post)
TAP_IDLE);
*/
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, int little, int count)
{
#if 0
int i;
@ -895,7 +895,7 @@ void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer,
int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, const uint32_t * data, size_t count)
{
/* bypass bits before and after */
int pre_bits;
@ -905,7 +905,7 @@ int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opc
if ((pre_bits > 32) || (post_bits > 32))
{
int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *, uint32_t, uint32_t *, size_t);
int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *, uint32_t, const uint32_t *, size_t);
return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
} else
{

67
src/openocd.c
View File

@ -301,6 +301,42 @@ struct command_context *setup_command_handler(Jim_Interp *interp)
return cmd_ctx;
}
static int main2(int argc, char *argv[], struct command_context *cmd_ctx)
{
int ret;
if (parse_cmdline_args(cmd_ctx, argc, argv) != ERROR_OK)
return EXIT_FAILURE;
if (server_preinit() != ERROR_OK)
return EXIT_FAILURE;
ret = parse_config_file(cmd_ctx);
if (ret != ERROR_OK)
return EXIT_FAILURE;
ret = server_init(cmd_ctx);
if (ERROR_OK != ret)
return EXIT_FAILURE;
ret = command_run_line(cmd_ctx, "init_targets");
if (ERROR_OK != ret)
ret = EXIT_FAILURE;
if (init_at_startup)
{
ret = command_run_line(cmd_ctx, "init");
if (ERROR_OK != ret)
return EXIT_FAILURE;
}
server_loop(cmd_ctx);
server_quit();
return ret;
}
/* normally this is the main() function entry, but if OpenOCD is linked
* into application, then this fn will not be invoked, but rather that
* application will have it's own implementation of main(). */
@ -326,36 +362,7 @@ int openocd_main(int argc, char *argv[])
command_context_mode(cmd_ctx, COMMAND_CONFIG);
command_set_output_handler(cmd_ctx, configuration_output_handler, NULL);
if (parse_cmdline_args(cmd_ctx, argc, argv) != ERROR_OK)
return EXIT_FAILURE;
if (server_preinit() != ERROR_OK)
return EXIT_FAILURE;
ret = parse_config_file(cmd_ctx);
if (ret != ERROR_OK)
return EXIT_FAILURE;
ret = server_init(cmd_ctx);
if (ERROR_OK != ret)
return EXIT_FAILURE;
ret = command_run_line(cmd_ctx, "init_targets");
if (ERROR_OK != ret)
ret = EXIT_FAILURE;
if (init_at_startup)
{
ret = command_run_line(cmd_ctx, "init");
if (ERROR_OK != ret)
ret = EXIT_FAILURE;
}
/* handle network connections */
if (ERROR_OK == ret)
server_loop(cmd_ctx);
server_quit();
ret = main2(argc, argv, cmd_ctx);
unregister_all_commands(cmd_ctx, NULL);

2
src/svf/svf.c
View File

@ -219,7 +219,7 @@ static size_t svf_command_buffer_size = 0;
static int svf_line_number = 1;
static int svf_getline (char **lineptr, size_t *n, FILE *stream);
#define SVF_MAX_BUFFER_SIZE_TO_COMMIT (4 * 1024)
#define SVF_MAX_BUFFER_SIZE_TO_COMMIT (1024 * 1024)
static uint8_t *svf_tdi_buffer = NULL, *svf_tdo_buffer = NULL, *svf_mask_buffer = NULL;
static int svf_buffer_index = 0, svf_buffer_size = 0;
static int svf_quiet = 0;

6
src/target/arm11.c
View File

@ -925,7 +925,7 @@ static int arm11_read_memory(struct target *target, uint32_t address, uint32_t s
*/
static int arm11_write_memory_inner(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer,
uint32_t count, const uint8_t *buffer,
bool no_increment)
{
int retval;
@ -1072,7 +1072,7 @@ static int arm11_write_memory_inner(struct target *target,
static int arm11_write_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
/* pointer increment matters only for multi-unit writes ...
* not e.g. to a "reset the chip" controller.
@ -1083,7 +1083,7 @@ static int arm11_write_memory(struct target *target,
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
static int arm11_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t count, const uint8_t *buffer)
{
if (target->state != TARGET_HALTED)
{

2
src/target/arm720t.c
View File

@ -330,7 +330,7 @@ static int arm720t_read_phys_memory(struct target *target,
}
static int arm720t_write_phys_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct arm720t_common *arm720t = target_to_arm720(target);

8
src/target/arm7_9_common.c
View File

@ -2431,7 +2431,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
return ERROR_OK;
}
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
@ -2655,7 +2655,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
}
static int dcc_count;
static uint8_t *dcc_buffer;
static const uint8_t *dcc_buffer;
static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
@ -2667,7 +2667,7 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int
int little = target->endianness == TARGET_LITTLE_ENDIAN;
int count = dcc_count;
uint8_t *buffer = dcc_buffer;
const uint8_t *buffer = dcc_buffer;
if (count > 2)
{
/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
@ -2720,7 +2720,7 @@ static const uint32_t dcc_code[] =
0xeafffff9 /* b w */
};
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);

4
src/target/arm7_9_common.h
View File

@ -134,8 +134,8 @@ int arm7_9_halt(struct target *target);
int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer);
int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);

4
src/target/arm920t.c
View File

@ -602,7 +602,7 @@ static int arm920t_read_phys_memory(struct target *target,
static int arm920t_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
struct arm920t_common *arm920t = target_to_arm920(target);
@ -613,7 +613,7 @@ static int arm920t_write_phys_memory(struct target *target,
/** Writes a buffer, in the specified word size, with current MMU settings. */
int arm920t_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */

2
src/target/arm920t.h
View File

@ -63,7 +63,7 @@ int arm920t_soft_reset_halt(struct target *target);
int arm920t_read_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm920t_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
int arm920t_post_debug_entry(struct target *target);
void arm920t_pre_restore_context(struct target *target);
int arm920t_get_ttb(struct target *target, uint32_t *result);

4
src/target/arm926ejs.c
View File

@ -626,7 +626,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
/** Writes a buffer, in the specified word size, with current MMU settings. */
int arm926ejs_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
@ -693,7 +693,7 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
static int arm926ejs_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);

2
src/target/arm926ejs.h
View File

@ -50,7 +50,7 @@ int arm926ejs_init_arch_info(struct target *target,
struct arm926ejs_common *arm926ejs, struct jtag_tap *tap);
int arm926ejs_arch_state(struct target *target);
int arm926ejs_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
int arm926ejs_soft_reset_halt(struct target *target);
extern const struct command_registration arm926ejs_command_handlers[];

2
src/target/arm946e.c
View File

@ -512,7 +512,7 @@ uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
/** Writes a buffer, in the specified word size, with current MMU settings. */
int arm946e_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;

43
src/target/arm_adi_v5.c
View File

@ -270,11 +270,11 @@ int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
* Write a buffer in target order (little endian) *
* *
*****************************************************************************/
int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
{
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
uint32_t adr = address;
uint8_t* pBuffer = buffer;
const uint8_t* pBuffer = buffer;
count >>= 2;
wcount = count;
@ -343,7 +343,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
}
static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
uint8_t *buffer, int count, uint32_t address)
const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
@ -424,7 +424,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
return retval;
}
int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
@ -456,7 +456,7 @@ int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
}
static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
uint8_t *buffer, int count, uint32_t address)
const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
@ -532,7 +532,7 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
return retval;
}
int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
@ -935,21 +935,21 @@ int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
}
int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address)
const uint8_t *buffer, int count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_write_buf_u8(swjdp, buffer, count, address);
}
int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address)
const uint8_t *buffer, int count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_write_buf_u16(swjdp, buffer, count, address);
}
int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address)
const uint8_t *buffer, int count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_write_buf_u32(swjdp, buffer, count, address);
@ -1083,23 +1083,11 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
}
struct broken_cpu {
uint32_t dbgbase;
uint32_t apid;
uint32_t idcode;
uint32_t correct_dbgbase;
char *model;
} broken_cpus[] = {
{ 0x80000000, 0x04770002, 0x1ba00477, 0x60000000, "imx51" },
{ 0x80040000, 0x04770002, 0x3b95c02f, 0x80000000, "omap4430" },
};
int dap_get_debugbase(struct adiv5_dap *dap, int ap,
uint32_t *out_dbgbase, uint32_t *out_apid)
{
uint32_t ap_old;
int retval;
unsigned int i;
uint32_t dbgbase, apid, idcode;
/* AP address is in bits 31:24 of DP_SELECT */
@ -1131,19 +1119,6 @@ int dap_get_debugbase(struct adiv5_dap *dap, int ap,
if (tap == NULL || !tap->hasidcode)
return ERROR_OK;
/* Some CPUs are messed up, so fixup if needed. */
for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
if (broken_cpus[i].dbgbase == dbgbase &&
broken_cpus[i].apid == apid &&
broken_cpus[i].idcode == idcode) {
LOG_WARNING("Found broken CPU (%s), trying to fixup "
"ROM Table location from 0x%08x to 0x%08x",
broken_cpus[i].model, dbgbase,
broken_cpus[i].correct_dbgbase);
dbgbase = broken_cpus[i].correct_dbgbase;
break;
}
dap_ap_select(dap, ap_old);
/* The asignment happens only here to prevent modification of these

12
src/target/arm_adi_v5.h
View File

@ -376,11 +376,11 @@ int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
const uint8_t *buffer, int count, uint32_t address);
int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
const uint8_t *buffer, int count, uint32_t address);
int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
const uint8_t *buffer, int count, uint32_t address);
@ -405,11 +405,11 @@ int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address);
int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address);
const uint8_t *buffer, int count, uint32_t address);
int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address);
const uint8_t *buffer, int count, uint32_t address);
int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address);
const uint8_t *buffer, int count, uint32_t address);

2
src/target/armv4_5_mmu.c
View File

@ -149,7 +149,7 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *
return retval;
}
int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;

4
src/target/armv4_5_mmu.h
View File

@ -28,7 +28,7 @@ struct armv4_5_mmu_common
{
int (*get_ttb)(struct target *target, uint32_t *result);
int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
int (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
struct armv4_5_cache_common armv4_5_cache;
@ -46,7 +46,7 @@ int armv4_5_mmu_read_physical(struct target *target,
int armv4_5_mmu_write_physical(struct target *target,
struct armv4_5_mmu_common *armv4_5_mmu,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
enum
{

4
src/target/avr32_ap7k.c
View File

@ -515,7 +515,7 @@ static int avr32_ap7k_read_memory(struct target *target, uint32_t address,
}
static int avr32_ap7k_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
@ -600,7 +600,7 @@ static int avr32_ap7k_examine(struct target *target)
}
static int avr32_ap7k_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
LOG_ERROR("%s: implement me", __func__);

6
src/target/avr32_mem.c
View File

@ -152,7 +152,7 @@ int avr32_jtag_read_memory8(struct avr32_jtag *jtag_info,
}
int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint32_t *buffer)
uint32_t addr, int count, const uint32_t *buffer)
{
int i, retval;
uint32_t data;
@ -173,7 +173,7 @@ int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info,
}
int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint16_t *buffer)
uint32_t addr, int count, const uint16_t *buffer)
{
int i, retval;
uint32_t data;
@ -248,7 +248,7 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info,
}
int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint8_t *buffer)
uint32_t addr, int count, const uint8_t *buffer)
{
int i, j, retval;
uint32_t data;

6
src/target/avr32_mem.h
View File

@ -27,11 +27,11 @@ int avr32_jtag_read_memory8(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint8_t *buffer);
int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint32_t *buffer);
uint32_t addr, int count, const uint32_t *buffer);
int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint16_t *buffer);
uint32_t addr, int count, const uint16_t *buffer);
int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info,
uint32_t addr, int count, uint8_t *buffer);
uint32_t addr, int count, const uint8_t *buffer);
#endif /* AVR32_MEM */

6
src/target/cortex_a.c
View File

@ -1587,7 +1587,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
static int cortex_a8_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
@ -1748,7 +1748,7 @@ static int cortex_a8_write_phys_memory(struct target *target,
}
static int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int enabled = 0;
uint32_t virt, phys;
@ -1774,7 +1774,7 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
}
static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
return cortex_a8_write_memory(target, address, 4, count, buffer);
}

4
src/target/cortex_m3.c
View File

@ -1618,7 +1618,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
}
static int cortex_m3_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = &armv7m->dap;
@ -1642,7 +1642,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
}
static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
return cortex_m3_write_memory(target, address, 4, count, buffer);
}

10
src/target/dsp563xx.c
View File

@ -1482,13 +1482,13 @@ static int dsp563xx_read_memory_default(struct target *target, uint32_t address,
return dsp563xx_read_memory(target, dsp563xx_get_default_memory(), address, size, count, buffer);
}
static int dsp563xx_write_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer)
static int dsp563xx_write_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer)
{
int err;
struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
uint32_t i, x;
uint32_t data, move_cmd = 0;
uint8_t *b;
const uint8_t *b;
LOG_DEBUG("memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", mem_type,address, size, count);
@ -1557,7 +1557,7 @@ static int dsp563xx_write_memory_core(struct target *target, int mem_type, uint3
return ERROR_OK;
}
static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer)
static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer)
{
int err;
uint32_t i,i1;
@ -1615,12 +1615,12 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a
return ERROR_OK;
}
static int dsp563xx_write_memory_default(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer)
static int dsp563xx_write_memory_default(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer)
{
return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, size, count, buffer);
}
static int dsp563xx_bulk_write_memory_default(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
static int dsp563xx_bulk_write_memory_default(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
{
return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, 4, count, buffer);
}

2
src/target/embeddedice.c
View File

@ -637,7 +637,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
* This is an inner loop of the open loop DCC write of data to target
*/
void embeddedice_write_dcc(struct jtag_tap *tap,
int reg_addr, uint8_t *buffer, int little, int count)
int reg_addr, const uint8_t *buffer, int little, int count)
{
int i;

2
src/target/embeddedice.h
View File

@ -130,6 +130,6 @@ static __inline__ void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg
TAP_IDLE);
}
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count);
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, int little, int count);
#endif /* EMBEDDED_ICE_H */

2
src/target/feroceon.c
View File

@ -460,7 +460,7 @@ static int feroceon_examine_debug_reason(struct target *target)
}
static int feroceon_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t count, const uint8_t *buffer)
{
int retval;
struct arm *armv4_5 = target->arch_info;

32
src/target/mips32_pracc.c
View File

@ -449,7 +449,7 @@ static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr,
uint32_t *param_out = malloc(count * sizeof(uint32_t));
int i;
// int retval;
int retval = ERROR_OK;
int blocksize;
int bytesread;
uint32_t param_in[2];
@ -465,7 +465,7 @@ static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr,
param_in[0] = addr;
param_in[1] = blocksize;
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
ARRAY_SIZE(param_in), param_in, count, param_out, 1);
// count -= blocksize;
@ -480,7 +480,7 @@ static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr,
free(param_out);
return ERROR_OK;
return retval;
}
static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
@ -526,7 +526,7 @@ static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr,
uint32_t *param_out = malloc(count * sizeof(uint32_t));
int i;
// int retval;
int retval = ERROR_OK;
int blocksize;
int bytesread;
uint32_t param_in[2];
@ -542,7 +542,7 @@ static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr,
param_in[0] = addr;
param_in[1] = blocksize;
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
ARRAY_SIZE(param_in), param_in, count, param_out, 1);
// count -= blocksize;
@ -557,7 +557,7 @@ static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr,
free(param_out);
return ERROR_OK;
return retval;
}
int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
@ -619,12 +619,13 @@ static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr
memcpy(&param_in[2], buf, count * sizeof(uint32_t));
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
int retval;
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
count + 2, param_in, 0, NULL, 1);
free(param_in);
return ERROR_OK;
return retval;
}
static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
@ -653,10 +654,8 @@ static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr,
param_in[0] = addr;
param_in[1] = *buf;
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
ARRAY_SIZE(param_in), param_in, 0, NULL, 1);
return ERROR_OK;
}
static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
@ -709,12 +708,13 @@ static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr
param_in[i + 2] = buf[i];
}
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
int retval;
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
count + 2, param_in, 0, NULL, 1);
free(param_in);
return ERROR_OK;
return retval;
}
static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
@ -768,7 +768,7 @@ static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr,
param_in[i + 2] = buf[i];
}
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
count + 2, param_in, 0, NULL, 1);
free(param_in);
@ -840,7 +840,7 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
int retval;
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
MIPS32NUMCOREREGS, regs, 0, NULL, 1);
return retval;
@ -915,7 +915,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
int retval;
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
0, NULL, MIPS32NUMCOREREGS, regs, 1);
return retval;

62
src/target/mips_ejtag.c
View File

@ -28,13 +28,12 @@
#include "mips32.h"
#include "mips_ejtag.h"
int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
{
struct jtag_tap *tap;
tap = ejtag_info->tap;
if (tap == NULL)
return ERROR_FAIL;
assert(tap != NULL);
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr)
{
@ -48,8 +47,6 @@ int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
jtag_add_ir_scan(tap, &field, TAP_IDLE);
}
return ERROR_OK;
}
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
@ -98,9 +95,8 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
{
struct jtag_tap *tap;
tap = ejtag_info->tap;
assert(tap != NULL);
if (tap == NULL)
return ERROR_FAIL;
struct scan_field field;
uint8_t t[4], r[4];
int retval;
@ -129,9 +125,8 @@ int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
{
struct jtag_tap *tap;
tap = ejtag_info->tap;
assert(tap != NULL);
if (tap == NULL)
return ERROR_FAIL;
struct scan_field field;
uint8_t t[4] = {0, 0, 0, 0}, r[4];
int retval;
@ -151,11 +146,24 @@ int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
*data = buf_get_u32(field.in_value, 0, 32);
keep_alive();
return ERROR_OK;
}
void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
{
struct jtag_tap *tap;
tap = ejtag_info->tap;
assert(tap != NULL);
struct scan_field field;
field.num_bits = 8;
field.out_value = &data;
field.in_value = NULL;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
}
static int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
{
static const uint32_t code[] = {
@ -167,10 +175,8 @@ static int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */
};
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
0, NULL, 0, NULL, 1);
return ERROR_OK;
return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
0, NULL, 0, NULL, 1);
}
static int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
@ -192,10 +198,8 @@ static int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
};
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
0, NULL, 0, NULL, 1);
return ERROR_OK;
}
int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
@ -219,7 +223,10 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
LOG_DEBUG("Failed to enter Debug Mode!");
{
LOG_ERROR("Failed to enter Debug Mode!");
return ERROR_FAIL;
}
return ERROR_OK;
}
@ -230,9 +237,7 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
inst = MIPS32_DRET;
/* execute our dret instruction */
mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
return ERROR_OK;
return mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
}
int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
@ -254,17 +259,18 @@ int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
};
mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
0, NULL, 1, debug_reg, 1);
return ERROR_OK;
}
int mips_ejtag_init(struct mips_ejtag *ejtag_info)
{
uint32_t ejtag_version;
int retval;
mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
/* get ejtag version */
@ -311,9 +317,7 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_
{
struct jtag_tap *tap;
tap = ejtag_info->tap;
if (tap == NULL)
return ERROR_FAIL;
assert(tap != NULL);
struct scan_field fields[2];
uint8_t spracc = 0;

3
src/target/mips_ejtag.h
View File

@ -131,12 +131,13 @@ struct mips_ejtag
int fast_access_save;
};
int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
int new_instr);
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);

33
src/target/mips_m4k.c
View File

@ -254,18 +254,14 @@ static int mips_m4k_assert_reset(struct target *target)
{
if (mips_m4k->is_pic32mx)
{
uint32_t mchip_cmd;
LOG_DEBUG("Using MTAP reset to reset processor...");
/* use microchip specific MTAP reset */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
mchip_cmd = MCHP_ASERT_RST;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
mchip_cmd = MCHP_DE_ASSERT_RST;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
}
else
@ -872,7 +868,7 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address,
}
static int mips_m4k_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
@ -940,7 +936,9 @@ static int mips_m4k_examine(struct target *target)
if (!target_was_examined(target))
{
mips_ejtag_get_idcode(ejtag_info, &idcode);
retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
if (retval != ERROR_OK)
return retval;
ejtag_info->idcode = idcode;
if (((idcode >> 1) & 0x7FF) == 0x29)
@ -964,7 +962,7 @@ static int mips_m4k_examine(struct target *target)
}
static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
@ -1002,19 +1000,34 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
ejtag_info->fast_access_save = -1;
}
uint8_t * t = NULL;
/* TAP data register is loaded LSB first (little endian) */
if (target->endianness == TARGET_BIG_ENDIAN)
{
t = malloc(count * sizeof(uint32_t));
if (t == NULL)
{
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
uint32_t i, t32;
for(i = 0; i < (count * 4); i += 4)
{
t32 = be_to_h_u32((uint8_t *) &buffer[i]);
h_u32_to_le(&buffer[i], t32);
h_u32_to_le(&t[i], t32);
}
buffer = t;
}
retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
count, (uint32_t*) (void *)buffer);
if (t != NULL)
free(t);
if (retval != ERROR_OK)
{
/* FASTDATA access failed, try normal memory write */

20
src/target/target.c
View File

@ -49,7 +49,7 @@
static int target_read_buffer_default(struct target *target, uint32_t address,
uint32_t size, uint8_t *buffer);
static int target_write_buffer_default(struct target *target, uint32_t address,
uint32_t size, uint8_t *buffer);
uint32_t size, const uint8_t *buffer);
static int target_array2mem(Jim_Interp *interp, struct target *target,
int argc, Jim_Obj *const *argv);
static int target_mem2array(Jim_Interp *interp, struct target *target,
@ -615,7 +615,7 @@ const char *target_type_name(struct target *target)
return target->type->name;
}
static int target_write_memory_imp(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int target_write_memory_imp(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
if (!target_was_examined(target))
{
@ -705,19 +705,19 @@ static int target_read_phys_memory(struct target *target,
}
int target_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
return target->type->write_memory(target, address, size, count, buffer);
}
static int target_write_phys_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
return target->type->write_phys_memory(target, address, size, count, buffer);
}
int target_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t count, const uint8_t *buffer)
{
return target->type->bulk_write_memory(target, address, count, buffer);
}
@ -783,7 +783,7 @@ err_read_phys_memory(struct target *target, uint32_t address,
static int
err_write_phys_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
LOG_ERROR("Not implemented: %s", __func__);
return ERROR_FAIL;
@ -1340,7 +1340,7 @@ int target_arch_state(struct target *target)
* mode respectively, otherwise data is handled as quickly as
* possible
*/
int target_write_buffer(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer)
int target_write_buffer(struct target *target, uint32_t address, uint32_t size, const uint8_t *buffer)
{
LOG_DEBUG("writing buffer of %i byte at 0x%8.8x",
(int)size, (unsigned)address);
@ -1367,7 +1367,7 @@ int target_write_buffer(struct target *target, uint32_t address, uint32_t size,
return target->type->write_buffer(target, address, size, buffer);
}
static int target_write_buffer_default(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer)
static int target_write_buffer_default(struct target *target, uint32_t address, uint32_t size, const uint8_t *buffer)
{
int retval = ERROR_OK;
@ -2390,10 +2390,10 @@ COMMAND_HANDLER(handle_md_command)
}
typedef int (*target_write_fn)(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
static int target_write_memory_fast(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
return target_write_buffer(target, address, size * count, buffer);
}

6
src/target/target.h
View File

@ -408,7 +408,7 @@ int target_read_memory(struct target *target,
* This routine is wrapper for target->type->write_memory.
*/
int target_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
/**
* Write @a count items of 4 bytes to the memory of @a target at
@ -418,7 +418,7 @@ int target_write_memory(struct target *target,
* This routine is wrapper for target->type->bulk_write_memory.
*/
int target_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer);
uint32_t address, uint32_t count, const uint8_t *buffer);
/*
* Write to target memory using the virtual address.
@ -445,7 +445,7 @@ int target_bulk_write_memory(struct target *target,
* peripheral registers which do not support byte operations.
*/
int target_write_buffer(struct target *target,
uint32_t address, uint32_t size, uint8_t *buffer);
uint32_t address, uint32_t size, const uint8_t *buffer);
int target_read_buffer(struct target *target,
uint32_t address, uint32_t size, uint8_t *buffer);
int target_checksum_memory(struct target *target,

10
src/target/target_type.h
View File

@ -112,25 +112,25 @@ struct target_type
* directly, use target_read_memory() instead.
*/
int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int (*write_memory_imp)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int (*write_memory_imp)(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
/**
* Target memory write callback. Do @b not call this function
* directly, use target_write_memory() instead.
*/
int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
/* Default implementation will do some fancy alignment to improve performance, target can override */
int (*read_buffer)(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer);
/* Default implementation will do some fancy alignment to improve performance, target can override */
int (*write_buffer)(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer);
int (*write_buffer)(struct target *target, uint32_t address, uint32_t size, const uint8_t *buffer);
/**
* Write target memory in multiples of 4 bytes, optimized for
* writing large quantities of data. Do @b not call this
* function directly, use target_bulk_write_memory() instead.
*/
int (*bulk_write_memory)(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
int (*bulk_write_memory)(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer);
int (*checksum_memory)(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum);
int (*blank_check_memory)(struct target *target, uint32_t address, uint32_t count, uint32_t* blank);
@ -225,7 +225,7 @@ struct target_type
/*
* same as read_phys_memory, except that it writes...
*/
int (*write_phys_memory)(struct target *target, uint32_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer);
int (*write_phys_memory)(struct target *target, uint32_t phys_address, uint32_t size, uint32_t count, const uint8_t *buffer);
int (*mmu)(struct target *target, int *enabled);

8
src/target/xscale.c
View File

@ -528,7 +528,7 @@ static int xscale_write_rx(struct target *target)
}
/* send count elements of size byte to the debug handler */
static int xscale_send(struct target *target, uint8_t *buffer, int count, int size)
static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t t[3];
@ -1937,7 +1937,7 @@ static int xscale_read_phys_memory(struct target *target, uint32_t address,
}
static int xscale_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct xscale_common *xscale = target_to_xscale(target);
int retval;
@ -2016,7 +2016,7 @@ static int xscale_write_memory(struct target *target, uint32_t address,
}
static int xscale_write_phys_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct xscale_common *xscale = target_to_xscale(target);
@ -2031,7 +2031,7 @@ static int xscale_write_phys_memory(struct target *target, uint32_t address,
}
static int xscale_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
uint32_t count, const uint8_t *buffer)
{
return xscale_write_memory(target, address, 4, count, buffer);
}